1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020  Realtek Corporation
41 static const u8 mss_signature[] = {0x4D, 0x53, 0x53, 0x4B, 0x50, 0x4F, 0x4F, 0x4C};
44 	.ver = 0x00,
45 	.list = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
46 		 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
47 		 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
48 		 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
85 	u32 header_len = 0;  in rtw89_fw_h2c_alloc_skb()
86 	u32 h2c_desc_size = rtwdev->chip->h2c_desc_size;  in rtw89_fw_h2c_alloc_skb()
95 	memset(skb->data, 0, len);  in rtw89_fw_h2c_alloc_skb()
112 	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;  in rtw89_fw_check_rdy()
116 	ret = read_poll_timeout_atomic(mac->fwdl_get_status, val,  in rtw89_fw_check_rdy()
123 			return -EINVAL;  in rtw89_fw_check_rdy()
127 			return -EINVAL;  in rtw89_fw_check_rdy()
131 			return -EINVAL;  in rtw89_fw_check_rdy()
135 			return -EBUSY;  in rtw89_fw_check_rdy()
139 	set_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);  in rtw89_fw_check_rdy()
141 	return 0;  in rtw89_fw_check_rdy()
148 	const struct rtw89_chip_info *chip = rtwdev->chip;  in rtw89_fw_hdr_parser_v0()
150 	struct rtw89_fw_secure *sec = &rtwdev->fw.sec;  in rtw89_fw_hdr_parser_v0()
161 		return -EINVAL;  in rtw89_fw_hdr_parser_v0()
163 	info->section_num = le32_get_bits(fw_hdr->w6, FW_HDR_W6_SEC_NUM);  in rtw89_fw_hdr_parser_v0()
164 	base_hdr_len = struct_size(fw_hdr, sections, info->section_num);  in rtw89_fw_hdr_parser_v0()
165 	info->dynamic_hdr_en = le32_get_bits(fw_hdr->w7, FW_HDR_W7_DYN_HDR);  in rtw89_fw_hdr_parser_v0()
166 	info->idmem_share_mode = le32_get_bits(fw_hdr->w7, FW_HDR_W7_IDMEM_SHARE_MODE);  in rtw89_fw_hdr_parser_v0()
168 	if (info->dynamic_hdr_en) {  in rtw89_fw_hdr_parser_v0()
169 		info->hdr_len = le32_get_bits(fw_hdr->w3, FW_HDR_W3_LEN);  in rtw89_fw_hdr_parser_v0()
170 		info->dynamic_hdr_len = info->hdr_len - base_hdr_len;  in rtw89_fw_hdr_parser_v0()
172 		if (le32_to_cpu(fwdynhdr->hdr_len) != info->dynamic_hdr_len) {  in rtw89_fw_hdr_parser_v0()
174 			return -EINVAL;  in rtw89_fw_hdr_parser_v0()
177 		info->hdr_len = base_hdr_len;  in rtw89_fw_hdr_parser_v0()
178 		info->dynamic_hdr_len = 0;  in rtw89_fw_hdr_parser_v0()
181 	bin = fw + info->hdr_len;  in rtw89_fw_hdr_parser_v0()
184 	section_info = info->section_info;  in rtw89_fw_hdr_parser_v0()
185 	for (i = 0; i < info->section_num; i++) {  in rtw89_fw_hdr_parser_v0()
186 		section = &fw_hdr->sections[i];  in rtw89_fw_hdr_parser_v0()
187 		section_info->type =  in rtw89_fw_hdr_parser_v0()
188 			le32_get_bits(section->w1, FWSECTION_HDR_W1_SECTIONTYPE);  in rtw89_fw_hdr_parser_v0()
189 		section_info->len = le32_get_bits(section->w1, FWSECTION_HDR_W1_SEC_SIZE);  in rtw89_fw_hdr_parser_v0()
191 		if (le32_get_bits(section->w1, FWSECTION_HDR_W1_CHECKSUM))  in rtw89_fw_hdr_parser_v0()
192 			section_info->len += FWDL_SECTION_CHKSUM_LEN;  in rtw89_fw_hdr_parser_v0()
193 		section_info->redl = le32_get_bits(section->w1, FWSECTION_HDR_W1_REDL);  in rtw89_fw_hdr_parser_v0()
194 		section_info->dladdr =  in rtw89_fw_hdr_parser_v0()
195 			le32_get_bits(section->w0, FWSECTION_HDR_W0_DL_ADDR) & 0x1fffffff;  in rtw89_fw_hdr_parser_v0()
196 		section_info->addr = bin;  in rtw89_fw_hdr_parser_v0()
198 		if (section_info->type == FWDL_SECURITY_SECTION_TYPE) {  in rtw89_fw_hdr_parser_v0()
199 			section_info->mssc =  in rtw89_fw_hdr_parser_v0()
200 				le32_get_bits(section->w2, FWSECTION_HDR_W2_MSSC);  in rtw89_fw_hdr_parser_v0()
207 			if (sec->secure_boot && chip->chip_id == RTL8852B)  in rtw89_fw_hdr_parser_v0()
208 				section_info->len_override = 960;  in rtw89_fw_hdr_parser_v0()
210 			section_info->mssc = 0;  in rtw89_fw_hdr_parser_v0()
211 			mssc_len = 0;  in rtw89_fw_hdr_parser_v0()
215 			    "section[%d] type=%d len=0x%-6x mssc=%d mssc_len=%d addr=%tx\n",  in rtw89_fw_hdr_parser_v0()
216 			    i, section_info->type, section_info->len,  in rtw89_fw_hdr_parser_v0()
217 			    section_info->mssc, mssc_len, bin - fw);  in rtw89_fw_hdr_parser_v0()
219 			    "           ignore=%d key_addr=%p (0x%tx) key_len=%d key_idx=%d\n",  in rtw89_fw_hdr_parser_v0()
220 			    section_info->ignore, section_info->key_addr,  in rtw89_fw_hdr_parser_v0()
221 			    section_info->key_addr ?  in rtw89_fw_hdr_parser_v0()
222 			    section_info->key_addr - section_info->addr : 0,  in rtw89_fw_hdr_parser_v0()
223 			    section_info->key_len, section_info->key_idx);  in rtw89_fw_hdr_parser_v0()
225 		bin += section_info->len + mssc_len;  in rtw89_fw_hdr_parser_v0()
231 		return -EINVAL;  in rtw89_fw_hdr_parser_v0()
234 	return 0;  in rtw89_fw_hdr_parser_v0()
241 	struct rtw89_fw_secure *sec = &rtwdev->fw.sec;  in __get_mssc_key_idx()
247 	if (sec->mss_dev_type == RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF) {  in __get_mssc_key_idx()
248 		if (!mss_hdr->defen)  in __get_mssc_key_idx()
249 			return -ENOENT;  in __get_mssc_key_idx()
251 		mss_sel_idx = sec->mss_cust_idx * le16_to_cpu(mss_hdr->msskey_num_max) +  in __get_mssc_key_idx()
252 			      sec->mss_key_num;  in __get_mssc_key_idx()
254 		if (mss_hdr->defen)  in __get_mssc_key_idx()
257 			mss_sel_idx = 0;  in __get_mssc_key_idx()
258 		mss_sel_idx += sec->mss_dev_type * le16_to_cpu(mss_hdr->msskey_num_max) *  in __get_mssc_key_idx()
259 						   le16_to_cpu(mss_hdr->msscust_max) +  in __get_mssc_key_idx()
260 			       sec->mss_cust_idx * le16_to_cpu(mss_hdr->msskey_num_max) +  in __get_mssc_key_idx()
261 			       sec->mss_key_num;  in __get_mssc_key_idx()
265 	sel_bit_idx = mss_sel_idx & 0x7;  in __get_mssc_key_idx()
268 		return -EFAULT;  in __get_mssc_key_idx()
270 	if (!(mss_hdr->rmp_tbl[sel_byte_idx] & BIT(sel_bit_idx)))  in __get_mssc_key_idx()
271 		return -ENOENT;  in __get_mssc_key_idx()
273 	*key_idx = hweight8(mss_hdr->rmp_tbl[sel_byte_idx] & (BIT(sel_bit_idx) - 1));  in __get_mssc_key_idx()
275 	for (i = 0; i < sel_byte_idx; i++)  in __get_mssc_key_idx()
276 		*key_idx += hweight8(mss_hdr->rmp_tbl[i]);  in __get_mssc_key_idx()
278 	return 0;  in __get_mssc_key_idx()
292 	const struct rtw89_fw_mss_pool_hdr *mss_hdr = content + section_info->len;  in __parse_formatted_mssc()
295 	const struct rtw89_fw_mss_pool_hdr *mss_hdr = (const void *)(content + section_info->len);  in __parse_formatted_mssc()
298 	struct rtw89_fw_secure *sec = &rtwdev->fw.sec;  in __parse_formatted_mssc()
305 	if (memcmp(mss_signature, mss_hdr->signature, sizeof(mss_signature)) != 0) {  in __parse_formatted_mssc()
307 		return -ENOENT;  in __parse_formatted_mssc()
310 	if (mss_hdr->rmpfmt == MSS_POOL_RMP_TBL_BITMASK) {  in __parse_formatted_mssc()
311 		rmp_tbl_size = (le16_to_cpu(mss_hdr->msskey_num_max) *  in __parse_formatted_mssc()
312 				le16_to_cpu(mss_hdr->msscust_max) *  in __parse_formatted_mssc()
313 				mss_hdr->mssdev_max) >> 3;  in __parse_formatted_mssc()
314 		if (mss_hdr->defen)  in __parse_formatted_mssc()
318 			  mss_hdr->rmpfmt);  in __parse_formatted_mssc()
319 		return -EINVAL;  in __parse_formatted_mssc()
322 	if (rmp_tbl_size + sizeof(*mss_hdr) != le32_to_cpu(mss_hdr->key_raw_offset)) {  in __parse_formatted_mssc()
323 		rtw89_err(rtwdev, "[ERR] MSS Key Pool Format Error:0x%X + 0x%X != 0x%X\n",  in __parse_formatted_mssc()
325 			  le32_to_cpu(mss_hdr->key_raw_offset));  in __parse_formatted_mssc()
326 		return -EINVAL;  in __parse_formatted_mssc()
329 	key_sign_len = le16_to_cpu(section_content->key_sign_len.v) >> 2;  in __parse_formatted_mssc()
333 	if (info->dsp_checksum)  in __parse_formatted_mssc()
337 		    le16_to_cpu(mss_hdr->keypair_num) * key_sign_len;  in __parse_formatted_mssc()
339 	if (!sec->secure_boot)  in __parse_formatted_mssc()
342 	sb_sel_ver = get_unaligned_le32(&section_content->sb_sel_ver.v);  in __parse_formatted_mssc()
343 	if (sb_sel_ver && sb_sel_ver != sec->sb_sel_mgn)  in __parse_formatted_mssc()
350 	section_info->key_addr = content + section_info->len +  in __parse_formatted_mssc()
351 				le32_to_cpu(mss_hdr->key_raw_offset) +  in __parse_formatted_mssc()
353 	section_info->key_len = key_sign_len;  in __parse_formatted_mssc()
354 	section_info->key_idx = real_key_idx;  in __parse_formatted_mssc()
357 	if (info->secure_section_exist) {  in __parse_formatted_mssc()
358 		section_info->ignore = true;  in __parse_formatted_mssc()
359 		return 0;  in __parse_formatted_mssc()
362 	info->secure_section_exist = true;  in __parse_formatted_mssc()
364 	return 0;  in __parse_formatted_mssc()
367 	section_info->ignore = true;  in __parse_formatted_mssc()
369 	return 0;  in __parse_formatted_mssc()
377 	const struct rtw89_fw_blacklist *chip_blacklist = rtwdev->chip->fw_blacklist;  in __check_secure_blacklist()
379 	struct rtw89_fw_secure *sec = &rtwdev->fw.sec;  in __check_secure_blacklist()
383 	if (!sec->secure_boot)  in __check_secure_blacklist()
384 		return 0;  in __check_secure_blacklist()
386 	if (!info->secure_section_exist || section_info->ignore)  in __check_secure_blacklist()
387 		return 0;  in __check_secure_blacklist()
391 		return -ENOENT;  in __check_secure_blacklist()
394 	byte_idx = section_content->blacklist.bit_in_chip_list >> 3;  in __check_secure_blacklist()
395 	bit_mask = BIT(section_content->blacklist.bit_in_chip_list & 0x7);  in __check_secure_blacklist()
397 	if (section_content->blacklist.ver > chip_blacklist->ver) {  in __check_secure_blacklist()
399 			   section_content->blacklist.ver, chip_blacklist->ver);  in __check_secure_blacklist()
400 		return -EINVAL;  in __check_secure_blacklist()
403 	if (chip_blacklist->list[byte_idx] & bit_mask) {  in __check_secure_blacklist()
405 			   section_content->blacklist.ver);  in __check_secure_blacklist()
406 		return -EPERM;  in __check_secure_blacklist()
409 	return 0;  in __check_secure_blacklist()
422 	struct rtw89_fw_secure *sec = &rtwdev->fw.sec;  in __parse_security_section()
425 	if ((section_info->mssc & FORMATTED_MSSC_MASK) == FORMATTED_MSSC) {  in __parse_security_section()
429 			return -EINVAL;  in __parse_security_section()
431 		*mssc_len = section_info->mssc * FWDL_SECURITY_SIGLEN;  in __parse_security_section()
432 		if (info->dsp_checksum)  in __parse_security_section()
433 			*mssc_len += section_info->mssc * FWDL_SECURITY_CHKSUM_LEN;  in __parse_security_section()
435 		if (sec->secure_boot) {  in __parse_security_section()
436 			if (sec->mss_idx >= section_info->mssc) {  in __parse_security_section()
438 					  sec->mss_idx, section_info->mssc);  in __parse_security_section()
439 				return -EFAULT;  in __parse_security_section()
441 			section_info->key_addr = content + section_info->len +  in __parse_security_section()
442 						 sec->mss_idx * FWDL_SECURITY_SIGLEN;  in __parse_security_section()
443 			section_info->key_len = FWDL_SECURITY_SIGLEN;  in __parse_security_section()
446 		info->secure_section_exist = true;  in __parse_security_section()
452 	return 0;  in __parse_security_section()
469 	info->section_num = le32_get_bits(fw_hdr->w6, FW_HDR_V1_W6_SEC_NUM);  in rtw89_fw_hdr_parser_v1()
470 	info->dsp_checksum = le32_get_bits(fw_hdr->w6, FW_HDR_V1_W6_DSP_CHKSUM);  in rtw89_fw_hdr_parser_v1()
471 	base_hdr_len = struct_size(fw_hdr, sections, info->section_num);  in rtw89_fw_hdr_parser_v1()
472 	info->dynamic_hdr_en = le32_get_bits(fw_hdr->w7, FW_HDR_V1_W7_DYN_HDR);  in rtw89_fw_hdr_parser_v1()
473 	info->idmem_share_mode = le32_get_bits(fw_hdr->w7, FW_HDR_V1_W7_IDMEM_SHARE_MODE);  in rtw89_fw_hdr_parser_v1()
475 	if (info->dynamic_hdr_en) {  in rtw89_fw_hdr_parser_v1()
476 		info->hdr_len = le32_get_bits(fw_hdr->w5, FW_HDR_V1_W5_HDR_SIZE);  in rtw89_fw_hdr_parser_v1()
477 		info->dynamic_hdr_len = info->hdr_len - base_hdr_len;  in rtw89_fw_hdr_parser_v1()
479 		if (le32_to_cpu(fwdynhdr->hdr_len) != info->dynamic_hdr_len) {  in rtw89_fw_hdr_parser_v1()
481 			return -EINVAL;  in rtw89_fw_hdr_parser_v1()
484 		info->hdr_len = base_hdr_len;  in rtw89_fw_hdr_parser_v1()
485 		info->dynamic_hdr_len = 0;  in rtw89_fw_hdr_parser_v1()
488 	bin = fw + info->hdr_len;  in rtw89_fw_hdr_parser_v1()
491 	section_info = info->section_info;  in rtw89_fw_hdr_parser_v1()
492 	for (i = 0; i < info->section_num; i++) {  in rtw89_fw_hdr_parser_v1()
493 		section = &fw_hdr->sections[i];  in rtw89_fw_hdr_parser_v1()
495 		section_info->type =  in rtw89_fw_hdr_parser_v1()
496 			le32_get_bits(section->w1, FWSECTION_HDR_V1_W1_SECTIONTYPE);  in rtw89_fw_hdr_parser_v1()
497 		section_info->len =  in rtw89_fw_hdr_parser_v1()
498 			le32_get_bits(section->w1, FWSECTION_HDR_V1_W1_SEC_SIZE);  in rtw89_fw_hdr_parser_v1()
499 		if (le32_get_bits(section->w1, FWSECTION_HDR_V1_W1_CHECKSUM))  in rtw89_fw_hdr_parser_v1()
500 			section_info->len += FWDL_SECTION_CHKSUM_LEN;  in rtw89_fw_hdr_parser_v1()
501 		section_info->redl = le32_get_bits(section->w1, FWSECTION_HDR_V1_W1_REDL);  in rtw89_fw_hdr_parser_v1()
502 		section_info->dladdr =  in rtw89_fw_hdr_parser_v1()
503 			le32_get_bits(section->w0, FWSECTION_HDR_V1_W0_DL_ADDR);  in rtw89_fw_hdr_parser_v1()
504 		section_info->addr = bin;  in rtw89_fw_hdr_parser_v1()
506 		if (section_info->type == FWDL_SECURITY_SECTION_TYPE) {  in rtw89_fw_hdr_parser_v1()
507 			section_info->mssc =  in rtw89_fw_hdr_parser_v1()
508 				le32_get_bits(section->w2, FWSECTION_HDR_V1_W2_MSSC);  in rtw89_fw_hdr_parser_v1()
515 			section_info->mssc = 0;  in rtw89_fw_hdr_parser_v1()
516 			mssc_len = 0;  in rtw89_fw_hdr_parser_v1()
520 			    "section[%d] type=%d len=0x%-6x mssc=%d mssc_len=%d addr=%tx\n",  in rtw89_fw_hdr_parser_v1()
521 			    i, section_info->type, section_info->len,  in rtw89_fw_hdr_parser_v1()
522 			    section_info->mssc, mssc_len, bin - fw);  in rtw89_fw_hdr_parser_v1()
524 			    "           ignore=%d key_addr=%p (0x%tx) key_len=%d key_idx=%d\n",  in rtw89_fw_hdr_parser_v1()
525 			    section_info->ignore, section_info->key_addr,  in rtw89_fw_hdr_parser_v1()
526 			    section_info->key_addr ?  in rtw89_fw_hdr_parser_v1()
527 			    section_info->key_addr - section_info->addr : 0,  in rtw89_fw_hdr_parser_v1()
528 			    section_info->key_len, section_info->key_idx);  in rtw89_fw_hdr_parser_v1()
530 		bin += section_info->len + mssc_len;  in rtw89_fw_hdr_parser_v1()
536 		return -EINVAL;  in rtw89_fw_hdr_parser_v1()
539 	if (!info->secure_section_exist)  in rtw89_fw_hdr_parser_v1()
542 	return 0;  in rtw89_fw_hdr_parser_v1()
549 	const u8 *fw = fw_suit->data;  in rtw89_fw_hdr_parser()
550 	u32 len = fw_suit->size;  in rtw89_fw_hdr_parser()
553 		rtw89_err(rtwdev, "fw type %d isn't recognized\n", fw_suit->type);  in rtw89_fw_hdr_parser()
554 		return -ENOENT;  in rtw89_fw_hdr_parser()
557 	switch (fw_suit->hdr_ver) {  in rtw89_fw_hdr_parser()
558 	case 0:  in rtw89_fw_hdr_parser()
563 		return -ENOENT;  in rtw89_fw_hdr_parser()
573 	if (sizeof(*mfw_hdr) > firmware->size)  in rtw89_mfw_get_hdr_ptr()
576 	mfw_hdr = (const struct rtw89_mfw_hdr *)&firmware->data[0];  in rtw89_mfw_get_hdr_ptr()
578 	if (mfw_hdr->sig != RTW89_MFW_SIG)  in rtw89_mfw_get_hdr_ptr()
589 	const void *mfw = firmware->data;
591 	const u8 *mfw = firmware->data;
593 	u32 mfw_len = firmware->size;
594 	u8 fw_nr = mfw_hdr->fw_nr;
597 	if (fw_nr == 0) {
599 		return -ENOENT;
602 	ptr = &mfw_hdr->info[fw_nr];
610 		return -EFAULT;
613 	return 0;
620 	struct rtw89_fw_info *fw_info = &rtwdev->fw;
621 	const struct firmware *firmware = fw_info->req.firmware;
624 	const u8 *mfw = firmware->data;
625 	u32 mfw_len = firmware->size;
634 			return -EINVAL;
635 		fw_suit->data = mfw;
636 		fw_suit->size = mfw_len;
637 		return 0;
644 	for (i = 0; i < mfw_hdr->fw_nr; i++) {
645 		tmp = &mfw_hdr->info[i];
646 		if (tmp->type != type)
657 		if (tmp->cv <= rtwdev->hal.cv && !tmp->mp) {
658 			if (!mfw_info || mfw_info->cv < tmp->cv)
668 	return -ENOENT;
671 	fw_suit->data = mfw + le32_to_cpu(mfw_info->shift);
672 	fw_suit->size = le32_to_cpu(mfw_info->size);
674 	if (fw_suit->data + fw_suit->size > mfw + mfw_len) {
676 		return -EFAULT;
679 	return 0;
684 	struct rtw89_fw_info *fw_info = &rtwdev->fw;
685 	const struct firmware *firmware = fw_info->req.firmware;
694 		return 0;
701 	mfw_info = &mfw_hdr->info[mfw_hdr->fw_nr - 1];
702 	size = le32_to_cpu(mfw_info->shift) + le32_to_cpu(mfw_info->size);
711 	fw_suit->major_ver = le32_get_bits(hdr->w1, FW_HDR_W1_MAJOR_VERSION);
712 	fw_suit->minor_ver = le32_get_bits(hdr->w1, FW_HDR_W1_MINOR_VERSION);
713 	fw_suit->sub_ver = le32_get_bits(hdr->w1, FW_HDR_W1_SUBVERSION);
714 	fw_suit->sub_idex = le32_get_bits(hdr->w1, FW_HDR_W1_SUBINDEX);
715 	fw_suit->commitid = le32_get_bits(hdr->w2, FW_HDR_W2_COMMITID);
716 	fw_suit->build_year = le32_get_bits(hdr->w5, FW_HDR_W5_YEAR);
717 	fw_suit->build_mon = le32_get_bits(hdr->w4, FW_HDR_W4_MONTH);
718 	fw_suit->build_date = le32_get_bits(hdr->w4, FW_HDR_W4_DATE);
719 	fw_suit->build_hour = le32_get_bits(hdr->w4, FW_HDR_W4_HOUR);
720 	fw_suit->build_min = le32_get_bits(hdr->w4, FW_HDR_W4_MIN);
721 	fw_suit->cmd_ver = le32_get_bits(hdr->w7, FW_HDR_W7_CMD_VERSERION);
728 	fw_suit->major_ver = le32_get_bits(hdr->w1, FW_HDR_V1_W1_MAJOR_VERSION);
729 	fw_suit->minor_ver = le32_get_bits(hdr->w1, FW_HDR_V1_W1_MINOR_VERSION);
730 	fw_suit->sub_ver = le32_get_bits(hdr->w1, FW_HDR_V1_W1_SUBVERSION);
731 	fw_suit->sub_idex = le32_get_bits(hdr->w1, FW_HDR_V1_W1_SUBINDEX);
732 	fw_suit->commitid = le32_get_bits(hdr->w2, FW_HDR_V1_W2_COMMITID);
733 	fw_suit->build_year = le32_get_bits(hdr->w5, FW_HDR_V1_W5_YEAR);
734 	fw_suit->build_mon = le32_get_bits(hdr->w4, FW_HDR_V1_W4_MONTH);
735 	fw_suit->build_date = le32_get_bits(hdr->w4, FW_HDR_V1_W4_DATE);
736 	fw_suit->build_hour = le32_get_bits(hdr->w4, FW_HDR_V1_W4_HOUR);
737 	fw_suit->build_min = le32_get_bits(hdr->w4, FW_HDR_V1_W4_MIN);
738 	fw_suit->cmd_ver = le32_get_bits(hdr->w7, FW_HDR_V1_W3_CMD_VERSERION);
745 	const struct rtw89_fw_hdr *v0 = (const struct rtw89_fw_hdr *)fw_suit->data;
746 	const struct rtw89_fw_hdr_v1 *v1 = (const struct rtw89_fw_hdr_v1 *)fw_suit->data;
749 		return 0;
751 	fw_suit->type = type;
752 	fw_suit->hdr_ver = le32_get_bits(v0->w3, FW_HDR_W3_HDR_VER);
754 	switch (fw_suit->hdr_ver) {
755 	case 0:
763 			  fw_suit->hdr_ver);
764 		return -ENOENT;
769 		   fw_suit->major_ver, fw_suit->minor_ver, fw_suit->sub_ver,
770 		   fw_suit->sub_idex, fw_suit->commitid, fw_suit->cmd_ver, type);
772 	return 0;
799 	struct rtw89_hal *hal = &rtwdev->hal;
805 	if (hal->cv < elm->u.bbmcu.cv)
809 	if (fw_suit->data)
812 	fw_suit->data = elm->u.bbmcu.contents;
813 	fw_suit->size = le32_to_cpu(elm->size);
844 	__CFG_FW_FEAT(RTL8851B, ge, 0, 29, 37, 1, TX_WAKE),
845 	__CFG_FW_FEAT(RTL8851B, ge, 0, 29, 37, 1, SCAN_OFFLOAD),
846 	__CFG_FW_FEAT(RTL8851B, ge, 0, 29, 41, 0, CRASH_TRIGGER_TYPE_0),
847 	__CFG_FW_FEAT(RTL8852A, le, 0, 13, 29, 0, OLD_HT_RA_FORMAT),
848 	__CFG_FW_FEAT(RTL8852A, ge, 0, 13, 35, 0, SCAN_OFFLOAD),
849 	__CFG_FW_FEAT(RTL8852A, ge, 0, 13, 35, 0, TX_WAKE),
850 	__CFG_FW_FEAT(RTL8852A, ge, 0, 13, 36, 0, CRASH_TRIGGER_TYPE_0),
851 	__CFG_FW_FEAT(RTL8852A, lt, 0, 13, 37, 0, NO_WOW_CPU_IO_RX),
852 	__CFG_FW_FEAT(RTL8852A, lt, 0, 13, 38, 0, NO_PACKET_DROP),
853 	__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 26, 0, NO_LPS_PG),
854 	__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 26, 0, TX_WAKE),
855 	__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 29, 0, CRASH_TRIGGER_TYPE_0),
856 	__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 29, 0, SCAN_OFFLOAD),
857 	__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 29, 7, BEACON_FILTER),
858 	__CFG_FW_FEAT(RTL8852B, lt, 0, 29, 30, 0, NO_WOW_CPU_IO_RX),
859 	__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 127, 0, LPS_DACK_BY_C2H_REG),
860 	__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 128, 0, CRASH_TRIGGER_TYPE_1),
861 	__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 128, 0, SCAN_OFFLOAD_EXTRA_OP),
862 	__CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 74, 0, NO_LPS_PG),
863 	__CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 74, 0, TX_WAKE),
864 	__CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 90, 0, CRASH_TRIGGER_TYPE_0),
865 	__CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 91, 0, SCAN_OFFLOAD),
866 	__CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 110, 0, BEACON_FILTER),
867 	__CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 127, 0, SCAN_OFFLOAD_EXTRA_OP),
868 	__CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 127, 0, LPS_DACK_BY_C2H_REG),
869 	__CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 127, 0, CRASH_TRIGGER_TYPE_1),
870 	__CFG_FW_FEAT(RTL8852C, le, 0, 27, 33, 0, NO_DEEP_PS),
871 	__CFG_FW_FEAT(RTL8852C, ge, 0, 0, 0, 0, RFK_NTFY_MCC_V0),
872 	__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 34, 0, TX_WAKE),
873 	__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 36, 0, SCAN_OFFLOAD),
874 	__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 40, 0, CRASH_TRIGGER_TYPE_0),
875 	__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 56, 10, BEACON_FILTER),
876 	__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 80, 0, WOW_REASON_V1),
877 	__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 128, 0, BEACON_LOSS_COUNT_V1),
878 	__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 30, 0, CRASH_TRIGGER_TYPE_0),
879 	__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 11, 0, MACID_PAUSE_SLEEP),
880 	__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 35, 0, SCAN_OFFLOAD),
881 	__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 21, 0, SCAN_OFFLOAD_BE_V0),
882 	__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 12, 0, BEACON_FILTER),
883 	__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 22, 0, WOW_REASON_V1),
884 	__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 28, 0, RFK_IQK_V0),
885 	__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 31, 0, RFK_PRE_NOTIFY_V0),
886 	__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 31, 0, LPS_CH_INFO),
887 	__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 42, 0, RFK_RXDCK_V0),
888 	__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 46, 0, NOTIFY_AP_INFO),
889 	__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 47, 0, CH_INFO_BE_V0),
890 	__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 49, 0, RFK_PRE_NOTIFY_V1),
891 	__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 51, 0, NO_PHYCAP_P1),
892 	__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 64, 0, NO_POWER_DIFFERENCE),
893 	__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 71, 0, BEACON_LOSS_COUNT_V1),
894 	__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 76, 0, LPS_DACK_BY_C2H_REG),
895 	__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 79, 0, CRASH_TRIGGER_TYPE_1),
904 	for (i = 0; i < ARRAY_SIZE(fw_feat_tbl); i++) {
907 		if (chip->chip_id != ent->chip_id)
910 		if (ent->cond(ver_code, ent->ver_code))
911 			RTW89_SET_FW_FEATURE(ent->feature, fw);
917 	const struct rtw89_chip_info *chip = rtwdev->chip;
924 	rtw89_fw_iterate_feature_cfg(&rtwdev->fw, chip, suit_ver_code);
939 	for (fw_format = chip->fw_format_max; fw_format >= 0; fw_format--) {
941 				      chip->fw_basename, fw_format);
956 	ver_code = rtw89_compat_fw_hdr_ver_code(firmware->data);
969 	const struct rtw89_chip_variant *variant = rtwdev->variant;
974 		return 0;
979 	if (variant->fw_min_ver_code > suit_ver_code) {
980 		rtw89_err(rtwdev, "minimum required firmware version is 0x%x\n",
981 			  variant->fw_min_ver_code);
982 		return -ENOENT;
985 	return 0;
990 	const struct rtw89_chip_info *chip = rtwdev->chip;
993 	if (chip->try_ce_fw) {
1018 	return 0;
1026 	struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1035 		return -ENOMEM;
1037 	switch (le32_to_cpu(elm->id)) {
1039 		elm_info->bb_tbl = tbl;
1042 		elm_info->bb_gain = tbl;
1049 		idx = elm->u.reg2.idx;
1051 		elm_info->rf_radio[idx] = tbl;
1052 		tbl->rf_path = rf_path;
1053 		tbl->config = rtw89_phy_config_rf_reg_v1;
1056 		elm_info->rf_nctl = tbl;
1060 		return -ENOENT;
1063 	n_regs = le32_to_cpu(elm->size) / sizeof(tbl->regs[0]);
1068 	for (i = 0; i < n_regs; i++) {
1069 		regs[i].addr = le32_to_cpu(elm->u.reg2.regs[i].addr);
1070 		regs[i].data = le32_to_cpu(elm->u.reg2.regs[i].data);
1073 	tbl->n_regs = n_regs;
1074 	tbl->regs = regs;
1076 	return 0;
1080 	return -ENOMEM;
1088 	const struct __rtw89_fw_txpwr_element *txpwr_elm = &elm->u.txpwr;
1090 	struct rtw89_efuse *efuse = &rtwdev->efuse;
1093 	if (!rtwdev->rfe_data) {
1094 		rtwdev->rfe_data = kzalloc(sizeof(*rtwdev->rfe_data), GFP_KERNEL);
1095 		if (!rtwdev->rfe_data)
1096 			return -ENOMEM;
1100 	conf = (void *)rtwdev->rfe_data + offset;
1102 	conf = (void *)((u8 *)rtwdev->rfe_data + offset);
1106 	if (txpwr_elm->rfe_type == efuse->rfe_type)
1110 	if (txpwr_elm->rfe_type == RTW89_TXPWR_CONF_DFLT_RFE_TYPE &&
1112 	     conf->rfe_type == RTW89_TXPWR_CONF_DFLT_RFE_TYPE))
1116 		    elm->id, txpwr_elm->rfe_type);
1117 	return 0;
1121 		    elm->id, txpwr_elm->rfe_type);
1123 	conf->rfe_type = txpwr_elm->rfe_type;
1124 	conf->ent_sz = txpwr_elm->ent_sz;
1125 	conf->num_ents = le32_to_cpu(txpwr_elm->num_ents);
1126 	conf->data = txpwr_elm->content;
1127 	return 0;
1135 	struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1136 	const struct rtw89_chip_info *chip = rtwdev->chip;
1137 	u32 needed_bitmap = 0;
1138 	u32 offset = 0;
1143 	if (chip->support_bands & BIT(NL80211_BAND_6GHZ))
1145 	if (chip->support_bands & BIT(NL80211_BAND_5GHZ))
1147 	if (chip->support_bands & BIT(NL80211_BAND_2GHZ))
1150 	bitmap = le32_to_cpu(elm->u.txpwr_trk.bitmap);
1155 		return -ENOENT;
1158 	elm_info->txpwr_trk = kzalloc(sizeof(*elm_info->txpwr_trk), GFP_KERNEL);
1159 	if (!elm_info->txpwr_trk)
1160 		return -ENOMEM;
1162 	for (type = 0; bitmap; type++, bitmap >>= 1) {
1163 		if (!(bitmap & BIT(0)))
1178 		elm_info->txpwr_trk->delta[type] = &elm->u.txpwr_trk.contents[offset];
1181 		if (offset * DELTA_SWINGIDX_SIZE > le32_to_cpu(elm->size))
1185 	return 0;
1189 		   offset, le32_to_cpu(elm->size));
1190 	kfree(elm_info->txpwr_trk);
1191 	elm_info->txpwr_trk = NULL;
1193 	return -EFAULT;
1201 	struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1204 	if (elm_info->rfk_log_fmt)
1207 	elm_info->rfk_log_fmt = kzalloc(sizeof(*elm_info->rfk_log_fmt), GFP_KERNEL);
1208 	if (!elm_info->rfk_log_fmt)
1212 	rfk_id = elm->u.rfk_log_fmt.rfk_id;
1216 	elm_info->rfk_log_fmt->elm[rfk_id] = elm;
1218 	return 0;
1229 		.fmap = cpu_to_le32(0x0),
1236 	memset(regd, 0, sizeof(*regd));
1238 	regd->alpha2[0] = entry.alpha2_0;
1239 	regd->alpha2[1] = entry.alpha2_1;
1240 	regd->alpha2[2] = '\0';
1243 	regd->txpwr_regd[RTW89_BAND_2G] = entry.rule_2ghz < RTW89_REGD_NUM ?
1245 	regd->txpwr_regd[RTW89_BAND_5G] = entry.rule_5ghz < RTW89_REGD_NUM ?
1247 	regd->txpwr_regd[RTW89_BAND_6G] = entry.rule_6ghz < RTW89_REGD_NUM ?
1254 	for (i = 0; i < NUM_OF_RTW89_REGD_FUNC; i++) {
1256 			set_bit(i, regd->func_bitmap);
1264 	for (const void *cursor = (element)->content, \
1265 	     *end = (element)->content + \
1266 		    le32_to_cpu((element)->num_ents) * (element)->ent_sz; \
1267 	     cursor < end; cursor += (element)->ent_sz) \
1268 		if (rtw89_regd_entcpy(regd, cursor, (element)->ent_sz))
1271 	for (const u8 *cursor = (element)->content, \
1272 	     *end = (element)->content + \
1273 		    le32_to_cpu((element)->num_ents) * (element)->ent_sz; \
1274 	     cursor < end; cursor += (element)->ent_sz) \
1275 		if (rtw89_regd_entcpy(regd, cursor, (element)->ent_sz))
1283 	const struct __rtw89_fw_regd_element *regd_elm = &elm->u.regd;
1284 	struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1285 	u32 num_ents = le32_to_cpu(regd_elm->num_ents);
1288 	u32 i = 0;
1299 	if (elm_info->regd) {
1302 		devm_kfree(rtwdev->dev, elm_info->regd);
1303 		elm_info->regd = NULL;
1306 	p = devm_kzalloc(rtwdev->dev, struct_size(p, map, num_ents), GFP_KERNEL);
1308 		return -ENOMEM;
1310 	p->nr = num_ents;
1312 		p->map[i++] = regd;
1316 			  num_ents - i);
1317 		devm_kfree(rtwdev->dev, p);
1318 		return -EINVAL;
1321 	elm_info->regd = p;
1322 	return 0;
1414 	struct rtw89_fw_info *fw_info = &rtwdev->fw;
1415 	const struct firmware *firmware = fw_info->req.firmware;
1416 	const struct rtw89_chip_info *chip = rtwdev->chip;
1417 	u32 unrecognized_elements = chip->needed_fw_elms;
1425 	BUILD_BUG_ON(sizeof(chip->needed_fw_elms) * 8 < RTW89_FW_ELEMENT_ID_NUM);
1429 	if (offset == 0)
1430 		return -EINVAL;
1432 	while (offset + sizeof(*hdr) < firmware->size) {
1433 		hdr = (const struct rtw89_fw_element_hdr *)(firmware->data + offset);
1435 		elm_size = le32_to_cpu(hdr->size);
1436 		if (offset + elm_size >= firmware->size) {
1441 		elem_id = le32_to_cpu(hdr->id);
1446 		if (!handler->fn)
1449 		ret = handler->fn(rtwdev, hdr, handler->arg);
1455 		if (handler->name)
1457 				   handler->name, hdr->ver);
1466 		rtw89_err(rtwdev, "Firmware elements 0x%08x are unrecognized\n",
1468 		return -ENOENT;
1471 	return 0;
1482 	if (!(rtwdev->fw.h2c_seq % 4))
1484 	hdr->hdr0 = cpu_to_le32(FIELD_PREP(H2C_HDR_DEL_TYPE, type) |
1488 				FIELD_PREP(H2C_HDR_H2C_SEQ, rtwdev->fw.h2c_seq));
1490 	hdr->hdr1 = cpu_to_le32(FIELD_PREP(H2C_HDR_TOTAL_LEN,
1492 				(rack ? H2C_HDR_REC_ACK : 0) |
1493 				(dack ? H2C_HDR_DONE_ACK : 0));
1495 	rtwdev->fw.h2c_seq++;
1507 	hdr->hdr0 = cpu_to_le32(FIELD_PREP(H2C_HDR_DEL_TYPE, type) |
1511 				FIELD_PREP(H2C_HDR_H2C_SEQ, rtwdev->fw.h2c_seq));
1513 	hdr->hdr1 = cpu_to_le32(FIELD_PREP(H2C_HDR_TOTAL_LEN,
1525 	le32p_replace_bits(&fw_hdr->w7, FWDL_SECTION_PER_PKT_LEN,
1528 	for (i = 0; i < info->section_num; i++) {
1529 		section_info = &info->section_info[i];
1531 		if (!section_info->len_override)
1534 		section = &fw_hdr->sections[i];
1535 		le32p_replace_bits(&section->w1, section_info->len_override,
1539 	return 0;
1548 	u8 dst_sec_idx = 0;
1551 	le32p_replace_bits(&fw_hdr->w7, FWDL_SECTION_PER_PKT_LEN,
1554 	for (sec_idx = 0; sec_idx < info->section_num; sec_idx++) {
1555 		section_info = &info->section_info[sec_idx];
1556 		section = &fw_hdr->sections[sec_idx];
1558 		if (section_info->ignore)
1562 			fw_hdr->sections[dst_sec_idx] = *section;
1567 	le32p_replace_bits(&fw_hdr->w6, dst_sec_idx, FW_HDR_V1_W6_SEC_NUM);
1569 	return (info->section_num - dst_sec_idx) * sizeof(*section);
1576 	u32 len = info->hdr_len - info->dynamic_hdr_len;
1578 	const u8 *fw = fw_suit->data;
1582 	u32 ret = 0;
1587 		return -ENOMEM;
1592 	switch (fw_suit->hdr_ver) {
1593 	case 0:
1594 		fw_hdr = (struct rtw89_fw_hdr *)skb->data;
1598 		fw_hdr_v1 = (struct rtw89_fw_hdr_v1 *)skb->data;
1602 		ret = -EOPNOTSUPP;
1607 		len -= truncated;
1621 	return 0;
1632 	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1641 	ret = mac->fwdl_check_path_ready(rtwdev, false);
1647 	rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0);
1648 	rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
1650 	return 0;
1657 	const u8 *section = info->addr;
1658 	u32 residue_len = info->len;
1663 	if (info->ignore)
1664 		return 0;
1666 	if (info->len_override) {
1667 		if (info->len_override > info->len)
1669 				   info->len_override, info->len);
1671 			residue_len = info->len_override;
1674 	if (info->key_addr && info->key_len) {
1675 		if (residue_len > FWDL_SECTION_PER_PKT_LEN || info->len < info->key_len)
1678 				   info->len, FWDL_SECTION_PER_PKT_LEN,
1679 				   info->key_len, residue_len);
1693 			return -ENOMEM;
1698 			memcpy(skb->data + pkt_len - info->key_len,
1699 			       info->key_addr, info->key_len);
1708 		residue_len -= pkt_len;
1711 	return 0;
1722 	switch (fw_suit->type) {
1736 	struct rtw89_fw_hdr_section_info *section_info = info->section_info;
1737 	const struct rtw89_chip_info *chip = rtwdev->chip;
1739 	u8 section_num = info->section_num;
1742 	while (section_num--) {
1749 	if (chip->chip_gen == RTW89_CHIP_AX)
1750 		return 0;
1756 			   fw_suit->type);
1760 	return 0;
1765 	enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
1781 	for (index = 0; index < 15; index++) {
1783 		rtw89_err(rtwdev, "[ERR]fw PC = 0x%x\n", val32);
1798 	rtw89_err(rtwdev, "[ERR]fwdl 0x1E0 = 0x%x\n", val32);
1801 	rtw89_err(rtwdev, "[ERR]fwdl 0x83F0 = 0x%x\n", val32);
1809 	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1821 	if (rtwdev->chip->chip_id == RTL8922A &&
1822 	    (fw_suit->type == RTW89_FW_NORMAL || fw_suit->type == RTW89_FW_WOWLAN))
1823 		rtw89_write32(rtwdev, R_BE_SECURE_BOOT_MALLOC_INFO, 0x20248000);
1825 	ret = mac->fwdl_check_path_ready(rtwdev, true);
1839 	return 0;
1846 	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1847 	struct rtw89_fw_info *fw_info = &rtwdev->fw;
1849 	u8 bbmcu_nr = rtwdev->chip->bbmcu_nr;
1853 	mac->disable_cpu(rtwdev);
1854 	ret = mac->fwdl_enable_wcpu(rtwdev, 0, true, include_bb);
1862 	for (i = 0; i < bbmcu_nr && include_bb; i++) {
1870 	fw_info->h2c_seq = 0;
1871 	fw_info->rec_seq = 0;
1872 	fw_info->h2c_counter = 0;
1873 	fw_info->c2h_counter = 0;
1874 	rtwdev->mac.rpwm_seq_num = RPWM_SEQ_NUM_MAX;
1875 	rtwdev->mac.cpwm_seq_num = CPWM_SEQ_NUM_MAX;
1898 	for (retry = 0; retry < 5; retry++) {
1901 			return 0;
1909 	struct rtw89_fw_info *fw = &rtwdev->fw;
1911 	wait_for_completion(&fw->req.completion);
1912 	if (!fw->req.firmware)
1913 		return -EINVAL;
1915 	return 0;
1924 	if (req->firmware) {
1927 		complete_all(&req->completion);
1928 		return 0;
1932 		ret = firmware_request_nowarn(&req->firmware, fw_name, rtwdev->dev);
1934 		ret = request_firmware(&req->firmware, fw_name, rtwdev->dev);
1936 	complete_all(&req->completion);
1945 	const struct rtw89_chip_info *chip = rtwdev->chip;
1949 			      chip->fw_basename, rtwdev->fw.fw_format);
1951 	rtw89_load_firmware_req(rtwdev, &rtwdev->fw.req, fw_name, false);
1959 	kfree(tbl->regs);
1965 	struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1968 	rtw89_free_phy_tbl_from_elm(elm_info->bb_tbl);
1969 	rtw89_free_phy_tbl_from_elm(elm_info->bb_gain);
1970 	for (i = 0; i < ARRAY_SIZE(elm_info->rf_radio); i++)
1971 		rtw89_free_phy_tbl_from_elm(elm_info->rf_radio[i]);
1972 	rtw89_free_phy_tbl_from_elm(elm_info->rf_nctl);
1974 	kfree(elm_info->txpwr_trk);
1975 	kfree(elm_info->rfk_log_fmt);
1980 	struct rtw89_fw_info *fw = &rtwdev->fw;
1982 	cancel_work_sync(&rtwdev->load_firmware_work);
1984 	if (fw->req.firmware) {
1985 		release_firmware(fw->req.firmware);
1990 		fw->req.firmware = NULL;
1993 	kfree(fw->log.fmts);
1999 	struct rtw89_fw_log *fw_log = &rtwdev->fw.log;
2002 	if (fmt_id > fw_log->last_fmt_id)
2003 		return 0;
2005 	for (i = 0; i < fw_log->fmt_count; i++) {
2006 		if (le32_to_cpu(fw_log->fmt_ids[i]) == fmt_id)
2009 	return 0;
2014 	struct rtw89_fw_log *log = &rtwdev->fw.log;
2016 	struct rtw89_fw_suit *suit = &log->suit;
2025 	suit_hdr = (const struct rtw89_fw_logsuit_hdr *)suit->data;
2026 	fmt_count = le32_to_cpu(suit_hdr->count);
2027 	log->fmt_ids = suit_hdr->ids;
2029 	fmts_ptr = &suit_hdr->ids[fmt_count];
2031 	fmts_ptr = (const u8 *)&suit_hdr->ids[fmt_count];
2033 	fmts_end_ptr = suit->data + suit->size;
2034 	log->fmts = kcalloc(fmt_count, sizeof(char *), GFP_KERNEL);
2035 	if (!log->fmts)
2036 		return -ENOMEM;
2038 	for (i = 0; i < fmt_count; i++) {
2039 		fmts_ptr = memchr_inv(fmts_ptr, 0, fmts_end_ptr - fmts_ptr);
2043 		(*log->fmts)[i] = fmts_ptr;
2044 		log->last_fmt_id = le32_to_cpu(log->fmt_ids[i]);
2045 		log->fmt_count++;
2049 	return 0;
2054 	struct rtw89_fw_log *log = &rtwdev->fw.log;
2055 	struct rtw89_fw_suit *suit = &log->suit;
2057 	if (!suit || !suit->data) {
2059 		return -EINVAL;
2061 	if (log->fmts)
2062 		return 0;
2071 	const char *(*fmts)[] = rtwdev->fw.log.fmts;
2073 	u32 args[RTW89_C2H_FW_LOG_MAX_PARA_NUM] = {0};
2076 	if (log_fmt->argc > RTW89_C2H_FW_LOG_MAX_PARA_NUM) {
2078 			   log_fmt->argc);
2083 		for (i = 0 ; i < log_fmt->argc; i++)
2084 			args[i] = le32_to_cpu(log_fmt->u.argv[i]);
2089 				 "fw_enc(%d, %d, %d) %*ph", le32_to_cpu(log_fmt->fmt_id),
2090 				 para_int, log_fmt->argc, (int)sizeof(args), args);
2093 				 "fw_enc(%d, %d, %d, %s)", le32_to_cpu(log_fmt->fmt_id),
2094 				 para_int, log_fmt->argc, log_fmt->u.raw);
2097 			 args[0x0], args[0x1], args[0x2], args[0x3], args[0x4],
2098 			 args[0x5], args[0x6], args[0x7], args[0x8], args[0x9],
2099 			 args[0xa], args[0xb], args[0xc], args[0xd], args[0xe],
2100 			 args[0xf]);
2118 	len -= RTW89_C2H_HEADER_LEN;
2124 	if (log_fmt->signature != cpu_to_le16(RTW89_C2H_FW_LOG_SIGNATURE))
2127 	if (!rtwdev->fw.log.fmts)
2130 	para_int = u8_get_bits(log_fmt->feature, RTW89_C2H_FW_LOG_FEATURE_PARA_INT);
2131 	fmt_idx = rtw89_fw_log_get_fmt_idx(rtwdev, le32_to_cpu(log_fmt->fmt_id));
2133 	if (!para_int && log_fmt->argc != 0 && fmt_idx != 0)
2135 			   (*rtwdev->fw.log.fmts)[fmt_idx], log_fmt->u.raw);
2136 	else if (fmt_idx != 0 && para_int)
2157 		return -ENOMEM;
2161 				     skb->data);
2162 	rtw89_cam_fill_bssid_cam_info(rtwdev, rtwvif_link, rtwsta_link, skb->data);
2167 			      H2C_FUNC_MAC_ADDR_CAM_UPD, 0, 1,
2176 	return 0;
2195 		return -ENOMEM;
2198 	h2c = (struct rtw89_h2c_dctlinfo_ud_v1 *)skb->data;
2205 			      H2C_FUNC_MAC_DCTLINFO_UD_V1, 0, 0,
2214 	return 0;
2234 		return -ENOMEM;
2237 	h2c = (struct rtw89_h2c_dctlinfo_ud_v2 *)skb->data;
2244 			      H2C_FUNC_MAC_DCTLINFO_UD_V2, 0, 0,
2253 	return 0;
2265 	u8 mac_id = rtwsta_link ? rtwsta_link->mac_id : rtwvif_link->mac_id;
2273 		rtw89_err(rtwdev, "failed to alloc skb for dctl v2\n");
2274 		return -ENOMEM;
2277 	h2c = (struct rtw89_h2c_dctlinfo_ud_v2 *)skb->data;
2279 	h2c->c0 = le32_encode_bits(mac_id, DCTLINFO_V2_C0_MACID) |
2282 	h2c->m0 = cpu_to_le32(DCTLINFO_V2_W0_ALL);
2283 	h2c->m1 = cpu_to_le32(DCTLINFO_V2_W1_ALL);
2284 	h2c->m2 = cpu_to_le32(DCTLINFO_V2_W2_ALL);
2285 	h2c->m3 = cpu_to_le32(DCTLINFO_V2_W3_ALL);
2286 	h2c->m4 = cpu_to_le32(DCTLINFO_V2_W4_ALL);
2287 	h2c->m5 = cpu_to_le32(DCTLINFO_V2_W5_ALL);
2288 	h2c->m6 = cpu_to_le32(DCTLINFO_V2_W6_ALL);
2289 	h2c->m7 = cpu_to_le32(DCTLINFO_V2_W7_ALL);
2290 	h2c->m8 = cpu_to_le32(DCTLINFO_V2_W8_ALL);
2291 	h2c->m9 = cpu_to_le32(DCTLINFO_V2_W9_ALL);
2292 	h2c->m10 = cpu_to_le32(DCTLINFO_V2_W10_ALL);
2293 	h2c->m11 = cpu_to_le32(DCTLINFO_V2_W11_ALL);
2294 	h2c->m12 = cpu_to_le32(DCTLINFO_V2_W12_ALL);
2299 			      H2C_FUNC_MAC_DCTLINFO_UD_V2, 0, 0,
2308 	return 0;
2321 	const struct rtw89_chip_info *chip = rtwdev->chip;
2323 	u8 macid = rtwsta_link->mac_id;
2330 	      rtw89_core_acquire_sta_ba_entry(rtwdev, rtwsta_link, params->tid,
2332 	      rtw89_core_release_sta_ba_entry(rtwdev, rtwsta_link, params->tid,
2340 			    valid ? "alloc" : "free", params->tid);
2341 		return 0;
2347 		return -ENOMEM;
2350 	h2c = (struct rtw89_h2c_ba_cam *)skb->data;
2352 	h2c->w0 = le32_encode_bits(macid, RTW89_H2C_BA_CAM_W0_MACID);
2353 	if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
2354 		h2c->w1 |= le32_encode_bits(entry_idx, RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1);
2356 		h2c->w0 |= le32_encode_bits(entry_idx, RTW89_H2C_BA_CAM_W0_ENTRY_IDX);
2359 	h2c->w0 |= le32_encode_bits(valid, RTW89_H2C_BA_CAM_W0_VALID) |
2360 		   le32_encode_bits(params->tid, RTW89_H2C_BA_CAM_W0_TID);
2361 	if (params->buf_size > 64)
2362 		h2c->w0 |= le32_encode_bits(4, RTW89_H2C_BA_CAM_W0_BMAP_SIZE);
2364 		h2c->w0 |= le32_encode_bits(0, RTW89_H2C_BA_CAM_W0_BMAP_SIZE);
2366 	h2c->w0 |= le32_encode_bits(1, RTW89_H2C_BA_CAM_W0_INIT_REQ) |
2367 		   le32_encode_bits(params->ssn, RTW89_H2C_BA_CAM_W0_SSN);
2369 	if (chip->bacam_ver == RTW89_BACAM_V0_EXT) {
2370 		h2c->w1 |= le32_encode_bits(1, RTW89_H2C_BA_CAM_W1_STD_EN) |
2371 			   le32_encode_bits(rtwvif_link->mac_idx,
2379 			      H2C_FUNC_MAC_BA_CAM, 0, 1,
2388 	return 0;
2407 		return -ENOMEM;
2410 	h2c = (struct rtw89_h2c_ba_cam *)skb->data;
2412 	h2c->w0 = le32_encode_bits(1, RTW89_H2C_BA_CAM_W0_VALID);
2413 	h2c->w1 = le32_encode_bits(entry_idx, RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1) |
2415 		  le32_encode_bits(0, RTW89_H2C_BA_CAM_W1_BAND) |
2416 		  le32_encode_bits(0, RTW89_H2C_BA_CAM_W1_STD_EN);
2421 			      H2C_FUNC_MAC_BA_CAM, 0, 1,
2430 	return 0;
2439 	const struct rtw89_chip_info *chip = rtwdev->chip;
2440 	u8 entry_idx = chip->bacam_num;
2441 	u8 uid = 0;
2444 	for (i = 0; i < chip->bacam_dynamic_num; i++) {
2456 	const struct rtw89_chip_info *chip = rtwdev->chip;
2458 	u8 macid = rtwsta_link->mac_id;
2466 	      rtw89_core_acquire_sta_ba_entry(rtwdev, rtwsta_link, params->tid,
2468 	      rtw89_core_release_sta_ba_entry(rtwdev, rtwsta_link, params->tid,
2476 			    valid ? "alloc" : "free", params->tid);
2477 		return 0;
2483 		return -ENOMEM;
2486 	h2c = (struct rtw89_h2c_ba_cam_v1 *)skb->data;
2488 	if (params->buf_size > 512)
2490 	else if (params->buf_size > 256)
2492 	else if (params->buf_size > 64)
2495 		bmap_size = 0;
2497 	h2c->w0 = le32_encode_bits(valid, RTW89_H2C_BA_CAM_V1_W0_VALID) |
2500 		  le32_encode_bits(params->tid, RTW89_H2C_BA_CAM_V1_W0_TID_MASK) |
2502 		  le32_encode_bits(params->ssn, RTW89_H2C_BA_CAM_V1_W0_SSN_MASK);
2504 	entry_idx += chip->bacam_dynamic_num; /* std entry right after dynamic ones */
2505 	h2c->w1 = le32_encode_bits(entry_idx, RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK) |
2507 		  le32_encode_bits(!!rtwvif_link->mac_idx,
2513 			      H2C_FUNC_MAC_BA_CAM_V1, 0, 1,
2522 	return 0;
2541 		return -ENOMEM;
2544 	h2c = (struct rtw89_h2c_ba_cam_init *)skb->data;
2546 	h2c->w0 = le32_encode_bits(users, RTW89_H2C_BA_CAM_INIT_USERS_MASK) |
2553 			      H2C_FUNC_MAC_BA_CAM_INIT, 0, 1,
2562 	return 0;
2573 	u32 comp = 0;
2584 		return -ENOMEM;
2588 	SET_LOG_CFG_LEVEL(skb->data, RTW89_FW_LOG_LEVEL_LOUD);
2589 	SET_LOG_CFG_PATH(skb->data, BIT(RTW89_FW_LOG_LEVEL_C2H));
2590 	SET_LOG_CFG_COMP(skb->data, comp);
2591 	SET_LOG_CFG_COMP_EXT(skb->data, 0);
2596 			      H2C_FUNC_LOG_CFG, 0, 0,
2605 	return 0;
2615 	static const u8 gtkbody[] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x88,
2616 				     0x8E, 0x01, 0x03, 0x00, 0x5F, 0x02, 0x03};
2618 	struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
2625 	if (rtw_wow->ptk_alg == 3)
2627 	else if (rtw_wow->akm == 1 || rtw_wow->akm == 2)
2629 	else if (rtw_wow->akm > 2 && rtw_wow->akm < 7)
2632 		key_des_ver = 0;
2639 	hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA |
2647 	ether_addr_copy(hdr->addr1, bss_conf->bssid);
2648 	ether_addr_copy(hdr->addr2, bss_conf->addr);
2649 	ether_addr_copy(hdr->addr3, bss_conf->bssid);
2656 	memcpy(eapol_pkt->gtkbody, gtkbody, sizeof(gtkbody));
2657 	eapol_pkt->key_des_ver = key_des_ver;
2676 	hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
2684 	ether_addr_copy(hdr->addr1, bss_conf->bssid);
2685 	ether_addr_copy(hdr->addr2, bss_conf->addr);
2686 	ether_addr_copy(hdr->addr3, bss_conf->bssid);
2693 	sa_query->category = WLAN_CATEGORY_SA_QUERY;
2694 	sa_query->action = WLAN_ACTION_SA_QUERY_RESPONSE;
2702 	struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
2704 	struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
2717 	if (rtw_wow->ptk_alg)
2723 	hdr->frame_control = fc;
2724 	ether_addr_copy(hdr->addr1, rtwvif_link->bssid);
2725 	ether_addr_copy(hdr->addr2, rtwvif_link->mac_addr);
2726 	ether_addr_copy(hdr->addr3, rtwvif_link->bssid);
2731 	memcpy(arp_skb->llc_hdr, rfc1042_header, sizeof(rfc1042_header));
2732 	arp_skb->llc_type = htons(ETH_P_ARP);
2734 	arp_hdr = &arp_skb->arp_hdr;
2735 	arp_hdr->ar_hrd = htons(ARPHRD_ETHER);
2736 	arp_hdr->ar_pro = htons(ETH_P_IP);
2737 	arp_hdr->ar_hln = ETH_ALEN;
2738 	arp_hdr->ar_pln = 4;
2739 	arp_hdr->ar_op = htons(ARPOP_REPLY);
2741 	ether_addr_copy(arp_skb->sender_hw, rtwvif_link->mac_addr);
2742 	arp_skb->sender_ip = rtwvif->ip_addr;
2753 	int link_id = ieee80211_vif_is_mld(vif) ? rtwvif_link->link_id : -1;
2760 		return -ENOMEM;
2764 		skb = ieee80211_pspoll_get(rtwdev->hw, vif);
2767 		skb = ieee80211_proberesp_get(rtwdev->hw, vif);
2770 		skb = ieee80211_nullfunc_get(rtwdev->hw, vif, link_id, false);
2773 		skb = ieee80211_nullfunc_get(rtwdev->hw, vif, link_id, true);
2791 	ret = rtw89_fw_h2c_add_pkt_offload(rtwdev, &info->id, skb);
2797 	list_add_tail(&info->list, &rtwvif_link->general_pkt_list);
2798 	*id = info->id;
2799 	return 0;
2803 	return -ENOMEM;
2810 	struct list_head *pkt_list = &rtwvif_link->general_pkt_list;
2815 			rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
2817 			rtw89_core_release_bit_map(rtwdev->pkt_offload, info->id);
2818 		list_del(&info->list);
2836 #define H2C_GENERAL_PKT_ID_UND 0xff
2856 		return -ENOMEM;
2859 	SET_GENERAL_PKT_MACID(skb->data, macid);
2860 	SET_GENERAL_PKT_PROBRSP_ID(skb->data, H2C_GENERAL_PKT_ID_UND);
2861 	SET_GENERAL_PKT_PSPOLL_ID(skb->data, pkt_id_ps_poll);
2862 	SET_GENERAL_PKT_NULL_ID(skb->data, pkt_id_null);
2863 	SET_GENERAL_PKT_QOS_NULL_ID(skb->data, pkt_id_qos_null);
2864 	SET_GENERAL_PKT_CTS2SELF_ID(skb->data, H2C_GENERAL_PKT_ID_UND);
2869 			      H2C_FUNC_MAC_GENERAL_PKT, 0, 1,
2878 	return 0;
2893 	if (RTW89_CHK_FW_FEATURE(LPS_DACK_BY_C2H_REG, &rtwdev->fw))
2896 		done_ack = !lps_param->psmode;
2901 		return -ENOMEM;
2905 	SET_LPS_PARM_MACID(skb->data, lps_param->macid);
2906 	SET_LPS_PARM_PSMODE(skb->data, lps_param->psmode);
2907 	SET_LPS_PARM_LASTRPWM(skb->data, lps_param->lastrpwm);
2908 	SET_LPS_PARM_RLBM(skb->data, 1);
2909 	SET_LPS_PARM_SMARTPS(skb->data, 1);
2910 	SET_LPS_PARM_AWAKEINTERVAL(skb->data, 1);
2911 	SET_LPS_PARM_VOUAPSD(skb->data, 0);
2912 	SET_LPS_PARM_VIUAPSD(skb->data, 0);
2913 	SET_LPS_PARM_BEUAPSD(skb->data, 0);
2914 	SET_LPS_PARM_BKUAPSD(skb->data, 0);
2919 			      H2C_FUNC_MAC_LPS_PARM, 0, done_ack,
2928 	return 0;
2937 	const struct rtw89_chip_info *chip = rtwdev->chip;
2949 	if (chip->chip_gen != RTW89_CHIP_BE)
2950 		return 0;
2955 		return -ENOMEM;
2958 	h2c = (struct rtw89_h2c_lps_ch_info *)skb->data;
2961 		phy_idx = rtwvif_link->phy_idx;
2962 		if (phy_idx >= ARRAY_SIZE(h2c->info))
2965 		chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
2968 		h2c->info[phy_idx].central_ch = chan->channel;
2969 		h2c->info[phy_idx].pri_ch = chan->primary_channel;
2970 		h2c->info[phy_idx].band = chan->band_type;
2971 		h2c->info[phy_idx].bw = chan->band_width;
2976 		ret = -ENOENT;
2980 	h2c->mlo_dbcc_mode_lps = cpu_to_le32(rtwdev->mlo_dbcc_mode);
2984 			      H2C_FUNC_FW_LPS_CH_INFO, 0, 0, len);
2986 	rtw89_phy_write32_mask(rtwdev, R_CHK_LPS_STAT, B_CHK_LPS_STAT, 0);
2998 	return 0;
3008 	const struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be;
3009 	struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat;
3010 	static const u8 bcn_bw_ofst[] = {0, 0, 0, 3, 6, 9, 0, 12};
3011 	const struct rtw89_chip_info *chip = rtwdev->chip;
3012 	struct rtw89_efuse *efuse = &rtwdev->efuse;
3027 	if (chip->chip_gen != RTW89_CHIP_BE)
3028 		return 0;
3033 		return -ENOMEM;
3036 	h2c = (struct rtw89_h2c_lps_ml_cmn_info *)skb->data;
3038 	h2c->fmt_id = 0x3;
3040 	h2c->mlo_dbcc_mode = cpu_to_le32(rtwdev->mlo_dbcc_mode);
3041 	h2c->rfe_type = efuse->rfe_type;
3044 		path = rtwvif_link->phy_idx == RTW89_PHY_1 ? RF_PATH_B : RF_PATH_A;
3045 		chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
3046 		gain_band = rtw89_subband_to_gain_band_be(chan->subband_type);
3048 		h2c->central_ch[rtwvif_link->phy_idx] = chan->channel;
3049 		h2c->pri_ch[rtwvif_link->phy_idx] = chan->primary_channel;
3050 		h2c->band[rtwvif_link->phy_idx] = chan->band_type;
3051 		h2c->bw[rtwvif_link->phy_idx] = chan->band_width;
3052 		if (pkt_stat->beacon_rate < RTW89_HW_RATE_OFDM6)
3053 			h2c->bcn_rate_type[rtwvif_link->phy_idx] = 0x1;
3055 			h2c->bcn_rate_type[rtwvif_link->phy_idx] = 0x2;
3058 		for (i = 0; i < TIA_GAIN_NUM; i++) {
3059 			h2c->tia_gain[rtwvif_link->phy_idx][i] =
3060 				cpu_to_le16(gain->tia_gain[gain_band][bw_idx][path][i]);
3063 		if (rtwvif_link->bcn_bw_idx < ARRAY_SIZE(bcn_bw_ofst)) {
3064 			beacon_bw_ofst = bcn_bw_ofst[rtwvif_link->bcn_bw_idx];
3065 			h2c->dup_bcn_ofst[rtwvif_link->phy_idx] = beacon_bw_ofst;
3068 		memcpy(h2c->lna_gain[rtwvif_link->phy_idx],
3069 		       gain->lna_gain[gain_band][bw_idx][path],
3071 		memcpy(h2c->tia_lna_op1db[rtwvif_link->phy_idx],
3072 		       gain->tia_lna_op1db[gain_band][bw_idx][path],
3074 		memcpy(h2c->lna_op1db[rtwvif_link->phy_idx],
3075 		       gain->lna_op1db[gain_band][bw_idx][path],
3081 			      H2C_FUNC_FW_LPS_ML_CMN_INFO, 0, 0, len);
3083 	rtw89_phy_write32_mask(rtwdev, R_CHK_LPS_STAT, B_CHK_LPS_STAT, 0);
3095 	return 0;
3108 	bool p2p_type_gc = rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT;
3116 		return -ENOMEM;
3119 	cmd = skb->data;
3121 	RTW89_SET_FWCMD_P2P_MACID(cmd, rtwvif_link->mac_id);
3122 	RTW89_SET_FWCMD_P2P_P2PID(cmd, 0);
3126 	RTW89_SET_FWCMD_P2P_ALL_SLEP(cmd, 0);
3128 		RTW89_SET_FWCMD_NOA_START_TIME(cmd, desc->start_time);
3129 		RTW89_SET_FWCMD_NOA_INTERVAL(cmd, desc->interval);
3130 		RTW89_SET_FWCMD_NOA_DURATION(cmd, desc->duration);
3131 		RTW89_SET_FWCMD_NOA_COUNT(cmd, desc->count);
3137 			      H2C_FUNC_P2P_ACT, 0, 0,
3146 	return 0;
3156 	const struct rtw89_chip_info *chip = rtwdev->chip;
3157 	struct rtw89_hal *hal = &rtwdev->hal;
3161 	if (chip->rf_path_num == 1) {
3163 		map_b = 0;
3165 		ntx_path = hal->antenna_tx ? hal->antenna_tx : RF_AB;
3166 		map_b = ntx_path == RF_AB ? 1 : 0;
3169 	SET_CMC_TBL_NTX_PATH_EN(skb->data, ntx_path);
3170 	SET_CMC_TBL_PATH_MAP_A(skb->data, 0);
3171 	SET_CMC_TBL_PATH_MAP_B(skb->data, map_b);
3172 	SET_CMC_TBL_PATH_MAP_C(skb->data, 0);
3173 	SET_CMC_TBL_PATH_MAP_D(skb->data, 0);
3181 	const struct rtw89_chip_info *chip = rtwdev->chip;
3182 	u8 macid = rtwsta_link ? rtwsta_link->mac_id : rtwvif_link->mac_id;
3189 		return -ENOMEM;
3192 	SET_CTRL_INFO_MACID(skb->data, macid);
3193 	SET_CTRL_INFO_OPERATION(skb->data, 1);
3194 	if (chip->h2c_cctl_func_id == H2C_FUNC_MAC_CCTLINFO_UD) {
3195 		SET_CMC_TBL_TXPWR_MODE(skb->data, 0);
3197 		SET_CMC_TBL_ANTSEL_A(skb->data, 0);
3198 		SET_CMC_TBL_ANTSEL_B(skb->data, 0);
3199 		SET_CMC_TBL_ANTSEL_C(skb->data, 0);
3200 		SET_CMC_TBL_ANTSEL_D(skb->data, 0);
3202 	SET_CMC_TBL_DOPPLER_CTRL(skb->data, 0);
3203 	SET_CMC_TBL_TXPWR_TOLERENCE(skb->data, 0);
3204 	if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE)
3205 		SET_CMC_TBL_DATA_DCM(skb->data, 0);
3209 			      chip->h2c_cctl_func_id, 0, 1,
3218 	return 0;
3230 	u8 mac_id = rtwsta_link ? rtwsta_link->mac_id : rtwvif_link->mac_id;
3239 		return -ENOMEM;
3242 	h2c = (struct rtw89_h2c_cctlinfo_ud_g7 *)skb->data;
3244 	h2c->c0 = le32_encode_bits(mac_id, CCTLINFO_G7_C0_MACID) |
3247 	h2c->w0 = le32_encode_bits(4, CCTLINFO_G7_W0_DATARATE);
3248 	h2c->m0 = cpu_to_le32(CCTLINFO_G7_W0_ALL);
3250 	h2c->w1 = le32_encode_bits(4, CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE) |
3251 		  le32_encode_bits(0xa, CCTLINFO_G7_W1_RTSRATE) |
3253 	h2c->m1 = cpu_to_le32(CCTLINFO_G7_W1_ALL);
3255 	h2c->m2 = cpu_to_le32(CCTLINFO_G7_W2_ALL);
3257 	h2c->m3 = cpu_to_le32(CCTLINFO_G7_W3_ALL);
3259 	h2c->w4 = le32_encode_bits(0xFFFF, CCTLINFO_G7_W4_ACT_SUBCH_CBW);
3260 	h2c->m4 = cpu_to_le32(CCTLINFO_G7_W4_ALL);
3262 	h2c->w5 = le32_encode_bits(2, CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0) |
3267 	h2c->m5 = cpu_to_le32(CCTLINFO_G7_W5_ALL);
3269 	h2c->w6 = le32_encode_bits(0xb, CCTLINFO_G7_W6_RESP_REF_RATE);
3270 	h2c->m6 = cpu_to_le32(CCTLINFO_G7_W6_ALL);
3272 	h2c->w7 = le32_encode_bits(1, CCTLINFO_G7_W7_NC) |
3275 		  le32_encode_bits(0x1, CCTLINFO_G7_W7_CSI_PARA_EN) |
3276 		  le32_encode_bits(0xb, CCTLINFO_G7_W7_CSI_FIX_RATE);
3277 	h2c->m7 = cpu_to_le32(CCTLINFO_G7_W7_ALL);
3279 	h2c->m8 = cpu_to_le32(CCTLINFO_G7_W8_ALL);
3281 	h2c->w14 = le32_encode_bits(0, CCTLINFO_G7_W14_VO_CURR_RATE) |
3282 		   le32_encode_bits(0, CCTLINFO_G7_W14_VI_CURR_RATE) |
3283 		   le32_encode_bits(0, CCTLINFO_G7_W14_BE_CURR_RATE_L);
3284 	h2c->m14 = cpu_to_le32(CCTLINFO_G7_W14_ALL);
3286 	h2c->w15 = le32_encode_bits(0, CCTLINFO_G7_W15_BE_CURR_RATE_H) |
3287 		   le32_encode_bits(0, CCTLINFO_G7_W15_BK_CURR_RATE) |
3288 		   le32_encode_bits(0, CCTLINFO_G7_W15_MGNT_CURR_RATE);
3289 	h2c->m15 = cpu_to_le32(CCTLINFO_G7_W15_ALL);
3293 			      H2C_FUNC_MAC_CCTLINFO_UD_G7, 0, 1,
3302 	return 0;
3316 	u8 nss = min(link_sta->rx_nss, rtwdev->hal.tx_nss) - 1;
3317 	u8 ppe_thres_hdr = link_sta->he_cap.ppe_thres[0];
3324 			   link_sta->he_cap.he_cap_elem.phy_cap_info[6]);
3329 				link_sta->he_cap.he_cap_elem.phy_cap_info[9]);
3331 		for (i = 0; i < RTW89_PPE_BW_NUM; i++)
3341 	for (i = 0; i < RTW89_PPE_BW_NUM; i++) {
3351 		ppe = le16_to_cpu(*((__le16 *)&link_sta->he_cap.ppe_thres[idx]));
3370 	const struct rtw89_chip_info *chip = rtwdev->chip;
3372 						       rtwvif_link->chanctx_idx);
3376 	u8 mac_id = rtwsta_link ? rtwsta_link->mac_id : rtwvif_link->mac_id;
3380 	memset(pads, 0, sizeof(pads));
3385 		return -ENOMEM;
3393 	if (rtwsta_link && link_sta->he_cap.has_he)
3396 	if (vif->p2p)
3398 	else if (chan->band_type == RTW89_BAND_2G)
3404 	SET_CTRL_INFO_MACID(skb->data, mac_id);
3405 	SET_CTRL_INFO_OPERATION(skb->data, 1);
3406 	SET_CMC_TBL_DISRTSFB(skb->data, 1);
3407 	SET_CMC_TBL_DISDATAFB(skb->data, 1);
3408 	SET_CMC_TBL_RTS_RTY_LOWEST_RATE(skb->data, lowest_rate);
3409 	SET_CMC_TBL_RTS_TXCNT_LMT_SEL(skb->data, 0);
3410 	SET_CMC_TBL_DATA_TXCNT_LMT_SEL(skb->data, 0);
3411 	if (vif->type == NL80211_IFTYPE_STATION)
3412 		SET_CMC_TBL_ULDL(skb->data, 1);
3414 		SET_CMC_TBL_ULDL(skb->data, 0);
3415 	SET_CMC_TBL_MULTI_PORT_ID(skb->data, rtwvif_link->port);
3416 	if (chip->h2c_cctl_func_id == H2C_FUNC_MAC_CCTLINFO_UD_V1) {
3417 		SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(skb->data, pads[RTW89_CHANNEL_WIDTH_20]);
3418 		SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(skb->data, pads[RTW89_CHANNEL_WIDTH_40]);
3419 		SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(skb->data, pads[RTW89_CHANNEL_WIDTH_80]);
3420 		SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(skb->data, pads[RTW89_CHANNEL_WIDTH_160]);
3421 	} else if (chip->h2c_cctl_func_id == H2C_FUNC_MAC_CCTLINFO_UD) {
3422 		SET_CMC_TBL_NOMINAL_PKT_PADDING(skb->data, pads[RTW89_CHANNEL_WIDTH_20]);
3423 		SET_CMC_TBL_NOMINAL_PKT_PADDING40(skb->data, pads[RTW89_CHANNEL_WIDTH_40]);
3424 		SET_CMC_TBL_NOMINAL_PKT_PADDING80(skb->data, pads[RTW89_CHANNEL_WIDTH_80]);
3425 		SET_CMC_TBL_NOMINAL_PKT_PADDING160(skb->data, pads[RTW89_CHANNEL_WIDTH_160]);
3428 		SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(skb->data,
3429 						  link_sta->he_cap.has_he);
3430 	if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE)
3431 		SET_CMC_TBL_DATA_DCM(skb->data, 0);
3437 			      chip->h2c_cctl_func_id, 0, 1,
3446 	return 0;
3458 	u8 nss = min(link_sta->rx_nss, rtwdev->hal.tx_nss) - 1;
3467 	ppe_th = !!u8_get_bits(link_sta->eht_cap.eht_cap_elem.phy_cap_info[5],
3472 		pad = u8_get_bits(link_sta->eht_cap.eht_cap_elem.phy_cap_info[5],
3475 		for (i = 0; i < RTW89_PPE_BW_NUM; i++)
3481 	ppe_thres_hdr = get_unaligned_le16(link_sta->eht_cap.eht_ppe_thres);
3488 	for (i = 0; i < RTW89_PPE_BW_NUM; i++) {
3498 		ppe = get_unaligned_le16(link_sta->eht_cap.eht_ppe_thres + idx);
3517 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
3518 	u8 mac_id = rtwsta_link ? rtwsta_link->mac_id : rtwvif_link->mac_id;
3528 	memset(pads, 0, sizeof(pads));
3533 		return -ENOMEM;
3543 		if (link_sta->eht_cap.has_eht)
3545 		else if (link_sta->he_cap.has_he)
3549 	if (vif->p2p)
3551 	else if (chan->band_type == RTW89_BAND_2G)
3557 	h2c = (struct rtw89_h2c_cctlinfo_ud_g7 *)skb->data;
3559 	h2c->c0 = le32_encode_bits(mac_id, CCTLINFO_G7_C0_MACID) |
3562 	h2c->w0 = le32_encode_bits(1, CCTLINFO_G7_W0_DISRTSFB) |
3564 	h2c->m0 = cpu_to_le32(CCTLINFO_G7_W0_DISRTSFB |
3567 	h2c->w1 = le32_encode_bits(lowest_rate, CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE);
3568 	h2c->m1 = cpu_to_le32(CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE);
3570 	h2c->w2 = le32_encode_bits(0, CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL);
3571 	h2c->m2 = cpu_to_le32(CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL);
3573 	h2c->w3 = le32_encode_bits(0, CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL);
3574 	h2c->m3 = cpu_to_le32(CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL);
3576 	h2c->w4 = le32_encode_bits(rtwvif_link->port, CCTLINFO_G7_W4_MULTI_PORT_ID);
3577 	h2c->m4 = cpu_to_le32(CCTLINFO_G7_W4_MULTI_PORT_ID);
3579 	if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) {
3580 		h2c->w4 |= le32_encode_bits(0, CCTLINFO_G7_W4_DATA_DCM);
3581 		h2c->m4 |= cpu_to_le32(CCTLINFO_G7_W4_DATA_DCM);
3584 	if (bss_conf->eht_support) {
3585 		u16 punct = bss_conf->chanreq.oper.punctured;
3587 		h2c->w4 |= le32_encode_bits(~punct,
3589 		h2c->m4 |= cpu_to_le32(CCTLINFO_G7_W4_ACT_SUBCH_CBW);
3592 	h2c->w5 = le32_encode_bits(pads[RTW89_CHANNEL_WIDTH_20],
3602 	h2c->m5 = cpu_to_le32(CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 |
3608 	h2c->w6 = le32_encode_bits(vif->cfg.aid, CCTLINFO_G7_W6_AID12_PAID) |
3609 		  le32_encode_bits(vif->type == NL80211_IFTYPE_STATION ? 1 : 0,
3611 	h2c->m6 = cpu_to_le32(CCTLINFO_G7_W6_AID12_PAID | CCTLINFO_G7_W6_ULDL);
3614 		h2c->w8 = le32_encode_bits(link_sta->he_cap.has_he,
3616 		h2c->m8 = cpu_to_le32(CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT);
3623 			      H2C_FUNC_MAC_CCTLINFO_UD_G7, 0, 1,
3632 	return 0;
3644 	struct rtw89_sta *rtwsta = rtwsta_link->rtwsta;
3648 	u16 agg_num = 0;
3649 	u8 ba_bmap = 0;
3656 		return -ENOMEM;
3659 	h2c = (struct rtw89_h2c_cctlinfo_ud_g7 *)skb->data;
3661 	for_each_set_bit(tid, rtwsta->ampdu_map, IEEE80211_NUM_TIDS) {
3662 		if (agg_num == 0)
3663 			agg_num = rtwsta->ampdu_params[tid].agg_num;
3665 			agg_num = min(agg_num, rtwsta->ampdu_params[tid].agg_num);
3668 	if (agg_num <= 0x20)
3670 	else if (agg_num > 0x20 && agg_num <= 0x40)
3671 		ba_bmap = 0;
3672 	else if (agg_num > 0x40 && agg_num <= 0x80)
3674 	else if (agg_num > 0x80 && agg_num <= 0x100)
3676 	else if (agg_num > 0x100 && agg_num <= 0x200)
3678 	else if (agg_num > 0x200 && agg_num <= 0x400)
3681 	h2c->c0 = le32_encode_bits(rtwsta_link->mac_id, CCTLINFO_G7_C0_MACID) |
3684 	h2c->w3 = le32_encode_bits(ba_bmap, CCTLINFO_G7_W3_BA_BMAP);
3685 	h2c->m3 = cpu_to_le32(CCTLINFO_G7_W3_BA_BMAP);
3689 			      H2C_FUNC_MAC_CCTLINFO_UD_G7, 0, 0,
3698 	return 0;
3709 	const struct rtw89_chip_info *chip = rtwdev->chip;
3716 		return -ENOMEM;
3719 	SET_CTRL_INFO_MACID(skb->data, rtwsta_link->mac_id);
3720 	SET_CTRL_INFO_OPERATION(skb->data, 1);
3721 	if (rtwsta_link->cctl_tx_time) {
3722 		SET_CMC_TBL_AMPDU_TIME_SEL(skb->data, 1);
3723 		SET_CMC_TBL_AMPDU_MAX_TIME(skb->data, rtwsta_link->ampdu_max_time);
3725 	if (rtwsta_link->cctl_tx_retry_limit) {
3726 		SET_CMC_TBL_DATA_TXCNT_LMT_SEL(skb->data, 1);
3727 		SET_CMC_TBL_DATA_TX_CNT_LMT(skb->data, rtwsta_link->data_tx_cnt_lmt);
3732 			      chip->h2c_cctl_func_id, 0, 1,
3741 	return 0;
3760 		return -ENOMEM;
3763 	h2c = (struct rtw89_h2c_cctlinfo_ud_g7 *)skb->data;
3765 	h2c->c0 = le32_encode_bits(rtwsta_link->mac_id, CCTLINFO_G7_C0_MACID) |
3768 	if (rtwsta_link->cctl_tx_time) {
3769 		h2c->w3 |= le32_encode_bits(1, CCTLINFO_G7_W3_AMPDU_TIME_SEL);
3770 		h2c->m3 |= cpu_to_le32(CCTLINFO_G7_W3_AMPDU_TIME_SEL);
3772 		h2c->w2 |= le32_encode_bits(rtwsta_link->ampdu_max_time,
3774 		h2c->m2 |= cpu_to_le32(CCTLINFO_G7_W2_AMPDU_MAX_TIME);
3776 	if (rtwsta_link->cctl_tx_retry_limit) {
3777 		h2c->w2 |= le32_encode_bits(1, CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL) |
3778 			   le32_encode_bits(rtwsta_link->data_tx_cnt_lmt,
3780 		h2c->m2 |= cpu_to_le32(CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL |
3786 			      H2C_FUNC_MAC_CCTLINFO_UD_G7, 0, 1,
3795 	return 0;
3815 		return -ENOMEM;
3819 	h2c = (struct rtw89_h2c_cctlinfo_ud_g7 *)skb->data;
3821 	h2c->c0 = le32_encode_bits(rtwvif_link->mac_id, CCTLINFO_G7_C0_MACID) |
3824 	h2c->w4 = le32_encode_bits(~punctured, CCTLINFO_G7_W4_ACT_SUBCH_CBW);
3825 	h2c->m4 = cpu_to_le32(CCTLINFO_G7_W4_ACT_SUBCH_CBW);
3829 			      H2C_FUNC_MAC_CCTLINFO_UD_G7, 0, 1,
3838 	return 0;
3849 	const struct rtw89_chip_info *chip = rtwdev->chip;
3853 	if (chip->h2c_cctl_func_id != H2C_FUNC_MAC_CCTLINFO_UD)
3854 		return 0;
3859 		return -ENOMEM;
3862 	SET_CTRL_INFO_MACID(skb->data, rtwsta_link->mac_id);
3863 	SET_CTRL_INFO_OPERATION(skb->data, 1);
3869 			      H2C_FUNC_MAC_CCTLINFO_UD, 0, 1,
3878 	return 0;
3889 						       rtwvif_link->chanctx_idx);
3903 	if (vif->p2p)
3905 	else if (chan->band_type == RTW89_BAND_2G)
3910 	skb_beacon = ieee80211_beacon_get_tim(rtwdev->hw, vif, &tim_offset,
3911 					      NULL, 0);
3914 		return -ENOMEM;
3920 	     pskb_expand_head(skb_beacon, 0, noa_len, GFP_KERNEL) == 0)) {
3925 	tim_offset -= ieee80211_hdrlen(hdr->frame_control);
3927 	bcn_total_len = len + skb_beacon->len;
3932 		return -ENOMEM;
3935 	h2c = (struct rtw89_h2c_bcn_upd *)skb->data;
3937 	h2c->w0 = le32_encode_bits(rtwvif_link->port, RTW89_H2C_BCN_UPD_W0_PORT) |
3938 		  le32_encode_bits(0, RTW89_H2C_BCN_UPD_W0_MBSSID) |
3939 		  le32_encode_bits(rtwvif_link->mac_idx, RTW89_H2C_BCN_UPD_W0_BAND) |
3941 	h2c->w1 = le32_encode_bits(rtwvif_link->mac_id, RTW89_H2C_BCN_UPD_W1_MACID) |
3946 	skb_put_data(skb, skb_beacon->data, skb_beacon->len);
3951 			      H2C_FUNC_MAC_BCN_UPD, 0, 1,
3961 	return 0;
3968 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
3982 	if (vif->p2p)
3984 	else if (chan->band_type == RTW89_BAND_2G)
3989 	skb_beacon = ieee80211_beacon_get_tim(rtwdev->hw, vif, &tim_offset,
3990 					      NULL, 0);
3993 		return -ENOMEM;
3999 	     pskb_expand_head(skb_beacon, 0, noa_len, GFP_KERNEL) == 0)) {
4004 	tim_offset -= ieee80211_hdrlen(hdr->frame_control);
4006 	bcn_total_len = len + skb_beacon->len;
4011 		return -ENOMEM;
4014 	h2c = (struct rtw89_h2c_bcn_upd_be *)skb->data;
4016 	h2c->w0 = le32_encode_bits(rtwvif_link->port, RTW89_H2C_BCN_UPD_BE_W0_PORT) |
4017 		  le32_encode_bits(0, RTW89_H2C_BCN_UPD_BE_W0_MBSSID) |
4018 		  le32_encode_bits(rtwvif_link->mac_idx, RTW89_H2C_BCN_UPD_BE_W0_BAND) |
4020 	h2c->w1 = le32_encode_bits(rtwvif_link->mac_id, RTW89_H2C_BCN_UPD_BE_W1_MACID) |
4025 	skb_put_data(skb, skb_beacon->data, skb_beacon->len);
4030 			      H2C_FUNC_MAC_BCN_UPD_BE, 0, 1,
4039 	return 0;
4053 	u8 mac_id = rtwsta_link ? rtwsta_link->mac_id : rtwvif_link->mac_id;
4060 	if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) {
4064 			self_role = rtwvif_link->self_role;
4066 		self_role = rtwvif_link->self_role;
4072 		return -ENOMEM;
4075 	h2c = (struct rtw89_h2c_role_maintain *)skb->data;
4077 	h2c->w0 = le32_encode_bits(mac_id, RTW89_H2C_ROLE_MAINTAIN_W0_MACID) |
4080 		  le32_encode_bits(rtwvif_link->wifi_role,
4082 		  le32_encode_bits(rtwvif_link->mac_idx,
4084 		  le32_encode_bits(rtwvif_link->port, RTW89_H2C_ROLE_MAINTAIN_W0_PORT);
4088 			      H2C_FUNC_MAC_FWROLE_MAINTAIN, 0, 1,
4097 	return 0;
4119 	if (link_sta->eht_cap.has_eht)
4121 	else if (link_sta->he_cap.has_he)
4131 	if (bss_conf->eht_support)
4133 	else if (bss_conf->he_support)
4147 	u8 mac_id = rtwsta_link ? rtwsta_link->mac_id : rtwvif_link->mac_id;
4150 	u8 self_role = rtwvif_link->self_role;
4152 	u8 net_type = rtwvif_link->net_type;
4162 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) {
4175 		return -ENOMEM;
4178 	h2c = (struct rtw89_h2c_join *)skb->data;
4180 	h2c->w0 = le32_encode_bits(mac_id, RTW89_H2C_JOININFO_W0_MACID) |
4182 		  le32_encode_bits(rtwvif_link->mac_idx, RTW89_H2C_JOININFO_W0_BAND) |
4183 		  le32_encode_bits(rtwvif_link->wmm, RTW89_H2C_JOININFO_W0_WMM) |
4184 		  le32_encode_bits(rtwvif_link->trigger, RTW89_H2C_JOININFO_W0_TGR) |
4185 		  le32_encode_bits(0, RTW89_H2C_JOININFO_W0_ISHESTA) |
4186 		  le32_encode_bits(0, RTW89_H2C_JOININFO_W0_DLBW) |
4187 		  le32_encode_bits(0, RTW89_H2C_JOININFO_W0_TF_MAC_PAD) |
4188 		  le32_encode_bits(0, RTW89_H2C_JOININFO_W0_DL_T_PE) |
4189 		  le32_encode_bits(rtwvif_link->port, RTW89_H2C_JOININFO_W0_PORT_ID) |
4191 		  le32_encode_bits(rtwvif_link->wifi_role,
4198 	h2c_v1 = (struct rtw89_h2c_join_v1 *)skb->data;
4201 	init_ps = rtwvif_link != rtw89_get_designated_link(rtwvif_link->rtwvif);
4204 		main_mac_id = rtw89_sta_get_main_macid(rtwsta_link->rtwsta);
4206 		main_mac_id = rtw89_vif_get_main_macid(rtwvif_link->rtwvif);
4208 	h2c_v1->w1 = le32_encode_bits(sta_type, RTW89_H2C_JOININFO_W1_STA_TYPE) |
4213 		     le32_encode_bits(0, RTW89_H2C_JOININFO_W1_EMLSR_CAB) |
4214 		     le32_encode_bits(0, RTW89_H2C_JOININFO_W1_NSTR_EN) |
4220 		     le32_encode_bits(0, RTW89_H2C_JOININFO_W2_MACID_EXT) |
4221 		     le32_encode_bits(0, RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT);
4223 	h2c_v1->w2 = 0;
4228 			      H2C_FUNC_MAC_JOININFO, 0, 1,
4237 	return 0;
4244 int rtw89_fw_h2c_notify_dbcc(struct rtw89_dev *rtwdev, bool en)  argument
4254 		return -ENOMEM;
4257 	h2c = (struct rtw89_h2c_notify_dbcc *)skb->data;
4259 	h2c->w0 = le32_encode_bits(en, RTW89_H2C_NOTIFY_DBCC_EN);
4263 			      H2C_FUNC_NOTIFY_DBCC, 0, 1,
4272 	return 0;
4290 	if (RTW89_CHK_FW_FEATURE(MACID_PAUSE_SLEEP, &rtwdev->fw)) {
4301 		return -ENOMEM;
4306 		h2c_new = (struct rtw89_fw_macid_pause_sleep_grp *)skb->data;
4308 		h2c_new->n[0].pause_mask_grp[grp] = set;
4309 		h2c_new->n[0].sleep_mask_grp[grp] = set;
4311 			h2c_new->n[0].pause_grp[grp] = set;
4312 			h2c_new->n[0].sleep_grp[grp] = set;
4315 		h2c = (struct rtw89_fw_macid_pause_grp *)skb->data;
4317 		h2c->mask_grp[grp] = set;
4319 			h2c->pause_grp[grp] = set;
4324 			      h2c_macid_pause_id, 1, 0,
4333 	return 0;
4350 		return -ENOMEM;
4353 	RTW89_SET_EDCA_SEL(skb->data, 0);
4354 	RTW89_SET_EDCA_BAND(skb->data, rtwvif_link->mac_idx);
4355 	RTW89_SET_EDCA_WMM(skb->data, 0);
4356 	RTW89_SET_EDCA_AC(skb->data, ac);
4357 	RTW89_SET_EDCA_PARAM(skb->data, val);
4361 			      H2C_FUNC_USR_EDCA, 0, 1,
4370 	return 0;
4380 			      bool en)  argument
4383 	u16 early_us = en ? 2000 : 0;
4390 		return -ENOMEM;
4393 	cmd = skb->data;
4395 	RTW89_SET_FWCMD_TSF32_TOGL_BAND(cmd, rtwvif_link->mac_idx);
4396 	RTW89_SET_FWCMD_TSF32_TOGL_EN(cmd, en);
4397 	RTW89_SET_FWCMD_TSF32_TOGL_PORT(cmd, rtwvif_link->port);
4402 			      H2C_FUNC_TSF32_TOGL, 0, 0,
4411 	return 0;
4421 	static const u8 cfg[] = {0x09, 0x00, 0x00, 0x00, 0x5e, 0x00, 0x00, 0x00};
4428 		return -ENOMEM;
4434 			      H2C_FUNC_OFLD_CFG, 0, 1,
4443 	return 0;
4461 		return -ENOMEM;
4465 	h2c = (struct rtw89_h2c_tx_duty *)skb->data;
4469 	if (lv == 0 || lv > RTW89_THERMAL_PROT_LV_MAX) {
4470 		h2c->w1 = le32_encode_bits(1, RTW89_H2C_TX_DUTY_W1_STOP);
4472 		active = 100 - lv * RTW89_THERMAL_PROT_STEP;
4473 		pause = 100 - active;
4475 		h2c->w0 = le32_encode_bits(pause, RTW89_H2C_TX_DUTY_W0_PAUSE_INTVL_MASK) |
4481 			      H2C_FUNC_TX_DUTY, 0, 0, len);
4489 	return 0;
4509 	if (!RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw))
4510 		return -EINVAL;
4512 	if (!rtwvif_link || rtwvif_link->net_type != RTW89_NET_TYPE_INFRA)
4513 		return -EINVAL;
4519 	if (bss_conf->cqm_rssi_hyst)
4520 		hyst = bss_conf->cqm_rssi_hyst;
4521 	if (bss_conf->cqm_rssi_thold)
4522 		thold = bss_conf->cqm_rssi_thold;
4529 		return -ENOMEM;
4533 	h2c = (struct rtw89_h2c_bcnfltr *)skb->data;
4535 	if (RTW89_CHK_FW_FEATURE(BEACON_LOSS_COUNT_V1, &rtwdev->fw))
4536 		max_cnt = BIT(7) - 1;
4538 		max_cnt = BIT(4) - 1;
4542 	h2c->w0 = le32_encode_bits(connect, RTW89_H2C_BCNFLTR_W0_MON_RSSI) |
4548 		  le32_encode_bits(cnt & 0xf, RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT_L4) |
4552 		  le32_encode_bits(rtwvif_link->mac_id, RTW89_H2C_BCNFLTR_W0_MAC_ID);
4556 			      H2C_FUNC_CFG_BCNFLTR, 0, 1, len);
4564 	return 0;
4580 	if (!RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw))
4581 		return -EINVAL;
4584 		return -EINVAL;
4589 		return -ENOMEM;
4592 	rssi = phy_ppdu->rssi_avg >> RSSI_FACTOR;
4594 	h2c = (struct rtw89_h2c_ofld_rssi *)skb->data;
4596 	h2c->w0 = le32_encode_bits(phy_ppdu->mac_id, RTW89_H2C_OFLD_RSSI_W0_MACID) |
4598 	h2c->w1 = le32_encode_bits(rssi, RTW89_H2C_OFLD_RSSI_W1_VAL);
4602 			      H2C_FUNC_OFLD_RSSI, 0, 1, len);
4610 	return 0;
4619 	struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
4620 	struct rtw89_traffic_stats *stats = &rtwvif->stats;
4626 	if (rtwvif_link->net_type != RTW89_NET_TYPE_INFRA)
4627 		return -EINVAL;
4632 		return -ENOMEM;
4636 	h2c = (struct rtw89_h2c_ofld *)skb->data;
4638 	h2c->w0 = le32_encode_bits(rtwvif_link->mac_id, RTW89_H2C_OFLD_W0_MAC_ID) |
4639 		  le32_encode_bits(stats->tx_throughput, RTW89_H2C_OFLD_W0_TX_TP) |
4640 		  le32_encode_bits(stats->rx_throughput, RTW89_H2C_OFLD_W0_RX_TP);
4644 			      H2C_FUNC_OFLD_TP, 0, 1, len);
4652 	return 0;
4659 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi)  argument
4661 	const struct rtw89_chip_info *chip = rtwdev->chip;
4669 	if (chip->chip_gen == RTW89_CHIP_BE) {
4677 		return -ENOMEM;
4680 	h2c = (struct rtw89_h2c_ra *)skb->data;
4683 		    "ra cmd msk: %llx ", ra->ra_mask);
4685 		    "ra cmd msk: %jx ", (uintmax_t)ra->ra_mask);
4688 	h2c->w0 = le32_encode_bits(ra->mode_ctrl, RTW89_H2C_RA_W0_MODE) |
4689 		  le32_encode_bits(ra->bw_cap, RTW89_H2C_RA_W0_BW_CAP) |
4690 		  le32_encode_bits(ra->macid, RTW89_H2C_RA_W0_MACID) |
4691 		  le32_encode_bits(ra->dcm_cap, RTW89_H2C_RA_W0_DCM) |
4692 		  le32_encode_bits(ra->er_cap, RTW89_H2C_RA_W0_ER) |
4693 		  le32_encode_bits(ra->init_rate_lv, RTW89_H2C_RA_W0_INIT_RATE_LV) |
4694 		  le32_encode_bits(ra->upd_all, RTW89_H2C_RA_W0_UPD_ALL) |
4695 		  le32_encode_bits(ra->en_sgi, RTW89_H2C_RA_W0_SGI) |
4696 		  le32_encode_bits(ra->ldpc_cap, RTW89_H2C_RA_W0_LDPC) |
4697 		  le32_encode_bits(ra->stbc_cap, RTW89_H2C_RA_W0_STBC) |
4698 		  le32_encode_bits(ra->ss_num, RTW89_H2C_RA_W0_SS_NUM) |
4699 		  le32_encode_bits(ra->giltf, RTW89_H2C_RA_W0_GILTF) |
4700 		  le32_encode_bits(ra->upd_bw_nss_mask, RTW89_H2C_RA_W0_UPD_BW_NSS_MASK) |
4701 		  le32_encode_bits(ra->upd_mask, RTW89_H2C_RA_W0_UPD_MASK);
4702 	h2c->w1 = le32_encode_bits(ra->ra_mask, RTW89_H2C_RA_W1_RAMASK_LO32);
4703 	h2c->w2 = le32_encode_bits(ra->ra_mask >> 32, RTW89_H2C_RA_W2_RAMASK_HI32);
4704 	h2c->w3 = le32_encode_bits(ra->fix_giltf_en, RTW89_H2C_RA_W3_FIX_GILTF_EN) |
4705 		  le32_encode_bits(ra->fix_giltf, RTW89_H2C_RA_W3_FIX_GILTF);
4708 		goto csi;
4711 	h2c_v1->w4 = le32_encode_bits(ra->mode_ctrl, RTW89_H2C_RA_V1_W4_MODE_EHT) |
4712 		     le32_encode_bits(ra->bw_cap, RTW89_H2C_RA_V1_W4_BW_EHT);
4714 csi:
4715 	if (!csi)
4718 	h2c->w2 |= le32_encode_bits(1, RTW89_H2C_RA_W2_BFEE_CSI_CTL);
4719 	h2c->w3 |= le32_encode_bits(ra->band_num, RTW89_H2C_RA_W3_BAND_NUM) |
4720 		   le32_encode_bits(ra->cr_tbl_sel, RTW89_H2C_RA_W3_CR_TBL_SEL) |
4721 		   le32_encode_bits(ra->fixed_csi_rate_en, RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN) |
4722 		   le32_encode_bits(ra->ra_csi_rate_en, RTW89_H2C_RA_W3_RA_CSI_RATE_EN) |
4723 		   le32_encode_bits(ra->csi_mcs_ss_idx, RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX) |
4724 		   le32_encode_bits(ra->csi_mode, RTW89_H2C_RA_W3_FIXED_CSI_MODE) |
4725 		   le32_encode_bits(ra->csi_gi_ltf, RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF) |
4726 		   le32_encode_bits(ra->csi_bw, RTW89_H2C_RA_W3_FIXED_CSI_BW);
4731 			      H2C_FUNC_OUTSRC_RA_MACIDCFG, 0, 0,
4740 	return 0;
4749 	struct rtw89_btc *btc = &rtwdev->btc;
4750 	struct rtw89_btc_dm *dm = &btc->dm;
4751 	struct rtw89_btc_init_info *init_info = &dm->init_info.init;
4752 	struct rtw89_btc_module *module = &init_info->module;
4753 	struct rtw89_btc_ant_info *ant = &module->ant;
4762 		return -ENOMEM;
4765 	h2c = (struct rtw89_h2c_cxinit *)skb->data;
4767 	h2c->hdr.type = type;
4768 	h2c->hdr.len = len - H2C_LEN_CXDRVHDR;
4770 	h2c->ant_type = ant->type;
4771 	h2c->ant_num = ant->num;
4772 	h2c->ant_iso = ant->isolation;
4773 	h2c->ant_info =
4774 		u8_encode_bits(ant->single_pos, RTW89_H2C_CXINIT_ANT_INFO_POS) |
4775 		u8_encode_bits(ant->diversity, RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY) |
4776 		u8_encode_bits(ant->btg_pos, RTW89_H2C_CXINIT_ANT_INFO_BTG_POS) |
4777 		u8_encode_bits(ant->stream_cnt, RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT);
4779 	h2c->mod_rfe = module->rfe_type;
4780 	h2c->mod_cv = module->cv;
4781 	h2c->mod_info =
4782 		u8_encode_bits(module->bt_solo, RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO) |
4783 		u8_encode_bits(module->bt_pos, RTW89_H2C_CXINIT_MOD_INFO_BT_POS) |
4784 		u8_encode_bits(module->switch_type, RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE) |
4785 		u8_encode_bits(module->wa_type, RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE);
4786 	h2c->mod_adie_kt = module->kt_ver_adie;
4787 	h2c->wl_gch = init_info->wl_guard_ch;
4789 	h2c->info =
4790 		u8_encode_bits(init_info->wl_only, RTW89_H2C_CXINIT_INFO_WL_ONLY) |
4791 		u8_encode_bits(init_info->wl_init_ok, RTW89_H2C_CXINIT_INFO_WL_INITOK) |
4792 		u8_encode_bits(init_info->dbcc_en, RTW89_H2C_CXINIT_INFO_DBCC_EN) |
4793 		u8_encode_bits(init_info->cx_other, RTW89_H2C_CXINIT_INFO_CX_OTHER) |
4794 		u8_encode_bits(init_info->bt_only, RTW89_H2C_CXINIT_INFO_BT_ONLY);
4798 			      SET_DRV_INFO, 0, 0,
4807 	return 0;
4816 	struct rtw89_btc *btc = &rtwdev->btc;
4817 	struct rtw89_btc_dm *dm = &btc->dm;
4818 	struct rtw89_btc_init_info_v7 *init_info = &dm->init_info.init_v7;
4827 		return -ENOMEM;
4830 	h2c = (struct rtw89_h2c_cxinit_v7 *)skb->data;
4832 	h2c->hdr.type = type;
4833 	h2c->hdr.ver = btc->ver->fcxinit;
4834 	h2c->hdr.len = len - H2C_LEN_CXDRVHDR_V7;
4835 	h2c->init = *init_info;
4839 			      SET_DRV_INFO, 0, 0,
4848 	return 0;
4862 	struct rtw89_btc *btc = &rtwdev->btc;
4863 	const struct rtw89_btc_ver *ver = btc->ver;
4864 	struct rtw89_btc_wl_info *wl = &btc->cx.wl;
4865 	struct rtw89_btc_wl_role_info *role_info = &wl->role_info;
4866 	struct rtw89_btc_wl_role_info_bpos *bpos = &role_info->role_map.role;
4867 	struct rtw89_btc_wl_active_role *active = role_info->active_role;
4870 	u8 offset = 0;
4875 	len = H2C_LEN_CXDRVINFO_ROLE_SIZE(ver->max_role_num);
4880 		return -ENOMEM;
4883 	cmd = skb->data;
4886 	RTW89_SET_FWCMD_CXHDR_LEN(cmd, len - H2C_LEN_CXDRVHDR);
4888 	RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, role_info->connect_cnt);
4889 	RTW89_SET_FWCMD_CXROLE_LINK_MODE(cmd, role_info->link_mode);
4891 	RTW89_SET_FWCMD_CXROLE_ROLE_NONE(cmd, bpos->none);
4892 	RTW89_SET_FWCMD_CXROLE_ROLE_STA(cmd, bpos->station);
4893 	RTW89_SET_FWCMD_CXROLE_ROLE_AP(cmd, bpos->ap);
4894 	RTW89_SET_FWCMD_CXROLE_ROLE_VAP(cmd, bpos->vap);
4895 	RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(cmd, bpos->adhoc);
4896 	RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(cmd, bpos->adhoc_master);
4897 	RTW89_SET_FWCMD_CXROLE_ROLE_MESH(cmd, bpos->mesh);
4898 	RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(cmd, bpos->moniter);
4899 	RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(cmd, bpos->p2p_device);
4900 	RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(cmd, bpos->p2p_gc);
4901 	RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(cmd, bpos->p2p_go);
4902 	RTW89_SET_FWCMD_CXROLE_ROLE_NAN(cmd, bpos->nan);
4904 	for (i = 0; i < RTW89_PORT_NUM; i++, active++) {
4905 		RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(cmd, active->connected, i, offset);
4906 		RTW89_SET_FWCMD_CXROLE_ACT_PID(cmd, active->pid, i, offset);
4907 		RTW89_SET_FWCMD_CXROLE_ACT_PHY(cmd, active->phy, i, offset);
4908 		RTW89_SET_FWCMD_CXROLE_ACT_NOA(cmd, active->noa, i, offset);
4909 		RTW89_SET_FWCMD_CXROLE_ACT_BAND(cmd, active->band, i, offset);
4910 		RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(cmd, active->client_ps, i, offset);
4911 		RTW89_SET_FWCMD_CXROLE_ACT_BW(cmd, active->bw, i, offset);
4912 		RTW89_SET_FWCMD_CXROLE_ACT_ROLE(cmd, active->role, i, offset);
4913 		RTW89_SET_FWCMD_CXROLE_ACT_CH(cmd, active->ch, i, offset);
4914 		RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(cmd, active->tx_lvl, i, offset);
4915 		RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(cmd, active->rx_lvl, i, offset);
4916 		RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(cmd, active->tx_rate, i, offset);
4917 		RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(cmd, active->rx_rate, i, offset);
4922 			      SET_DRV_INFO, 0, 0,
4931 	return 0;
4943 	struct rtw89_btc *btc = &rtwdev->btc;
4944 	const struct rtw89_btc_ver *ver = btc->ver;
4945 	struct rtw89_btc_wl_info *wl = &btc->cx.wl;
4946 	struct rtw89_btc_wl_role_info_v1 *role_info = &wl->role_info_v1;
4947 	struct rtw89_btc_wl_role_info_bpos *bpos = &role_info->role_map.role;
4948 	struct rtw89_btc_wl_active_role_v1 *active = role_info->active_role_v1;
4955 	len = H2C_LEN_CXDRVINFO_ROLE_SIZE_V1(ver->max_role_num);
4960 		return -ENOMEM;
4963 	cmd = skb->data;
4966 	RTW89_SET_FWCMD_CXHDR_LEN(cmd, len - H2C_LEN_CXDRVHDR);
4968 	RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, role_info->connect_cnt);
4969 	RTW89_SET_FWCMD_CXROLE_LINK_MODE(cmd, role_info->link_mode);
4971 	RTW89_SET_FWCMD_CXROLE_ROLE_NONE(cmd, bpos->none);
4972 	RTW89_SET_FWCMD_CXROLE_ROLE_STA(cmd, bpos->station);
4973 	RTW89_SET_FWCMD_CXROLE_ROLE_AP(cmd, bpos->ap);
4974 	RTW89_SET_FWCMD_CXROLE_ROLE_VAP(cmd, bpos->vap);
4975 	RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(cmd, bpos->adhoc);
4976 	RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(cmd, bpos->adhoc_master);
4977 	RTW89_SET_FWCMD_CXROLE_ROLE_MESH(cmd, bpos->mesh);
4978 	RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(cmd, bpos->moniter);
4979 	RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(cmd, bpos->p2p_device);
4980 	RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(cmd, bpos->p2p_gc);
4981 	RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(cmd, bpos->p2p_go);
4982 	RTW89_SET_FWCMD_CXROLE_ROLE_NAN(cmd, bpos->nan);
4985 	for (i = 0; i < RTW89_PORT_NUM; i++, active++) {
4986 		RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(cmd, active->connected, i, offset);
4987 		RTW89_SET_FWCMD_CXROLE_ACT_PID(cmd, active->pid, i, offset);
4988 		RTW89_SET_FWCMD_CXROLE_ACT_PHY(cmd, active->phy, i, offset);
4989 		RTW89_SET_FWCMD_CXROLE_ACT_NOA(cmd, active->noa, i, offset);
4990 		RTW89_SET_FWCMD_CXROLE_ACT_BAND(cmd, active->band, i, offset);
4991 		RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(cmd, active->client_ps, i, offset);
4992 		RTW89_SET_FWCMD_CXROLE_ACT_BW(cmd, active->bw, i, offset);
4993 		RTW89_SET_FWCMD_CXROLE_ACT_ROLE(cmd, active->role, i, offset);
4994 		RTW89_SET_FWCMD_CXROLE_ACT_CH(cmd, active->ch, i, offset);
4995 		RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(cmd, active->tx_lvl, i, offset);
4996 		RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(cmd, active->rx_lvl, i, offset);
4997 		RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(cmd, active->tx_rate, i, offset);
4998 		RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(cmd, active->rx_rate, i, offset);
4999 		RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(cmd, active->noa_duration, i, offset);
5002 	offset = len - H2C_LEN_CXDRVINFO_ROLE_DBCC_LEN;
5003 	RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(cmd, role_info->mrole_type, offset);
5004 	RTW89_SET_FWCMD_CXROLE_MROLE_NOA(cmd, role_info->mrole_noa_duration, offset);
5005 	RTW89_SET_FWCMD_CXROLE_DBCC_EN(cmd, role_info->dbcc_en, offset);
5006 	RTW89_SET_FWCMD_CXROLE_DBCC_CHG(cmd, role_info->dbcc_chg, offset);
5007 	RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(cmd, role_info->dbcc_2g_phy, offset);
5008 	RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(cmd, role_info->link_mode_chg, offset);
5012 			      SET_DRV_INFO, 0, 0,
5021 	return 0;
5033 	struct rtw89_btc *btc = &rtwdev->btc;
5034 	const struct rtw89_btc_ver *ver = btc->ver;
5035 	struct rtw89_btc_wl_info *wl = &btc->cx.wl;
5036 	struct rtw89_btc_wl_role_info_v2 *role_info = &wl->role_info_v2;
5037 	struct rtw89_btc_wl_role_info_bpos *bpos = &role_info->role_map.role;
5038 	struct rtw89_btc_wl_active_role_v2 *active = role_info->active_role_v2;
5045 	len = H2C_LEN_CXDRVINFO_ROLE_SIZE_V2(ver->max_role_num);
5050 		return -ENOMEM;
5053 	cmd = skb->data;
5056 	RTW89_SET_FWCMD_CXHDR_LEN(cmd, len - H2C_LEN_CXDRVHDR);
5058 	RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, role_info->connect_cnt);
5059 	RTW89_SET_FWCMD_CXROLE_LINK_MODE(cmd, role_info->link_mode);
5061 	RTW89_SET_FWCMD_CXROLE_ROLE_NONE(cmd, bpos->none);
5062 	RTW89_SET_FWCMD_CXROLE_ROLE_STA(cmd, bpos->station);
5063 	RTW89_SET_FWCMD_CXROLE_ROLE_AP(cmd, bpos->ap);
5064 	RTW89_SET_FWCMD_CXROLE_ROLE_VAP(cmd, bpos->vap);
5065 	RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(cmd, bpos->adhoc);
5066 	RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(cmd, bpos->adhoc_master);
5067 	RTW89_SET_FWCMD_CXROLE_ROLE_MESH(cmd, bpos->mesh);
5068 	RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(cmd, bpos->moniter);
5069 	RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(cmd, bpos->p2p_device);
5070 	RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(cmd, bpos->p2p_gc);
5071 	RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(cmd, bpos->p2p_go);
5072 	RTW89_SET_FWCMD_CXROLE_ROLE_NAN(cmd, bpos->nan);
5075 	for (i = 0; i < RTW89_PORT_NUM; i++, active++) {
5076 		RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(cmd, active->connected, i, offset);
5077 		RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(cmd, active->pid, i, offset);
5078 		RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(cmd, active->phy, i, offset);
5079 		RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(cmd, active->noa, i, offset);
5080 		RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(cmd, active->band, i, offset);
5081 		RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(cmd, active->client_ps, i, offset);
5082 		RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(cmd, active->bw, i, offset);
5083 		RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(cmd, active->role, i, offset);
5084 		RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(cmd, active->ch, i, offset);
5085 		RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(cmd, active->noa_duration, i, offset);
5088 	offset = len - H2C_LEN_CXDRVINFO_ROLE_DBCC_LEN;
5089 	RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(cmd, role_info->mrole_type, offset);
5090 	RTW89_SET_FWCMD_CXROLE_MROLE_NOA(cmd, role_info->mrole_noa_duration, offset);
5091 	RTW89_SET_FWCMD_CXROLE_DBCC_EN(cmd, role_info->dbcc_en, offset);
5092 	RTW89_SET_FWCMD_CXROLE_DBCC_CHG(cmd, role_info->dbcc_chg, offset);
5093 	RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(cmd, role_info->dbcc_2g_phy, offset);
5094 	RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(cmd, role_info->link_mode_chg, offset);
5098 			      SET_DRV_INFO, 0, 0,
5107 	return 0;
5116 	struct rtw89_btc *btc = &rtwdev->btc;
5117 	struct rtw89_btc_wl_role_info_v7 *role = &btc->cx.wl.role_info_v7;
5126 		return -ENOMEM;
5129 	h2c = (struct rtw89_h2c_cxrole_v7 *)skb->data;
5131 	h2c->hdr.type = type;
5132 	h2c->hdr.ver = btc->ver->fwlrole;
5133 	h2c->hdr.len = len - H2C_LEN_CXDRVHDR_V7;
5134 	memcpy(&h2c->_u8, role, sizeof(h2c->_u8));
5135 	h2c->_u32.role_map = cpu_to_le32(role->role_map);
5136 	h2c->_u32.mrole_type = cpu_to_le32(role->mrole_type);
5137 	h2c->_u32.mrole_noa_duration = cpu_to_le32(role->mrole_noa_duration);
5138 	h2c->_u32.dbcc_en = cpu_to_le32(role->dbcc_en);
5139 	h2c->_u32.dbcc_chg = cpu_to_le32(role->dbcc_chg);
5140 	h2c->_u32.dbcc_2g_phy = cpu_to_le32(role->dbcc_2g_phy);
5144 			      SET_DRV_INFO, 0, 0,
5153 	return 0;
5162 	struct rtw89_btc *btc = &rtwdev->btc;
5163 	struct rtw89_btc_wl_role_info_v8 *role = &btc->cx.wl.role_info_v8;
5172 		return -ENOMEM;
5175 	h2c = (struct rtw89_h2c_cxrole_v8 *)skb->data;
5177 	h2c->hdr.type = type;
5178 	h2c->hdr.ver = btc->ver->fwlrole;
5179 	h2c->hdr.len = len - H2C_LEN_CXDRVHDR_V7;
5180 	memcpy(&h2c->_u8, role, sizeof(h2c->_u8));
5181 	h2c->_u32.role_map = cpu_to_le32(role->role_map);
5182 	h2c->_u32.mrole_type = cpu_to_le32(role->mrole_type);
5183 	h2c->_u32.mrole_noa_duration = cpu_to_le32(role->mrole_noa_duration);
5187 			      SET_DRV_INFO, 0, 0,
5196 	return 0;
5205 	struct rtw89_btc *btc = &rtwdev->btc;
5206 	struct rtw89_btc_fbtc_outsrc_set_info *osi = &btc->dm.ost_info;
5215 		return -ENOMEM;
5218 	h2c = (struct rtw89_h2c_cxosi *)skb->data;
5220 	h2c->hdr.type = type;
5221 	h2c->hdr.ver = btc->ver->fcxosi;
5222 	h2c->hdr.len = len - H2C_LEN_CXDRVHDR_V7;
5223 	h2c->osi = *osi;
5227 			      SET_DRV_INFO, 0, 0,
5236 	return 0;
5246 	struct rtw89_btc *btc = &rtwdev->btc;
5247 	const struct rtw89_btc_ver *ver = btc->ver;
5248 	struct rtw89_btc_ctrl *ctrl = &btc->ctrl.ctrl;
5256 		return -ENOMEM;
5259 	cmd = skb->data;
5262 	RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_CTRL - H2C_LEN_CXDRVHDR);
5264 	RTW89_SET_FWCMD_CXCTRL_MANUAL(cmd, ctrl->manual);
5265 	RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(cmd, ctrl->igno_bt);
5266 	RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(cmd, ctrl->always_freerun);
5267 	if (ver->fcxctrl == 0)
5268 		RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(cmd, ctrl->trace_step);
5272 			      SET_DRV_INFO, 0, 0,
5281 	return 0;
5290 	struct rtw89_btc *btc = &rtwdev->btc;
5291 	struct rtw89_btc_ctrl_v7 *ctrl = &btc->ctrl.ctrl_v7;
5300 		return -ENOMEM;
5303 	h2c = (struct rtw89_h2c_cxctrl_v7 *)skb->data;
5305 	h2c->hdr.type = type;
5306 	h2c->hdr.ver = btc->ver->fcxctrl;
5307 	h2c->hdr.len = sizeof(*h2c) - H2C_LEN_CXDRVHDR_V7;
5308 	h2c->ctrl = *ctrl;
5312 			      SET_DRV_INFO, 0, 0, len);
5320 	return 0;
5330 	struct rtw89_btc *btc = &rtwdev->btc;
5331 	struct rtw89_btc_trx_info *trx = &btc->dm.trx_info;
5339 		return -ENOMEM;
5342 	cmd = skb->data;
5345 	RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_TRX - H2C_LEN_CXDRVHDR);
5347 	RTW89_SET_FWCMD_CXTRX_TXLV(cmd, trx->tx_lvl);
5348 	RTW89_SET_FWCMD_CXTRX_RXLV(cmd, trx->rx_lvl);
5349 	RTW89_SET_FWCMD_CXTRX_WLRSSI(cmd, trx->wl_rssi);
5350 	RTW89_SET_FWCMD_CXTRX_BTRSSI(cmd, trx->bt_rssi);
5351 	RTW89_SET_FWCMD_CXTRX_TXPWR(cmd, trx->tx_power);
5352 	RTW89_SET_FWCMD_CXTRX_RXGAIN(cmd, trx->rx_gain);
5353 	RTW89_SET_FWCMD_CXTRX_BTTXPWR(cmd, trx->bt_tx_power);
5354 	RTW89_SET_FWCMD_CXTRX_BTRXGAIN(cmd, trx->bt_rx_gain);
5355 	RTW89_SET_FWCMD_CXTRX_CN(cmd, trx->cn);
5356 	RTW89_SET_FWCMD_CXTRX_NHM(cmd, trx->nhm);
5357 	RTW89_SET_FWCMD_CXTRX_BTPROFILE(cmd, trx->bt_profile);
5358 	RTW89_SET_FWCMD_CXTRX_RSVD2(cmd, trx->rsvd2);
5359 	RTW89_SET_FWCMD_CXTRX_TXRATE(cmd, trx->tx_rate);
5360 	RTW89_SET_FWCMD_CXTRX_RXRATE(cmd, trx->rx_rate);
5361 	RTW89_SET_FWCMD_CXTRX_TXTP(cmd, trx->tx_tp);
5362 	RTW89_SET_FWCMD_CXTRX_RXTP(cmd, trx->rx_tp);
5363 	RTW89_SET_FWCMD_CXTRX_RXERRRA(cmd, trx->rx_err_ratio);
5367 			      SET_DRV_INFO, 0, 0,
5376 	return 0;
5386 	struct rtw89_btc *btc = &rtwdev->btc;
5387 	struct rtw89_btc_wl_info *wl = &btc->cx.wl;
5388 	struct rtw89_btc_wl_rfk_info *rfk_info = &wl->rfk_info;
5396 		return -ENOMEM;
5399 	cmd = skb->data;
5402 	RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_RFK - H2C_LEN_CXDRVHDR);
5404 	RTW89_SET_FWCMD_CXRFK_STATE(cmd, rfk_info->state);
5405 	RTW89_SET_FWCMD_CXRFK_PATH_MAP(cmd, rfk_info->path_map);
5406 	RTW89_SET_FWCMD_CXRFK_PHY_MAP(cmd, rfk_info->phy_map);
5407 	RTW89_SET_FWCMD_CXRFK_BAND(cmd, rfk_info->band);
5408 	RTW89_SET_FWCMD_CXRFK_TYPE(cmd, rfk_info->type);
5412 			      SET_DRV_INFO, 0, 0,
5421 	return 0;
5431 	struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
5440 		return -ENOMEM;
5443 	cmd = skb->data;
5456 	if (ret < 0) {
5463 	rtw89_core_release_bit_map(rtwdev->pkt_offload, id);
5464 	return 0;
5470 	struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
5477 	alloc_id = rtw89_core_acquire_bit_map(rtwdev->pkt_offload,
5480 		return -ENOSPC;
5484 	skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_LEN_PKT_OFLD + skb_ofld->len);
5487 		rtw89_core_release_bit_map(rtwdev->pkt_offload, alloc_id);
5488 		return -ENOMEM;
5491 	cmd = skb->data;
5495 	RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(cmd, skb_ofld->len);
5496 	skb_put_data(skb, skb_ofld->data, skb_ofld->len);
5501 			      H2C_LEN_PKT_OFLD + skb_ofld->len);
5506 	if (ret < 0) {
5510 		rtw89_core_release_bit_map(rtwdev->pkt_offload, alloc_id);
5514 	return 0;
5521 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
5522 	struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
5537 		return -ENOMEM;
5540 	h2c = (struct rtw89_h2c_chinfo *)skb->data;
5542 	h2c->ch_num = ch_num;
5543 	h2c->elem_size = sizeof(*elem) / 4; /* in unit of 4 bytes */
5548 		elem->w0 = le32_encode_bits(ch_info->period, RTW89_H2C_CHINFO_W0_PERIOD) |
5549 			   le32_encode_bits(ch_info->dwell_time, RTW89_H2C_CHINFO_W0_DWELL) |
5550 			   le32_encode_bits(ch_info->central_ch, RTW89_H2C_CHINFO_W0_CENTER_CH) |
5551 			   le32_encode_bits(ch_info->pri_ch, RTW89_H2C_CHINFO_W0_PRI_CH);
5553 		elem->w1 = le32_encode_bits(ch_info->bw, RTW89_H2C_CHINFO_W1_BW) |
5554 			   le32_encode_bits(ch_info->notify_action, RTW89_H2C_CHINFO_W1_ACTION) |
5555 			   le32_encode_bits(ch_info->num_pkt, RTW89_H2C_CHINFO_W1_NUM_PKT) |
5556 			   le32_encode_bits(ch_info->tx_pkt, RTW89_H2C_CHINFO_W1_TX) |
5557 			   le32_encode_bits(ch_info->pause_data, RTW89_H2C_CHINFO_W1_PAUSE_DATA) |
5558 			   le32_encode_bits(ch_info->ch_band, RTW89_H2C_CHINFO_W1_BAND) |
5559 			   le32_encode_bits(ch_info->probe_id, RTW89_H2C_CHINFO_W1_PKT_ID) |
5560 			   le32_encode_bits(ch_info->dfs_ch, RTW89_H2C_CHINFO_W1_DFS) |
5561 			   le32_encode_bits(ch_info->tx_null, RTW89_H2C_CHINFO_W1_TX_NULL) |
5562 			   le32_encode_bits(ch_info->rand_seq_num, RTW89_H2C_CHINFO_W1_RANDOM);
5564 		if (scan_info->extra_op.set)
5565 			elem->w1 |= le32_encode_bits(ch_info->macid_tx,
5568 		elem->w2 = le32_encode_bits(ch_info->pkt_id[0], RTW89_H2C_CHINFO_W2_PKT0) |
5569 			   le32_encode_bits(ch_info->pkt_id[1], RTW89_H2C_CHINFO_W2_PKT1) |
5570 			   le32_encode_bits(ch_info->pkt_id[2], RTW89_H2C_CHINFO_W2_PKT2) |
5571 			   le32_encode_bits(ch_info->pkt_id[3], RTW89_H2C_CHINFO_W2_PKT3);
5573 		elem->w3 = le32_encode_bits(ch_info->pkt_id[4], RTW89_H2C_CHINFO_W3_PKT4) |
5574 			   le32_encode_bits(ch_info->pkt_id[5], RTW89_H2C_CHINFO_W3_PKT5) |
5575 			   le32_encode_bits(ch_info->pkt_id[6], RTW89_H2C_CHINFO_W3_PKT6) |
5576 			   le32_encode_bits(ch_info->pkt_id[7], RTW89_H2C_CHINFO_W3_PKT7);
5591 	return 0;
5599 	struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
5615 		return -ENOMEM;
5618 	if (RTW89_CHK_FW_FEATURE(CH_INFO_BE_V0, &rtwdev->fw))
5619 		ver = 0;
5622 	h2c = (struct rtw89_h2c_chinfo_be *)skb->data;
5624 	h2c->ch_num = ch_num;
5625 	h2c->elem_size = sizeof(*elem) / 4; /* in unit of 4 bytes */
5626 	h2c->arg = u8_encode_bits(rtwvif_link->mac_idx,
5632 		elem->w0 = le32_encode_bits(ch_info->dwell_time, RTW89_H2C_CHINFO_BE_W0_DWELL) |
5633 			   le32_encode_bits(ch_info->central_ch,
5635 			   le32_encode_bits(ch_info->pri_ch, RTW89_H2C_CHINFO_BE_W0_PRI_CH);
5637 		elem->w1 = le32_encode_bits(ch_info->bw, RTW89_H2C_CHINFO_BE_W1_BW) |
5638 			   le32_encode_bits(ch_info->ch_band, RTW89_H2C_CHINFO_BE_W1_CH_BAND) |
5639 			   le32_encode_bits(ch_info->dfs_ch, RTW89_H2C_CHINFO_BE_W1_DFS) |
5640 			   le32_encode_bits(ch_info->pause_data,
5642 			   le32_encode_bits(ch_info->tx_null, RTW89_H2C_CHINFO_BE_W1_TX_NULL) |
5643 			   le32_encode_bits(ch_info->rand_seq_num,
5645 			   le32_encode_bits(ch_info->notify_action,
5647 			   le32_encode_bits(ch_info->probe_id != 0xff ? 1 : 0,
5649 			   le32_encode_bits(ch_info->leave_crit,
5651 			   le32_encode_bits(ch_info->chkpt_timer,
5654 		elem->w2 = le32_encode_bits(ch_info->leave_time,
5656 			   le32_encode_bits(ch_info->leave_th,
5658 			   le32_encode_bits(ch_info->tx_pkt_ctrl,
5661 		elem->w3 = le32_encode_bits(ch_info->pkt_id[0], RTW89_H2C_CHINFO_BE_W3_PKT0) |
5662 			   le32_encode_bits(ch_info->pkt_id[1], RTW89_H2C_CHINFO_BE_W3_PKT1) |
5663 			   le32_encode_bits(ch_info->pkt_id[2], RTW89_H2C_CHINFO_BE_W3_PKT2) |
5664 			   le32_encode_bits(ch_info->pkt_id[3], RTW89_H2C_CHINFO_BE_W3_PKT3);
5666 		elem->w4 = le32_encode_bits(ch_info->pkt_id[4], RTW89_H2C_CHINFO_BE_W4_PKT4) |
5667 			   le32_encode_bits(ch_info->pkt_id[5], RTW89_H2C_CHINFO_BE_W4_PKT5) |
5668 			   le32_encode_bits(ch_info->pkt_id[6], RTW89_H2C_CHINFO_BE_W4_PKT6) |
5669 			   le32_encode_bits(ch_info->pkt_id[7], RTW89_H2C_CHINFO_BE_W4_PKT7);
5671 		elem->w5 = le32_encode_bits(ch_info->sw_def, RTW89_H2C_CHINFO_BE_W5_SW_DEF) |
5672 			   le32_encode_bits(ch_info->fw_probe0_ssids,
5675 		elem->w6 = le32_encode_bits(ch_info->fw_probe0_shortssids,
5677 			   le32_encode_bits(ch_info->fw_probe0_bssids,
5679 		if (ver == 0)
5680 			elem->w0 |=
5681 			   le32_encode_bits(ch_info->period, RTW89_H2C_CHINFO_BE_W0_PERIOD);
5683 			elem->w7 = le32_encode_bits(ch_info->period,
5699 	return 0;
5707 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
5708 	struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
5709 	struct rtw89_chan *op = &rtwdev->scan_info.op_chan;
5715 	u64 tsf = 0;
5721 		return -ENOMEM;
5724 	h2c = (struct rtw89_h2c_scanofld *)skb->data;
5726 	if (option->delay) {
5733 			tsf += (u64)option->delay * 1000;
5737 	h2c->w0 = le32_encode_bits(rtwvif_link->mac_id, RTW89_H2C_SCANOFLD_W0_MACID) |
5738 		  le32_encode_bits(rtwvif_link->port, RTW89_H2C_SCANOFLD_W0_PORT_ID) |
5739 		  le32_encode_bits(rtwvif_link->mac_idx, RTW89_H2C_SCANOFLD_W0_BAND) |
5740 		  le32_encode_bits(option->enable, RTW89_H2C_SCANOFLD_W0_OPERATION);
5742 	h2c->w1 = le32_encode_bits(true, RTW89_H2C_SCANOFLD_W1_NOTIFY_END) |
5743 		  le32_encode_bits(option->target_ch_mode,
5746 		  le32_encode_bits(option->repeat, RTW89_H2C_SCANOFLD_W1_SCAN_TYPE);
5748 	h2c->w2 = le32_encode_bits(option->norm_pd, RTW89_H2C_SCANOFLD_W2_NORM_PD) |
5749 		  le32_encode_bits(option->slow_pd, RTW89_H2C_SCANOFLD_W2_SLOW_PD);
5751 	if (option->target_ch_mode) {
5752 		h2c->w1 |= le32_encode_bits(op->band_width,
5754 			   le32_encode_bits(op->primary_channel,
5756 			   le32_encode_bits(op->channel,
5758 		h2c->w0 |= le32_encode_bits(op->band_type,
5762 	h2c->tsf_high = le32_encode_bits(upper_32_bits(tsf),
5764 	h2c->tsf_low = le32_encode_bits(lower_32_bits(tsf),
5767 	if (scan_info->extra_op.set)
5768 		h2c->w6 = le32_encode_bits(scan_info->extra_op.macid,
5776 	if (option->enable)
5787 	return 0;
5797 	sband = rtwdev->hw->wiphy->bands[NL80211_BAND_6GHZ];
5799 		option->prohib_chan = U64_MAX;
5803 	for (i = 0; i < sband->n_channels; i++) {
5804 		chan = &sband->channels[i];
5805 		if (chan->flags & IEEE80211_CHAN_DISABLED) {
5806 			idx = (chan->hw_value - 1) / 4;
5807 			option->prohib_chan |= BIT(idx);
5817 	struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
5818 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
5819 	const struct rtw89_hw_scan_extra_op *ext = &scan_info->extra_op;
5820 	struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
5821 	struct cfg80211_scan_request *req = rtwvif->scan_req;
5824 	struct rtw89_chan *op = &scan_info->op_chan;
5830 	u8 macc_role_size = sizeof(*macc_role) * option->num_macc_role;
5831 	u8 opch_size = sizeof(*opch) * option->num_opch;
5850 	scan_op[0].macid = rtwvif_link->mac_id;
5851 	scan_op[0].port = rtwvif_link->port;
5852 	scan_op[0].chan = *op;
5853 	vif = rtwvif_to_vif(rtwvif_link->rtwvif);
5854 	if (vif->type == NL80211_IFTYPE_AP)
5855 		ap_idx = 0;
5857 	if (ext->set) {
5859 		vif = rtwvif_to_vif(ext->rtwvif_link->rtwvif);
5860 		if (vif->type == NL80211_IFTYPE_AP)
5866 	if (RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD_BE_V0, &rtwdev->fw)) {
5868 		scan_offload_ver = 0;
5875 		return -ENOMEM;
5879 	h2c = (struct rtw89_h2c_scanofld_be *)skb->data;
5880 	ptr = skb->data;
5884 	if (RTW89_CHK_FW_FEATURE(CH_INFO_BE_V0, &rtwdev->fw))
5885 		ver = 0;
5888 		list_for_each_entry(pkt_info, &scan_info->pkt_list[NL80211_BAND_6GHZ], list) {
5889 			if (pkt_info->wildcard_6ghz) {
5891 				probe_id[NL80211_BAND_6GHZ] = pkt_info->id;
5897 	h2c->w0 = le32_encode_bits(option->operation, RTW89_H2C_SCANOFLD_BE_W0_OP) |
5898 		  le32_encode_bits(option->scan_mode,
5900 		  le32_encode_bits(option->repeat, RTW89_H2C_SCANOFLD_BE_W0_REPEAT) |
5903 		  le32_encode_bits(rtwvif_link->mac_id, RTW89_H2C_SCANOFLD_BE_W0_MACID) |
5904 		  le32_encode_bits(rtwvif_link->port, RTW89_H2C_SCANOFLD_BE_W0_PORT) |
5905 		  le32_encode_bits(option->band, RTW89_H2C_SCANOFLD_BE_W0_BAND);
5907 	h2c->w1 = le32_encode_bits(option->num_macc_role, RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE) |
5908 		  le32_encode_bits(option->num_opch, RTW89_H2C_SCANOFLD_BE_W1_NUM_OP) |
5909 		  le32_encode_bits(option->norm_pd, RTW89_H2C_SCANOFLD_BE_W1_NORM_PD);
5911 	h2c->w2 = le32_encode_bits(option->slow_pd, RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD) |
5912 		  le32_encode_bits(option->norm_cy, RTW89_H2C_SCANOFLD_BE_W2_NORM_CY) |
5913 		  le32_encode_bits(option->opch_end, RTW89_H2C_SCANOFLD_BE_W2_OPCH_END);
5915 	h2c->w3 = le32_encode_bits(0, RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID) |
5916 		  le32_encode_bits(0, RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID) |
5917 		  le32_encode_bits(0, RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID) |
5920 	h2c->w4 = le32_encode_bits(probe_id[NL80211_BAND_5GHZ],
5924 		  le32_encode_bits(option->delay / 1000, RTW89_H2C_SCANOFLD_BE_W4_DELAY_START);
5926 	h2c->w5 = le32_encode_bits(option->mlo_mode, RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE);
5928 	h2c->w6 = le32_encode_bits(option->prohib_chan,
5930 	h2c->w7 = le32_encode_bits(option->prohib_chan >> 32,
5932 	if (!wowlan && req->no_cck) {
5933 		h2c->w0 |= le32_encode_bits(true, RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE);
5934 		h2c->w8 = le32_encode_bits(RTW89_HW_RATE_OFDM6,
5942 	if (scan_offload_ver == 0)
5945 	h2c->w9 = le32_encode_bits(sizeof(*h2c) / sizeof(h2c->w0),
5947 		  le32_encode_bits(sizeof(*macc_role) / sizeof(macc_role->w0),
5949 		  le32_encode_bits(sizeof(*opch) / sizeof(opch->w0),
5955 	for (i = 0; i < option->num_macc_role; i++) {
5961 		macc_role->w0 =
5962 			le32_encode_bits(0, RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND) |
5963 			le32_encode_bits(0, RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT) |
5964 			le32_encode_bits(0, RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID) |
5965 			le32_encode_bits(0, RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END);
5969 	for (i = 0; i < option->num_opch; i++) {
5974 		txbcn = is_ap_idx ? 1 : 0;
5981 		opch->w0 = le32_encode_bits(scan_op[i].macid,
5983 			   le32_encode_bits(option->band,
5994 		opch->w1 = le32_encode_bits(scan_op[i].chan.band_type,
5998 			   le32_encode_bits(0x3,
6005 		opch->w2 = le32_encode_bits(0,
6007 			   le32_encode_bits(0,
6014 		opch->w3 = le32_encode_bits(RTW89_SCANOFLD_PKT_NONE,
6023 		if (ver == 0)
6024 			opch->w1 |= le32_encode_bits(RTW89_CHANNEL_TIME,
6027 			opch->w4 = le32_encode_bits(RTW89_CHANNEL_TIME,
6037 	if (option->enable)
6048 	return 0;
6056 	u8 class = info->rf_path == RF_PATH_A ?
6063 		return -ENOMEM;
6065 	skb_put_data(skb, info->rtw89_phy_config_rf_h2c[page], len);
6068 			      H2C_CAT_OUTSRC, class, page, 0, 0,
6077 	return 0;
6086 	struct rtw89_rfk_mcc_info_data *rfk_mcc = rtwdev->rfk_mcc.data;
6095 	if (RTW89_CHK_FW_FEATURE(RFK_NTFY_MCC_V0, &rtwdev->fw)) {
6097 		ver = 0;
6103 		return -ENOMEM;
6107 	idx = rfk_mcc->table_idx;
6108 	if (ver == 0) {
6109 		mccch_v0 = (struct rtw89_fw_h2c_rf_get_mccch_v0 *)skb->data;
6110 		mccch_v0->ch_0 = cpu_to_le32(rfk_mcc->ch[0]);
6111 		mccch_v0->ch_1 = cpu_to_le32(rfk_mcc->ch[1]);
6112 		mccch_v0->band_0 = cpu_to_le32(rfk_mcc->band[0]);
6113 		mccch_v0->band_1 = cpu_to_le32(rfk_mcc->band[1]);
6114 		mccch_v0->current_band_type = cpu_to_le32(rfk_mcc->band[idx]);
6115 		mccch_v0->current_channel = cpu_to_le32(rfk_mcc->ch[idx]);
6117 		mccch = (struct rtw89_fw_h2c_rf_get_mccch *)skb->data;
6118 		mccch->ch_0_0 = cpu_to_le32(rfk_mcc->ch[0]);
6119 		mccch->ch_0_1 = cpu_to_le32(rfk_mcc->ch[0]);
6120 		mccch->ch_1_0 = cpu_to_le32(rfk_mcc->ch[1]);
6121 		mccch->ch_1_1 = cpu_to_le32(rfk_mcc->ch[1]);
6122 		mccch->current_channel = cpu_to_le32(rfk_mcc->ch[idx]);
6127 			      H2C_FUNC_OUTSRC_RF_GET_MCCCH, 0, 0,
6136 	return 0;
6146 			 u8 mcc_role_idx, u8 pd_val, bool en)  argument
6149 	const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6158 		return -ENOMEM;
6161 	h2c = (struct rtw89_h2c_mcc_dig *)skb->data;
6163 	h2c->w0 = le32_encode_bits(1, RTW89_H2C_MCC_DIG_W0_REG_CNT) |
6164 		  le32_encode_bits(en, RTW89_H2C_MCC_DIG_W0_DM_EN) |
6168 		  le32_encode_bits(chan->channel, RTW89_H2C_MCC_DIG_W0_CENTER_CH) |
6169 		  le32_encode_bits(chan->band_type, RTW89_H2C_MCC_DIG_W0_BAND_TYPE);
6170 	h2c->w1 = le32_encode_bits(dig_regs->seg0_pd_reg,
6172 		  le32_encode_bits(dig_regs->seg0_pd_reg >> 8,
6174 		  le32_encode_bits(dig_regs->pd_lower_bound_mask,
6176 		  le32_encode_bits(dig_regs->pd_lower_bound_mask >> 8,
6178 	h2c->w2 = le32_encode_bits(pd_val, RTW89_H2C_MCC_DIG_W2_VAL_LSB);
6182 			      H2C_FUNC_FW_MCC_DIG, 0, 0, len);
6190 	return 0;
6199 	const struct rtw89_chip_info *chip = rtwdev->chip;
6210 	if (chip->chip_gen != RTW89_CHIP_BE)
6211 		return 0;
6216 		return -ENOMEM;
6219 	h2c = (struct rtw89_h2c_rf_ps_info *)skb->data;
6220 	h2c->mlo_mode = cpu_to_le32(rtwdev->mlo_dbcc_mode);
6223 		chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
6224 		path = rtw89_phy_get_syn_sel(rtwdev, rtwvif_link->phy_idx);
6227 		if (path >= chip->rf_path_num || path >= NUM_OF_RTW89_FW_RFK_PATH) {
6229 			ret = -ENOENT;
6233 		h2c->rf18[path] = cpu_to_le32(val);
6234 		h2c->pri_ch[path] = chan->primary_channel;
6239 			      H2C_FUNC_OUTSRC_RF_PS_INFO, 0, 0,
6248 	return 0;
6259 	struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
6272 	if (RTW89_CHK_FW_FEATURE(RFK_PRE_NOTIFY_V1, &rtwdev->fw)) {
6275 	} else if (RTW89_CHK_FW_FEATURE(RFK_PRE_NOTIFY_V0, &rtwdev->fw)) {
6277 		ver = 0;
6283 		return -ENOMEM;
6286 	h2c = (struct rtw89_fw_h2c_rfk_pre_info *)skb->data;
6287 	common = &h2c->base_v1.common;
6289 	common->mlo_mode = cpu_to_le32(rtwdev->mlo_dbcc_mode);
6292 	BUILD_BUG_ON(ARRAY_SIZE(rfk_mcc->data) < NUM_OF_RTW89_FW_RFK_PATH);
6294 	for (tbl = 0; tbl < NUM_OF_RTW89_FW_RFK_TBL; tbl++) {
6295 		for (path = 0; path < NUM_OF_RTW89_FW_RFK_PATH; path++) {
6296 			common->dbcc.ch[path][tbl] =
6297 				cpu_to_le32(rfk_mcc->data[path].ch[tbl]);
6298 			common->dbcc.band[path][tbl] =
6299 				cpu_to_le32(rfk_mcc->data[path].band[tbl]);
6303 	for (path = 0; path < NUM_OF_RTW89_FW_RFK_PATH; path++) {
6304 		tbl_sel[path] = rfk_mcc->data[path].table_idx;
6306 		common->tbl.cur_ch[path] =
6307 			cpu_to_le32(rfk_mcc->data[path].ch[tbl_sel[path]]);
6308 		common->tbl.cur_band[path] =
6309 			cpu_to_le32(rfk_mcc->data[path].band[tbl_sel[path]]);
6314 		h2c->cur_bandwidth[path] =
6315 			cpu_to_le32(rfk_mcc->data[path].bw[tbl_sel[path]]);
6318 	common->phy_idx = cpu_to_le32(phy_idx);
6320 	if (ver == 0) { /* RFK_PRE_NOTIFY_V0 */
6321 		h2c_v0 = (struct rtw89_fw_h2c_rfk_pre_info_v0 *)skb->data;
6323 		h2c_v0->cur_band = cpu_to_le32(rfk_mcc->data[0].band[tbl_sel[0]]);
6324 		h2c_v0->cur_bw = cpu_to_le32(rfk_mcc->data[0].bw[tbl_sel[0]]);
6325 		h2c_v0->cur_center_ch = cpu_to_le32(rfk_mcc->data[0].ch[tbl_sel[0]]);
6328 		h2c_v0->ktbl_sel0 = cpu_to_le32(val32);
6330 		h2c_v0->ktbl_sel1 = cpu_to_le32(val32);
6332 		h2c_v0->rfmod0 = cpu_to_le32(val32);
6334 		h2c_v0->rfmod1 = cpu_to_le32(val32);
6337 			h2c_v0->mlo_1_1 = cpu_to_le32(1);
6339 		h2c_v0->rfe_type = cpu_to_le32(rtwdev->efuse.rfe_type);
6345 		h2c_v1 = &h2c->base_v1;
6346 		h2c_v1->mlo_1_1 = cpu_to_le32(1);
6351 			      H2C_FUNC_RFK_PRE_NOTIFY, 0, 0,
6360 	return 0;
6370 	struct rtw89_efuse *efuse = &rtwdev->efuse;
6371 	struct rtw89_hal *hal = &rtwdev->hal;
6380 		return -ENOMEM;
6383 	h2c = (struct rtw89_h2c_rf_tssi *)skb->data;
6385 	h2c->len = cpu_to_le16(len);
6386 	h2c->phy = phy_idx;
6387 	h2c->ch = chan->channel;
6388 	h2c->bw = chan->band_width;
6389 	h2c->band = chan->band_type;
6390 	h2c->hwtx_en = true;
6391 	h2c->cv = hal->cv;
6392 	h2c->tssi_mode = tssi_mode;
6393 	h2c->rfe_type = efuse->rfe_type;
6400 			      H2C_FUNC_RFK_TSSI_OFFLOAD, 0, 0, len);
6408 	return 0;
6418 	struct rtw89_hal *hal = &rtwdev->hal;
6426 	if (RTW89_CHK_FW_FEATURE(RFK_IQK_V0, &rtwdev->fw)) {
6428 		ver = 0;
6434 		return -ENOMEM;
6438 	if (ver == 0) {
6439 		h2c_v0 = (struct rtw89_h2c_rf_iqk_v0 *)skb->data;
6441 		h2c_v0->phy_idx = cpu_to_le32(phy_idx);
6442 		h2c_v0->dbcc = cpu_to_le32(rtwdev->dbcc_en);
6447 	h2c = (struct rtw89_h2c_rf_iqk *)skb->data;
6449 	h2c->len = sizeof(*h2c);
6450 	h2c->ktype = 0;
6451 	h2c->phy = phy_idx;
6452 	h2c->kpath = rtw89_phy_get_kpath(rtwdev, phy_idx);
6453 	h2c->band = chan->band_type;
6454 	h2c->bw = chan->band_width;
6455 	h2c->ch = chan->channel;
6456 	h2c->cv = hal->cv;
6461 			      H2C_FUNC_RFK_IQK_OFFLOAD, 0, 0, len);
6469 	return 0;
6487 		return -ENOMEM;
6490 	h2c = (struct rtw89_h2c_rf_dpk *)skb->data;
6492 	h2c->len = len;
6493 	h2c->phy = phy_idx;
6494 	h2c->dpk_enable = true;
6495 	h2c->kpath = RF_AB;
6496 	h2c->cur_band = chan->band_type;
6497 	h2c->cur_bw = chan->band_width;
6498 	h2c->cur_ch = chan->channel;
6499 	h2c->dpk_dbg_en = rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK);
6503 			      H2C_FUNC_RFK_DPK_OFFLOAD, 0, 0, len);
6511 	return 0;
6521 	struct rtw89_hal *hal = &rtwdev->hal;
6530 		return -ENOMEM;
6533 	h2c = (struct rtw89_h2c_rf_txgapk *)skb->data;
6535 	h2c->len = len;
6536 	h2c->ktype = 2;
6537 	h2c->phy = phy_idx;
6538 	h2c->kpath = RF_AB;
6539 	h2c->band = chan->band_type;
6540 	h2c->bw = chan->band_width;
6541 	h2c->ch = chan->channel;
6542 	h2c->cv = hal->cv;
6546 			      H2C_FUNC_RFK_TXGAPK_OFFLOAD, 0, 0, len);
6554 	return 0;
6572 		return -ENOMEM;
6575 	h2c = (struct rtw89_h2c_rf_dack *)skb->data;
6577 	h2c->len = cpu_to_le32(len);
6578 	h2c->phy = cpu_to_le32(phy_idx);
6579 	h2c->type = cpu_to_le32(0);
6583 			      H2C_FUNC_RFK_DACK_OFFLOAD, 0, 0, len);
6591 	return 0;
6605 	int ver = -1;
6608 	if (RTW89_CHK_FW_FEATURE(RFK_RXDCK_V0, &rtwdev->fw)) {
6610 		ver = 0;
6616 		return -ENOMEM;
6619 	v0 = (struct rtw89_h2c_rf_rxdck_v0 *)skb->data;
6621 	v0->len = len;
6622 	v0->phy = phy_idx;
6623 	v0->is_afe = false;
6624 	v0->kpath = RF_AB;
6625 	v0->cur_band = chan->band_type;
6626 	v0->cur_bw = chan->band_width;
6627 	v0->cur_ch = chan->channel;
6628 	v0->rxdck_dbg_en = rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK);
6630 	if (ver == 0)
6633 	h2c = (struct rtw89_h2c_rf_rxdck *)skb->data;
6634 	h2c->is_chl_k = is_chl_k;
6639 			      H2C_FUNC_RFK_RXDCK_OFFLOAD, 0, 0, len);
6647 	return 0;
6664 		return -ENOMEM;
6678 	return 0;
6693 		return -ENOMEM;
6703 	return 0;
6714 	lockdep_assert_wiphy(rtwdev->hw->wiphy);
6716 	list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) {
6717 		rtw89_fw_h2c_raw(rtwdev, early_h2c->h2c, early_h2c->h2c_len);
6725 	list_for_each_entry_safe(early_h2c, tmp, &rtwdev->early_h2c_list, list) {
6726 		list_del(&early_h2c->list);
6727 		kfree(early_h2c->h2c);
6734 	lockdep_assert_wiphy(rtwdev->hw->wiphy);
6741 	const struct rtw89_c2h_hdr *hdr = (const struct rtw89_c2h_hdr *)c2h->data;
6744 	attr->category = le32_get_bits(hdr->w0, RTW89_C2H_HDR_W0_CATEGORY);
6745 	attr->class = le32_get_bits(hdr->w0, RTW89_C2H_HDR_W0_CLASS);
6746 	attr->func = le32_get_bits(hdr->w0, RTW89_C2H_HDR_W0_FUNC);
6747 	attr->len = le32_get_bits(hdr->w1, RTW89_C2H_HDR_W1_LEN);
6754 	u8 category = attr->category;
6755 	u8 class = attr->class;
6756 	u8 func = attr->func;
6779 	skb_queue_tail(&rtwdev->c2h_queue, c2h);
6780 	wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->c2h_work);
6787 	u8 category = attr->category;
6788 	u8 class = attr->class;
6789 	u8 func = attr->func;
6790 	u16 len = attr->len;
6793 	if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
6815 		rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "C2H: ", skb->data, skb->len);
6824 	lockdep_assert_wiphy(rtwdev->hw->wiphy);
6826 	skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
6827 		skb_unlink(skb, &rtwdev->c2h_queue);
6835 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
6839 	lockdep_assert_wiphy(rtwdev->hw->wiphy);
6841 	limit = skb_queue_len(&rtwdev->c2h_queue);
6843 	skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
6846 		if (--limit < 0)
6849 		if (!attr->is_scan_event || attr->scan_seq == scan_info->seq)
6854 			    attr->scan_seq, scan_info->seq);
6856 		skb_unlink(skb, &rtwdev->c2h_queue);
6864 	const struct rtw89_chip_info *chip = rtwdev->chip;
6865 	struct rtw89_fw_info *fw_info = &rtwdev->fw;
6866 	const u32 *h2c_reg = chip->h2c_regs;
6870 	ret = read_poll_timeout(rtw89_read8, val, val == 0, 1000, 5000, false,
6871 				rtwdev, chip->h2c_ctrl_reg);
6877 	len = DIV_ROUND_UP(info->content_len + RTW89_H2CREG_HDR_LEN,
6878 			   sizeof(info->u.h2creg[0]));
6880 	u32p_replace_bits(&info->u.hdr.w0, info->id, RTW89_H2CREG_HDR_FUNC_MASK);
6881 	u32p_replace_bits(&info->u.hdr.w0, len, RTW89_H2CREG_HDR_LEN_MASK);
6883 	for (i = 0; i < RTW89_H2CREG_MAX; i++)
6884 		rtw89_write32(rtwdev, h2c_reg[i], info->u.h2creg[i]);
6886 	fw_info->h2c_counter++;
6887 	rtw89_write8_mask(rtwdev, chip->h2c_counter_reg.addr,
6888 			  chip->h2c_counter_reg.mask, fw_info->h2c_counter);
6889 	rtw89_write8(rtwdev, chip->h2c_ctrl_reg, B_AX_H2CREG_TRIGGER);
6891 	return 0;
6897 	const struct rtw89_chip_info *chip = rtwdev->chip;
6898 	struct rtw89_fw_info *fw_info = &rtwdev->fw;
6899 	const u32 *c2h_reg = chip->c2h_regs;
6903 	info->id = RTW89_FWCMD_C2HREG_FUNC_NULL;
6905 	if (rtwdev->hci.type == RTW89_HCI_TYPE_USB)
6912 				       chip->c2h_ctrl_reg);
6918 	for (i = 0; i < RTW89_C2HREG_MAX; i++)
6919 		info->u.c2hreg[i] = rtw89_read32(rtwdev, c2h_reg[i]);
6921 	rtw89_write8(rtwdev, chip->c2h_ctrl_reg, 0);
6923 	info->id = u32_get_bits(info->u.hdr.w0, RTW89_C2HREG_HDR_FUNC_MASK);
6924 	info->content_len =
6925 		(u32_get_bits(info->u.hdr.w0, RTW89_C2HREG_HDR_LEN_MASK) << 2) -
6928 	fw_info->c2h_counter++;
6929 	rtw89_write8_mask(rtwdev, chip->c2h_counter_reg.addr,
6930 			  chip->c2h_counter_reg.mask, fw_info->c2h_counter);
6932 	return 0;
6941 	if (h2c_info && h2c_info->id != RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE)
6942 		lockdep_assert_wiphy(rtwdev->hw->wiphy);
6945 		return -EINVAL;
6956 		return 0;
6962 	return 0;
6967 	if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) {
6972 	rtw89_info(rtwdev, "FW status = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM0));
6973 	rtw89_info(rtwdev, "FW BADADDR = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM1));
6974 	rtw89_info(rtwdev, "FW EPC/RA = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM2));
6975 	rtw89_info(rtwdev, "FW MISC = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM3));
6976 	rtw89_info(rtwdev, "R_AX_HALT_C2H = 0x%x\n",
6978 	rtw89_info(rtwdev, "R_AX_SER_DBG_INFO = 0x%x\n",
6986 	struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
6991 		if (!(rtwdev->chip->support_bands & BIT(idx)))
6995 			if (test_bit(info->id, rtwdev->pkt_offload))
6996 				rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
6997 			list_del(&info->list);
7006 	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
7007 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
7008 	struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
7010 	mac->free_chan_list(rtwdev);
7013 	rtwvif->scan_req = NULL;
7014 	rtwvif->scan_ies = NULL;
7015 	scan_info->scanning_vif = NULL;
7016 	scan_info->abort = false;
7017 	scan_info->connected = false;
7018 	scan_info->delay = 0;
7029 	if (req->ssids[ssid_idx].ssid_len) {
7030 		memcpy(info->ssid, req->ssids[ssid_idx].ssid,
7031 		       req->ssids[ssid_idx].ssid_len);
7032 		info->ssid_len = req->ssids[ssid_idx].ssid_len;
7035 		info->wildcard_6ghz = true;
7044 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
7045 	struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
7046 	struct ieee80211_scan_ies *ies = rtwvif->scan_ies;
7047 	struct cfg80211_scan_request *req = rtwvif->scan_req;
7050 	int ret = 0;
7054 		if (!(rtwdev->chip->support_bands & BIT(band)))
7059 			ret = -ENOMEM;
7062 		skb_put_data(new, ies->ies[band], ies->len[band]);
7063 		skb_put_data(new, ies->common_ies, ies->common_ie_len);
7067 			ret = -ENOMEM;
7074 		ret = rtw89_fw_h2c_add_pkt_offload(rtwdev, &info->id, new);
7081 		list_add_tail(&info->list, &scan_info->pkt_list[band]);
7092 	struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
7093 	struct cfg80211_scan_request *req = rtwvif->scan_req;
7095 	u8 num = req->n_ssids, i;
7098 	for (i = 0; i < num; i++) {
7099 		skb = ieee80211_probereq_get(rtwdev->hw, mac_addr,
7100 					     req->ssids[i].ssid,
7101 					     req->ssids[i].ssid_len,
7102 					     req->ie_len);
7104 			return -ENOMEM;
7113 	return 0;
7121 	struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif;
7122 	struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
7128 	int ret = 0;
7131 	if (!req->n_6ghz_params)
7132 		return 0;
7134 	for (i = 0; i < req->n_6ghz_params; i++) {
7135 		params = &req->scan_6ghz_params[i];
7137 		if (req->channels[params->channel_idx]->hw_value !=
7138 		    ch_info->pri_ch)
7143 			if (ether_addr_equal(tmp->bssid, params->bssid)) {
7151 		skb = ieee80211_probereq_get(rtwdev->hw, rtwvif_link->mac_addr,
7152 					     NULL, 0, req->ie_len);
7154 			return -ENOMEM;
7156 		skb_put_data(skb, ies->ies[NL80211_BAND_6GHZ], ies->len[NL80211_BAND_6GHZ]);
7157 		skb_put_data(skb, ies->common_ies, ies->common_ie_len);
7158 		hdr = (struct ieee80211_hdr *)skb->data;
7159 		ether_addr_copy(hdr->addr3, params->bssid);
7163 			ret = -ENOMEM;
7168 		ret = rtw89_fw_h2c_add_pkt_offload(rtwdev, &info->id, skb);
7175 		ether_addr_copy(info->bssid, params->bssid);
7176 		info->channel_6ghz = req->channels[params->channel_idx]->hw_value;
7177 		list_add_tail(&info->list, &rtwdev->scan_info.pkt_list[NL80211_BAND_6GHZ]);
7179 		ch_info->tx_pkt = true;
7180 		ch_info->period = RTW89_CHANNEL_TIME_6G + RTW89_DWELL_TIME_6G;
7193 	struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
7195 	u8 probe_count = 0;
7197 	ch_info->notify_action = RTW89_SCANOFLD_DEBUG_MASK;
7198 	ch_info->dfs_ch = chan_type == RTW89_CHAN_DFS;
7199 	ch_info->bw = RTW89_SCAN_WIDTH;
7200 	ch_info->tx_pkt = true;
7201 	ch_info->cfg_tx_pwr = false;
7202 	ch_info->tx_pwr_idx = 0;
7203 	ch_info->tx_null = false;
7204 	ch_info->pause_data = false;
7205 	ch_info->probe_id = RTW89_SCANOFLD_PKT_NONE;
7208 		list_for_each_entry(info, &rtw_wow->pno_pkt_list, list) {
7209 			if (info->channel_6ghz &&
7210 			    ch_info->pri_ch != info->channel_6ghz)
7212 			else if (info->channel_6ghz && probe_count != 0)
7213 				ch_info->period += RTW89_CHANNEL_TIME_6G;
7215 			if (info->wildcard_6ghz)
7218 			ch_info->pkt_id[probe_count++] = info->id;
7222 		ch_info->num_pkt = probe_count;
7227 		if (ch_info->ch_band != RTW89_BAND_6G)
7228 			ch_info->period = max_t(u8, ch_info->period,
7230 		ch_info->dwell_time = RTW89_DWELL_TIME;
7243 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
7244 	struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif;
7245 	const struct rtw89_hw_scan_extra_op *ext = &scan_info->extra_op;
7246 	struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
7247 	struct ieee80211_scan_ies *ies = rtwvif->scan_ies;
7248 	struct cfg80211_scan_request *req = rtwvif->scan_req;
7249 	struct rtw89_chan *op = &rtwdev->scan_info.op_chan;
7251 	u8 band, probe_count = 0;
7254 	ch_info->notify_action = RTW89_SCANOFLD_DEBUG_MASK;
7255 	ch_info->dfs_ch = chan_type == RTW89_CHAN_DFS;
7256 	ch_info->bw = RTW89_SCAN_WIDTH;
7257 	ch_info->tx_pkt = true;
7258 	ch_info->cfg_tx_pwr = false;
7259 	ch_info->tx_pwr_idx = 0;
7260 	ch_info->tx_null = false;
7261 	ch_info->pause_data = false;
7262 	ch_info->probe_id = RTW89_SCANOFLD_PKT_NONE;
7264 	if (ch_info->ch_band == RTW89_BAND_6G) {
7265 		if ((ssid_num == 1 && req->ssids[0].ssid_len == 0) ||
7266 		    !ch_info->is_psc) {
7267 			ch_info->tx_pkt = false;
7268 			if (!req->duration_mandatory)
7269 				ch_info->period -= RTW89_DWELL_TIME_6G;
7278 		band = rtw89_hw_to_nl80211_band(ch_info->ch_band);
7280 		list_for_each_entry(info, &scan_info->pkt_list[band], list) {
7281 			if (info->channel_6ghz &&
7282 			    ch_info->pri_ch != info->channel_6ghz)
7284 			else if (info->channel_6ghz && probe_count != 0)
7285 				ch_info->period += RTW89_CHANNEL_TIME_6G;
7287 			if (info->wildcard_6ghz)
7290 			ch_info->pkt_id[probe_count++] = info->id;
7294 		ch_info->num_pkt = probe_count;
7299 		ch_info->central_ch = op->channel;
7300 		ch_info->pri_ch = op->primary_channel;
7301 		ch_info->ch_band = op->band_type;
7302 		ch_info->bw = op->band_width;
7303 		ch_info->tx_null = true;
7304 		ch_info->num_pkt = 0;
7307 		if (ch_info->ch_band != RTW89_BAND_6G)
7308 			ch_info->period = max_t(u8, ch_info->period,
7310 		ch_info->dwell_time = RTW89_DWELL_TIME;
7311 		ch_info->pause_data = true;
7314 		ch_info->pause_data = true;
7317 		ch_info->central_ch = ext->chan.channel;
7318 		ch_info->pri_ch = ext->chan.primary_channel;
7319 		ch_info->ch_band = ext->chan.band_type;
7320 		ch_info->bw = ext->chan.band_width;
7321 		ch_info->tx_null = true;
7322 		ch_info->num_pkt = 0;
7323 		ch_info->macid_tx = true;
7334 	struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
7336 	u8 probe_count = 0, i;
7338 	ch_info->notify_action = RTW89_SCANOFLD_DEBUG_MASK;
7339 	ch_info->dfs_ch = chan_type == RTW89_CHAN_DFS;
7340 	ch_info->bw = RTW89_SCAN_WIDTH;
7341 	ch_info->tx_null = false;
7342 	ch_info->pause_data = false;
7343 	ch_info->probe_id = RTW89_SCANOFLD_PKT_NONE;
7346 		list_for_each_entry(info, &rtw_wow->pno_pkt_list, list) {
7347 			ch_info->pkt_id[probe_count++] = info->id;
7354 		ch_info->pkt_id[i] = RTW89_SCANOFLD_PKT_NONE;
7358 		ch_info->period = max_t(u8, ch_info->period, RTW89_DFS_CHAN_TIME);
7359 		ch_info->dwell_time = RTW89_DWELL_TIME;
7373 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
7374 	struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif;
7375 	struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
7376 	struct cfg80211_scan_request *req = rtwvif->scan_req;
7378 	u8 band, probe_count = 0, i;
7380 	ch_info->notify_action = RTW89_SCANOFLD_DEBUG_MASK;
7381 	ch_info->dfs_ch = chan_type == RTW89_CHAN_DFS;
7382 	ch_info->bw = RTW89_SCAN_WIDTH;
7383 	ch_info->tx_null = false;
7384 	ch_info->pause_data = false;
7385 	ch_info->probe_id = RTW89_SCANOFLD_PKT_NONE;
7388 		band = rtw89_hw_to_nl80211_band(ch_info->ch_band);
7390 		list_for_each_entry(info, &scan_info->pkt_list[band], list) {
7391 			if (info->channel_6ghz &&
7392 			    ch_info->pri_ch != info->channel_6ghz)
7395 			if (info->wildcard_6ghz)
7398 			ch_info->pkt_id[probe_count++] = info->id;
7404 	if (ch_info->ch_band == RTW89_BAND_6G) {
7405 		if ((ssid_num == 1 && req->ssids[0].ssid_len == 0) ||
7406 		    !ch_info->is_psc) {
7407 			ch_info->probe_id = RTW89_SCANOFLD_PKT_NONE;
7408 			if (!req->duration_mandatory)
7409 				ch_info->period -= RTW89_DWELL_TIME_6G;
7414 		ch_info->pkt_id[i] = RTW89_SCANOFLD_PKT_NONE;
7418 		if (ch_info->ch_band != RTW89_BAND_6G)
7419 			ch_info->period =
7420 				max_t(u8, ch_info->period, RTW89_DFS_CHAN_TIME);
7421 		ch_info->dwell_time = RTW89_DWELL_TIME;
7422 		ch_info->pause_data = true;
7425 		ch_info->pause_data = true;
7436 	struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
7437 	struct cfg80211_sched_scan_request *nd_config = rtw_wow->nd_config;
7443 	int ret = 0;
7447 	for (idx = 0, list_len = 0;
7448 	     idx < nd_config->n_channels && list_len < RTW89_SCAN_LIST_LIMIT_AX;
7450 		channel = nd_config->channels[idx];
7453 			ret = -ENOMEM;
7457 		ch_info->period = RTW89_CHANNEL_TIME;
7458 		ch_info->ch_band = rtw89_nl80211_to_hw_band(channel->band);
7459 		ch_info->central_ch = channel->hw_value;
7460 		ch_info->pri_ch = channel->hw_value;
7461 		ch_info->is_psc = cfg80211_channel_is_psc(channel);
7463 		if (channel->flags &
7469 		rtw89_pno_scan_add_chan_ax(rtwdev, type, nd_config->n_match_sets, ch_info);
7470 		list_add_tail(&ch_info->list, &chan_list);
7476 		list_del(&ch_info->list);
7493 		return -ENOMEM;
7497 		tmp->period = req->duration_mandatory ?
7498 			      req->duration : RTW89_CHANNEL_TIME;
7499 		*off_chan_time = 0;
7502 		tmp->period = RTW89_CHANNEL_TIME_EXTRA_OP;
7504 		*off_chan_time += tmp->period;
7508 		return -EINVAL;
7511 	rtw89_hw_scan_add_chan_ax(rtwdev, type, 0, tmp);
7512 	list_add_tail(&tmp->list, chan_list);
7514 	return 0;
7520 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
7521 	const struct rtw89_hw_scan_extra_op *ext = &scan_info->extra_op;
7522 	struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
7523 	struct cfg80211_scan_request *req = rtwvif->scan_req;
7527 	bool random_seq = req->flags & NL80211_SCAN_FLAG_RANDOM_SN;
7529 	int off_chan_time = 0;
7535 	for (idx = 0; idx < req->n_channels; idx++) {
7536 		channel = req->channels[idx];
7539 			ret = -ENOMEM;
7543 		if (req->duration)
7544 			ch_info->period = req->duration;
7545 		else if (channel->band == NL80211_BAND_6GHZ)
7546 			ch_info->period = RTW89_CHANNEL_TIME_6G +
7548 		else if (rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT)
7549 			ch_info->period = RTW89_P2P_CHAN_TIME;
7551 			ch_info->period = RTW89_CHANNEL_TIME;
7553 		ch_info->ch_band = rtw89_nl80211_to_hw_band(channel->band);
7554 		ch_info->central_ch = channel->hw_value;
7555 		ch_info->pri_ch = channel->hw_value;
7556 		ch_info->rand_seq_num = random_seq;
7557 		ch_info->is_psc = cfg80211_channel_is_psc(channel);
7559 		if (channel->flags &
7564 		rtw89_hw_scan_add_chan_ax(rtwdev, type, req->n_ssids, ch_info);
7566 		if (!(scan_info->connected &&
7567 		      off_chan_time + ch_info->period > RTW89_OFF_CHAN_TIME))
7577 		if (!ext->set)
7588 		list_add_tail(&ch_info->list, &chan_list);
7589 		off_chan_time += ch_info->period;
7592 	list_splice_tail(&chan_list, &scan_info->chan_list);
7593 	return 0;
7597 		list_del(&ch_info->list);
7606 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
7609 	list_for_each_entry_safe(ch_info, tmp, &scan_info->chan_list, list) {
7610 		list_del(&ch_info->list);
7618 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
7620 	unsigned int list_len = 0;
7626 	list_for_each_entry_safe(ch_info, tmp, &scan_info->chan_list, list) {
7627 		list_move_tail(&ch_info->list, &list);
7637 		list_del(&ch_info->list);
7647 	struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
7648 	struct cfg80211_sched_scan_request *nd_config = rtw_wow->nd_config;
7658 	for (idx = 0, list_len = 0;
7659 	     idx < nd_config->n_channels && list_len < RTW89_SCAN_LIST_LIMIT_BE;
7661 		channel = nd_config->channels[idx];
7664 			ret = -ENOMEM;
7668 		ch_info->period = RTW89_CHANNEL_TIME;
7669 		ch_info->ch_band = rtw89_nl80211_to_hw_band(channel->band);
7670 		ch_info->central_ch = channel->hw_value;
7671 		ch_info->pri_ch = channel->hw_value;
7672 		ch_info->is_psc = cfg80211_channel_is_psc(channel);
7674 		if (channel->flags &
7681 					   nd_config->n_match_sets, ch_info);
7682 		list_add_tail(&ch_info->list, &chan_list);
7690 		list_del(&ch_info->list);
7700 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
7701 	struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
7702 	struct cfg80211_scan_request *req = rtwvif->scan_req;
7711 	random_seq = !!(req->flags & NL80211_SCAN_FLAG_RANDOM_SN);
7714 	for (idx = 0; idx < req->n_channels; idx++) {
7715 		channel = req->channels[idx];
7718 			ret = -ENOMEM;
7722 		if (req->duration)
7723 			ch_info->period = req->duration;
7724 		else if (channel->band == NL80211_BAND_6GHZ)
7725 			ch_info->period = RTW89_CHANNEL_TIME_6G + RTW89_DWELL_TIME_6G;
7726 		else if (rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT)
7727 			ch_info->period = RTW89_P2P_CHAN_TIME;
7729 			ch_info->period = RTW89_CHANNEL_TIME;
7731 		ch_info->ch_band = rtw89_nl80211_to_hw_band(channel->band);
7732 		ch_info->central_ch = channel->hw_value;
7733 		ch_info->pri_ch = channel->hw_value;
7734 		ch_info->rand_seq_num = random_seq;
7735 		ch_info->is_psc = cfg80211_channel_is_psc(channel);
7737 		if (channel->flags & (IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR))
7741 		rtw89_hw_scan_add_chan_be(rtwdev, type, req->n_ssids, ch_info);
7743 		list_add_tail(&ch_info->list, &chan_list);
7746 	list_splice_tail(&chan_list, &scan_info->chan_list);
7747 	return 0;
7751 		list_del(&ch_info->list);
7760 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
7763 	list_for_each_entry_safe(ch_info, tmp, &scan_info->chan_list, list) {
7764 		list_del(&ch_info->list);
7772 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
7774 	unsigned int list_len = 0;
7780 	list_for_each_entry_safe(ch_info, tmp, &scan_info->chan_list, list) {
7781 		list_move_tail(&ch_info->list, &list);
7792 		list_del(&ch_info->list);
7803 	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
7815 	ret = mac->prep_chan_list(rtwdev, rtwvif_link);
7833 	beacon_int = bss_conf->beacon_int;
7838 	if (rtwdev->chip->chip_gen == RTW89_CHIP_AX)
7839 		rtwdev->scan_info.delay = ieee80211_tu_to_usec(beacon_int * 3) / 1000;
7848 	if (rtwdev->chip->chip_gen == RTW89_CHIP_AX) {
7867 	const struct rtw89_entity_mgnt *mgnt = &rtwdev->hal.entity_mgnt;
7868 	const struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
7869 	const struct rtw89_chip_info *chip = rtwdev->chip;
7876 	u16 tu = 0;
7878 	lockdep_assert_wiphy(rtwdev->hw->wiphy);
7883 	list_for_each_safe(pos, tmp, &scan_info->chan_list) {
7884 		switch (chip->chip_gen) {
7887 			tu += chinfo_ax->period;
7891 			tu += chinfo_be->period;
7895 				   __func__, chip->chip_gen);
7900 	if (unlikely(tu == 0)) {
7907 	list_for_each_entry(rtwvif, &mgnt->active_list, mgnt_entry) {
7911 		if (vif->type != NL80211_IFTYPE_AP || !vif->p2p)
7924 	struct rtw89_entity_mgnt *mgnt = &rtwdev->hal.entity_mgnt;
7925 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
7926 	struct rtw89_hw_scan_extra_op *ext = &scan_info->extra_op;
7929 	ext->set = false;
7930 	if (!RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD_EXTRA_OP, &rtwdev->fw))
7933 	list_for_each_entry(tmp, &mgnt->active_list, mgnt_entry) {
7940 		tmp_link = rtw89_vif_get_link_inst(tmp, 0);
7943 				    "hw scan: no HW-0 link for extra op\n");
7947 		tmp_chan = rtw89_chan_get(rtwdev, tmp_link->chanctx_idx);
7950 			.macid = tmp_link->mac_id,
7951 			.port = tmp_link->port,
7958 			    ext->chan.channel, ext->chan.primary_channel);
7967 	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
7969 	struct cfg80211_scan_request *req = &scan_req->req;
7971 						       rtwvif_link->chanctx_idx);
7972 	struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
7977 	u32 rx_fltr = rtwdev->hal.rx_fltr;
7983 	rtwdev->scan_info.op_chan = *chan;
7987 		    chan->channel, chan->primary_channel);
7991 	rtwdev->scan_info.connected = rtw89_is_any_vif_connected_or_connecting(rtwdev);
7992 	rtwdev->scan_info.scanning_vif = rtwvif_link;
7993 	rtwdev->scan_info.abort = false;
7994 	rtwdev->scan_info.delay = 0;
7995 	rtwvif->scan_ies = &scan_req->ies;
7996 	rtwvif->scan_req = req;
7998 	if (req->flags & NL80211_SCAN_FLAG_RANDOM_ADDR)
7999 		get_random_mask_addr(mac_addr, req->mac_addr,
8000 				     req->mac_addr_mask);
8002 		ether_addr_copy(mac_addr, rtwvif_link->mac_addr);
8010 	ieee80211_stop_queues(rtwdev->hw);
8019 	reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
8028 	return 0;
8038 	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
8041 	struct rtw89_vif_link *rtwvif_link = cb_data->rtwvif_link;
8043 		.aborted = cb_data->aborted,
8048 		return -EINVAL;
8050 	reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
8051 	rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr);
8054 	ieee80211_scan_completed(rtwdev->hw, &info);
8055 	ieee80211_wake_queues(rtwdev->hw);
8065 	return 0;
8092 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
8095 	scan_info->abort = true;
8118 			if (!is_zero_ether_addr(rtwvif_link->bssid))
8130 	const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
8131 	struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
8132 	const struct rtw89_hw_scan_extra_op *ext = &scan_info->extra_op;
8133 	struct rtw89_scan_option opt = {0};
8135 	int ret = 0;
8138 		return -EINVAL;
8140 	connected = rtwdev->scan_info.connected;
8143 	opt.delay = rtwdev->scan_info.delay;
8145 		ret = mac->add_chan_list(rtwdev, rtwvif_link);
8150 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) {
8153 		opt.band = rtwvif_link->mac_idx;
8154 		opt.num_macc_role = 0;
8155 		opt.mlo_mode = rtwdev->mlo_dbcc_mode;
8156 		opt.num_opch = connected ? 1 : 0;
8157 		if (connected && ext->set)
8160 		opt.opch_end = connected ? 0 : RTW89_CHAN_INVALID;
8169 #define H2C_FW_CPU_EXCEPTION_TYPE_0 0x5566
8170 #define H2C_FW_CPU_EXCEPTION_TYPE_1 0x0
8179 	if (RTW89_CHK_FW_FEATURE(CRASH_TRIGGER_TYPE_1, &rtwdev->fw))
8181 	else if (RTW89_CHK_FW_FEATURE(CRASH_TRIGGER_TYPE_0, &rtwdev->fw))
8184 		return -EOPNOTSUPP;
8190 		return -ENOMEM;
8194 	h2c = (struct rtw89_h2c_trig_cpu_except *)skb->data;
8196 	h2c->w0 = le32_encode_bits(cpu_exception_type_def,
8202 			      H2C_FUNC_CPU_EXCEPTION, 0, 0,
8212 	return 0;
8226 		return -ENOMEM;
8229 	switch (params->sel) {
8239 			    params->sel);
8244 	RTW89_SET_FWCMD_PKT_DROP_SEL(skb->data, params->sel);
8245 	RTW89_SET_FWCMD_PKT_DROP_MACID(skb->data, params->macid);
8246 	RTW89_SET_FWCMD_PKT_DROP_BAND(skb->data, params->mac_band);
8247 	RTW89_SET_FWCMD_PKT_DROP_PORT(skb->data, params->port);
8248 	RTW89_SET_FWCMD_PKT_DROP_MBSSID(skb->data, params->mbssid);
8249 	RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(skb->data, params->tf_trs);
8250 	RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(skb->data,
8251 						  params->macid_band_sel[0]);
8252 	RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(skb->data,
8253 						  params->macid_band_sel[1]);
8254 	RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(skb->data,
8255 						  params->macid_band_sel[2]);
8256 	RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(skb->data,
8257 						  params->macid_band_sel[3]);
8262 			      H2C_FUNC_PKT_DROP, 0, 0,
8271 	return 0;
8283 	u8 pkt_id = 0;
8291 			return -EPERM;
8297 		return -ENOMEM;
8302 	RTW89_SET_KEEP_ALIVE_ENABLE(skb->data, enable);
8303 	RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(skb->data, pkt_id);
8304 	RTW89_SET_KEEP_ALIVE_PERIOD(skb->data, 5);
8305 	RTW89_SET_KEEP_ALIVE_MACID(skb->data, rtwvif_link->mac_id);
8310 			      H2C_FUNC_KEEP_ALIVE, 0, 1,
8319 	return 0;
8333 	u8 pkt_id = 0;
8347 		return -ENOMEM;
8351 	h2c = (struct rtw89_h2c_arp_offload *)skb->data;
8353 	h2c->w0 = le32_encode_bits(enable, RTW89_H2C_ARP_OFFLOAD_W0_ENABLE) |
8354 		  le32_encode_bits(0, RTW89_H2C_ARP_OFFLOAD_W0_ACTION) |
8355 		  le32_encode_bits(rtwvif_link->mac_id, RTW89_H2C_ARP_OFFLOAD_W0_MACID) |
8361 			      H2C_FUNC_ARP_OFLD, 0, 1,
8370 	return 0;
8382 	struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
8384 	u8 macid = rtwvif_link->mac_id;
8390 		return -ENOMEM;
8395 	if (test_bit(RTW89_WOW_FLAG_EN_DISCONNECT, rtw_wow->flags)) {
8396 		RTW89_SET_DISCONNECT_DETECT_ENABLE(skb->data, enable);
8397 		RTW89_SET_DISCONNECT_DETECT_DISCONNECT(skb->data, !enable);
8398 		RTW89_SET_DISCONNECT_DETECT_MAC_ID(skb->data, macid);
8399 		RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(skb->data, 100);
8400 		RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(skb->data, 5);
8406 			      H2C_FUNC_DISCONNECT_DETECT, 0, 1,
8415 	return 0;
8426 	struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
8427 	struct cfg80211_sched_scan_request *nd_config = rtw_wow->nd_config;
8436 		return -ENOMEM;
8440 	h2c = (struct rtw89_h2c_cfg_nlo *)skb->data;
8442 	h2c->w0 = le32_encode_bits(enable, RTW89_H2C_NLO_W0_ENABLE) |
8444 		  le32_encode_bits(rtwvif_link->mac_id, RTW89_H2C_NLO_W0_MACID);
8447 		h2c->nlo_cnt = nd_config->n_match_sets;
8448 		for (i = 0 ; i < nd_config->n_match_sets; i++) {
8449 			h2c->ssid_len[i] = nd_config->match_sets[i].ssid.ssid_len;
8450 			memcpy(h2c->ssid[i], nd_config->match_sets[i].ssid.ssid,
8451 			       nd_config->match_sets[i].ssid.ssid_len);
8458 			      H2C_FUNC_NLO, 0, 1,
8467 	return 0;
8477 	struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
8479 	u8 macid = rtwvif_link->mac_id;
8487 		return -ENOMEM;
8491 	h2c = (struct rtw89_h2c_wow_global *)skb->data;
8493 	h2c->w0 = le32_encode_bits(enable, RTW89_H2C_WOW_GLOBAL_W0_ENABLE) |
8495 		  le32_encode_bits(rtw_wow->ptk_alg,
8497 		  le32_encode_bits(rtw_wow->gtk_alg,
8499 	h2c->key_info = rtw_wow->key_info;
8504 			      H2C_FUNC_WOW_GLOBAL, 0, 1,
8513 	return 0;
8526 	struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
8528 	u8 macid = rtwvif_link->mac_id;
8534 		return -ENOMEM;
8539 	if (rtw_wow->pattern_cnt)
8540 		RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(skb->data, enable);
8541 	if (test_bit(RTW89_WOW_FLAG_EN_MAGIC_PKT, rtw_wow->flags))
8542 		RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(skb->data, enable);
8543 	if (test_bit(RTW89_WOW_FLAG_EN_DISCONNECT, rtw_wow->flags))
8544 		RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(skb->data, enable);
8546 	RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(skb->data, macid);
8551 			      H2C_FUNC_WAKEUP_CTRL, 0, 1,
8560 	return 0;
8578 		return -ENOMEM;
8583 	RTW89_SET_WOW_CAM_UPD_R_W(skb->data, cam_info->r_w);
8584 	RTW89_SET_WOW_CAM_UPD_IDX(skb->data, cam_info->idx);
8585 	if (cam_info->valid) {
8586 		RTW89_SET_WOW_CAM_UPD_WKFM1(skb->data, cam_info->mask[0]);
8587 		RTW89_SET_WOW_CAM_UPD_WKFM2(skb->data, cam_info->mask[1]);
8588 		RTW89_SET_WOW_CAM_UPD_WKFM3(skb->data, cam_info->mask[2]);
8589 		RTW89_SET_WOW_CAM_UPD_WKFM4(skb->data, cam_info->mask[3]);
8590 		RTW89_SET_WOW_CAM_UPD_CRC(skb->data, cam_info->crc);
8591 		RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(skb->data,
8592 							     cam_info->negative_pattern_match);
8593 		RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(skb->data,
8594 						   cam_info->skip_mac_hdr);
8595 		RTW89_SET_WOW_CAM_UPD_UC(skb->data, cam_info->uc);
8596 		RTW89_SET_WOW_CAM_UPD_MC(skb->data, cam_info->mc);
8597 		RTW89_SET_WOW_CAM_UPD_BC(skb->data, cam_info->bc);
8599 	RTW89_SET_WOW_CAM_UPD_VALID(skb->data, cam_info->valid);
8604 			      H2C_FUNC_WOW_CAM_UPD, 0, 1,
8613 	return 0;
8624 	struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
8625 	struct rtw89_wow_gtk_info *gtk_info = &rtw_wow->gtk_info;
8627 	u8 macid = rtwvif_link->mac_id;
8629 	u8 pkt_id_sa_query = 0;
8631 	u8 pkt_id_eapol = 0;
8634 	if (!rtw_wow->gtk_alg)
8635 		return 0;
8640 		return -ENOMEM;
8644 	h2c = (struct rtw89_h2c_wow_gtk_ofld *)skb->data;
8655 	if (gtk_info->igtk_keyid) {
8664 	h2c->w0 = le32_encode_bits(enable, RTW89_H2C_WOW_GTK_OFLD_W0_EN) |
8665 		  le32_encode_bits(0, RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN) |
8666 		  le32_encode_bits(gtk_info->igtk_keyid ? 1 : 0,
8670 	h2c->w1 = le32_encode_bits(gtk_info->igtk_keyid ? pkt_id_sa_query : 0,
8672 		  le32_encode_bits(rtw_wow->akm, RTW89_H2C_WOW_GTK_OFLD_W1_ALGO_AKM_SUIT);
8673 	h2c->gtk_info = rtw_wow->gtk_info;
8679 			      H2C_FUNC_GTK_OFLD, 0, 1,
8687 	return 0;
8697 	struct rtw89_wait_info *wait = &rtwdev->mac.ps_wait;
8705 		return -ENOMEM;
8708 	h2c = (struct rtw89_h2c_fwips *)skb->data;
8710 	h2c->w0 = le32_encode_bits(rtwvif_link->mac_id, RTW89_H2C_FW_IPS_W0_MACID) |
8716 			      H2C_FUNC_IPS_CFG, 0, 1,
8724 	struct rtw89_wait_info *wait = &rtwdev->wow.wait;
8732 		return -ENOMEM;
8743 			      H2C_FUNC_AOAC_REPORT_REQ, 1, 0,
8749 /* Return < 0, if failures happen during waiting for the condition.
8750  * Return 0, when waiting for the condition succeeds.
8751  * Return > 0, if the wait is considered unreachable due to driver/FW design,
8763 		return -EBUSY;
8766 	if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags))
8776 	struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
8784 		return -ENOMEM;
8788 	RTW89_SET_FWCMD_ADD_MCC_MACID(skb->data, p->macid);
8789 	RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(skb->data, p->central_ch_seg0);
8790 	RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(skb->data, p->central_ch_seg1);
8791 	RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(skb->data, p->primary_ch);
8792 	RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(skb->data, p->bandwidth);
8793 	RTW89_SET_FWCMD_ADD_MCC_GROUP(skb->data, p->group);
8794 	RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(skb->data, p->c2h_rpt);
8795 	RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(skb->data, p->dis_tx_null);
8796 	RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(skb->data, p->dis_sw_retry);
8797 	RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(skb->data, p->in_curr_ch);
8798 	RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(skb->data, p->sw_retry_count);
8799 	RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(skb->data, p->tx_null_early);
8800 	RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(skb->data, p->btc_in_2g);
8801 	RTW89_SET_FWCMD_ADD_MCC_PTA_EN(skb->data, p->pta_en);
8802 	RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(skb->data, p->rfk_by_pass);
8803 	RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(skb->data, p->ch_band_type);
8804 	RTW89_SET_FWCMD_ADD_MCC_DURATION(skb->data, p->duration);
8805 	RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(skb->data, p->courtesy_en);
8806 	RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(skb->data, p->courtesy_num);
8807 	RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(skb->data, p->courtesy_target);
8812 			      H2C_FUNC_ADD_MCC, 0, 0,
8815 	cond = RTW89_MCC_WAIT_COND(p->group, H2C_FUNC_ADD_MCC);
8823 	struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
8831 		return -ENOMEM;
8835 	RTW89_SET_FWCMD_START_MCC_GROUP(skb->data, p->group);
8836 	RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(skb->data, p->btc_in_group);
8837 	RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(skb->data, p->old_group_action);
8838 	RTW89_SET_FWCMD_START_MCC_OLD_GROUP(skb->data, p->old_group);
8839 	RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(skb->data, p->notify_cnt);
8840 	RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(skb->data, p->notify_rxdbg_en);
8841 	RTW89_SET_FWCMD_START_MCC_MACID(skb->data, p->macid);
8842 	RTW89_SET_FWCMD_START_MCC_TSF_LOW(skb->data, p->tsf_low);
8843 	RTW89_SET_FWCMD_START_MCC_TSF_HIGH(skb->data, p->tsf_high);
8848 			      H2C_FUNC_START_MCC, 0, 0,
8851 	cond = RTW89_MCC_WAIT_COND(p->group, H2C_FUNC_START_MCC);
8859 	struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
8867 		return -ENOMEM;
8871 	RTW89_SET_FWCMD_STOP_MCC_MACID(skb->data, macid);
8872 	RTW89_SET_FWCMD_STOP_MCC_GROUP(skb->data, group);
8873 	RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(skb->data, prev_groups);
8878 			      H2C_FUNC_STOP_MCC, 0, 0,
8889 	struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
8897 		return -ENOMEM;
8901 	RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(skb->data, group);
8902 	RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(skb->data, prev_groups);
8907 			      H2C_FUNC_DEL_MCC_GROUP, 0, 0,
8917 	struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
8925 		return -ENOMEM;
8929 	RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(skb->data, group);
8934 			      H2C_FUNC_RESET_MCC_GROUP, 0, 0,
8946 	struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
8956 		return -ENOMEM;
8960 	RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(skb->data, req->group);
8961 	RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(skb->data, req->macid_x);
8962 	RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(skb->data, req->macid_y);
8967 			      H2C_FUNC_MCC_REQ_TSF, 0, 0,
8970 	cond = RTW89_MCC_WAIT_COND(req->group, H2C_FUNC_MCC_REQ_TSF);
8975 	tmp = (struct rtw89_mac_mcc_tsf_rpt *)wait->data.buf;
8978 	return 0;
8985 	struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
8998 		return -ENOMEM;
9002 	RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(skb->data, group);
9003 	RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(skb->data, macid);
9004 	RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(skb->data, map_len);
9005 	RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(skb->data, bitmap, map_len);
9010 			      H2C_FUNC_MCC_MACID_BITMAP, 0, 0,
9021 	struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
9029 		return -ENOMEM;
9033 	RTW89_SET_FWCMD_MCC_SYNC_GROUP(skb->data, group);
9034 	RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(skb->data, source);
9035 	RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(skb->data, target);
9036 	RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(skb->data, offset);
9041 			      H2C_FUNC_MCC_SYNC, 0, 0,
9052 	struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
9060 		return -ENOMEM;
9064 	RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(skb->data, p->group);
9065 	RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(skb->data, p->btc_in_group);
9066 	RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(skb->data, p->start_macid);
9067 	RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(skb->data, p->macid_x);
9068 	RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(skb->data, p->macid_y);
9069 	RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(skb->data,
9070 						       p->start_tsf_low);
9071 	RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(skb->data,
9072 							p->start_tsf_high);
9073 	RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(skb->data, p->duration_x);
9074 	RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(skb->data, p->duration_y);
9079 			      H2C_FUNC_MCC_SET_DURATION, 0, 0,
9082 	cond = RTW89_MCC_WAIT_COND(p->group, H2C_FUNC_MCC_SET_DURATION);
9097 	slot_h2c->w0 = le32_encode_bits(slot_arg->duration,
9099 		       le32_encode_bits(slot_arg->courtesy_en,
9101 		       le32_encode_bits(slot_arg->role_num,
9103 	slot_h2c->w1 = le32_encode_bits(slot_arg->courtesy_period,
9105 		       le32_encode_bits(slot_arg->courtesy_target,
9108 	for (i = 0; i < slot_arg->role_num; i++) {
9109 		slot_h2c->roles[i].w0 =
9110 			le32_encode_bits(slot_arg->roles[i].macid,
9112 			le32_encode_bits(slot_arg->roles[i].role_type,
9114 			le32_encode_bits(slot_arg->roles[i].is_master,
9116 			le32_encode_bits(slot_arg->roles[i].en_tx_null,
9122 		slot_h2c->roles[i].w1 =
9123 			le32_encode_bits(slot_arg->roles[i].central_ch,
9125 			le32_encode_bits(slot_arg->roles[i].primary_ch,
9127 			le32_encode_bits(slot_arg->roles[i].bw,
9129 			le32_encode_bits(slot_arg->roles[i].band,
9131 			le32_encode_bits(slot_arg->roles[i].null_early,
9137 		slot_h2c->roles[i].macid_main_bitmap =
9138 			cpu_to_le32(slot_arg->roles[i].macid_main_bitmap);
9139 		slot_h2c->roles[i].macid_paired_bitmap =
9140 			cpu_to_le32(slot_arg->roles[i].macid_paired_bitmap);
9144 	return struct_size(slot_h2c, roles, slot_arg->role_num);
9162 	for (i = 0; i < arg->slot_num; i++)
9163 		len += rtw89_fw_h2c_mrc_add_slot(rtwdev, &arg->slots[i], NULL);
9168 		return -ENOMEM;
9172 	tmp = skb->data;
9179 	h2c_head->w0 = le32_encode_bits(arg->sch_idx,
9181 		       le32_encode_bits(arg->sch_type,
9183 		       le32_encode_bits(arg->slot_num,
9185 		       le32_encode_bits(arg->btc_in_sch,
9189 	for (i = 0; i < arg->slot_num; i++)
9191 		tmp += rtw89_fw_h2c_mrc_add_slot(rtwdev, &arg->slots[i], tmp);
9193 		tmp += rtw89_fw_h2c_mrc_add_slot(rtwdev, &arg->slots[i], (void *)tmp);
9199 			      H2C_FUNC_ADD_MRC, 0, 0,
9206 		return -EBUSY;
9209 	return 0;
9215 	struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
9224 		return -ENOMEM;
9228 	h2c = (struct rtw89_h2c_mrc_start *)skb->data;
9230 	h2c->w0 = le32_encode_bits(arg->sch_idx,
9232 		  le32_encode_bits(arg->old_sch_idx,
9234 		  le32_encode_bits(arg->action,
9237 	h2c->start_tsf_high = cpu_to_le32(arg->start_tsf >> 32);
9238 	h2c->start_tsf_low = cpu_to_le32(arg->start_tsf);
9243 			      H2C_FUNC_START_MRC, 0, 0,
9246 	cond = RTW89_MRC_WAIT_COND(arg->sch_idx, H2C_FUNC_START_MRC);
9252 	struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
9261 		return -ENOMEM;
9265 	h2c = (struct rtw89_h2c_mrc_del *)skb->data;
9267 	h2c->w0 = le32_encode_bits(sch_idx, RTW89_H2C_MRC_DEL_W0_SCH_IDX) |
9273 			      H2C_FUNC_DEL_MRC, 0, 0,
9284 	struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
9292 	len = struct_size(h2c, infos, arg->num);
9296 		return -ENOMEM;
9300 	h2c = (struct rtw89_h2c_mrc_req_tsf *)skb->data;
9302 	h2c->req_tsf_num = arg->num;
9303 	for (i = 0; i < arg->num; i++)
9304 		h2c->infos[i] =
9305 			u8_encode_bits(arg->infos[i].band,
9307 			u8_encode_bits(arg->infos[i].port,
9313 			      H2C_FUNC_MRC_REQ_TSF, 0, 0,
9320 	tmp = (struct rtw89_mac_mrc_tsf_rpt *)wait->data.buf;
9323 	return 0;
9337 		return -ENOMEM;
9341 	h2c = (struct rtw89_h2c_mrc_upd_bitmap *)skb->data;
9343 	h2c->w0 = le32_encode_bits(arg->sch_idx,
9345 		  le32_encode_bits(arg->action,
9347 		  le32_encode_bits(arg->macid,
9349 	h2c->w1 = le32_encode_bits(arg->client_macid,
9355 			      H2C_FUNC_MRC_UPD_BITMAP, 0, 0,
9362 		return -EBUSY;
9365 	return 0;
9379 		return -ENOMEM;
9383 	h2c = (struct rtw89_h2c_mrc_sync *)skb->data;
9385 	h2c->w0 = le32_encode_bits(true, RTW89_H2C_MRC_SYNC_W0_SYNC_EN) |
9386 		  le32_encode_bits(arg->src.port,
9388 		  le32_encode_bits(arg->src.band,
9390 		  le32_encode_bits(arg->dest.port,
9392 		  le32_encode_bits(arg->dest.band,
9394 	h2c->w1 = le32_encode_bits(arg->offset, RTW89_H2C_MRC_SYNC_W1_OFFSET);
9399 			      H2C_FUNC_MRC_SYNC, 0, 0,
9406 		return -EBUSY;
9409 	return 0;
9421 	len = struct_size(h2c, slots, arg->slot_num);
9425 		return -ENOMEM;
9429 	h2c = (struct rtw89_h2c_mrc_upd_duration *)skb->data;
9431 	h2c->w0 = le32_encode_bits(arg->sch_idx,
9433 		  le32_encode_bits(arg->slot_num,
9438 	h2c->start_tsf_high = cpu_to_le32(arg->start_tsf >> 32);
9439 	h2c->start_tsf_low = cpu_to_le32(arg->start_tsf);
9441 	for (i = 0; i < arg->slot_num; i++) {
9442 		h2c->slots[i] =
9443 			le32_encode_bits(arg->slots[i].slot_idx,
9445 			le32_encode_bits(arg->slots[i].duration,
9452 			      H2C_FUNC_MRC_UPD_DURATION, 0, 0,
9459 		return -EBUSY;
9462 	return 0;
9465 static int rtw89_fw_h2c_ap_info(struct rtw89_dev *rtwdev, bool en)  argument
9475 		return -ENOMEM;
9479 	h2c = (struct rtw89_h2c_ap_info *)skb->data;
9481 	h2c->w0 = le32_encode_bits(en, RTW89_H2C_AP_INFO_W0_PWR_INT_EN);
9486 			      H2C_FUNC_AP_INFO, 0, 0,
9493 		return -EBUSY;
9496 	return 0;
9499 int rtw89_fw_h2c_ap_info_refcount(struct rtw89_dev *rtwdev, bool en)  argument
9503 	if (en) {
9504 		if (refcount_inc_not_zero(&rtwdev->refcount_ap_info))
9505 			return 0;
9507 		if (!refcount_dec_and_test(&rtwdev->refcount_ap_info))
9508 			return 0;
9511 	ret = rtw89_fw_h2c_ap_info(rtwdev, en);
9513 		if (!test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags))
9517 		 * handling, so show a warning, but return 0 with refcount
9519 		 * with @en == false later.
9524 	if (en)
9525 		refcount_set(&rtwdev->refcount_ap_info, 1);
9527 	return 0;
9533 	struct rtw89_wait_info *wait = &rtwdev->mlo.wait;
9535 	u8 mac_id = rtwvif_link->mac_id;
9544 		return -ENOMEM;
9548 	h2c = (struct rtw89_h2c_mlo_link_cfg *)skb->data;
9550 	h2c->w0 = le32_encode_bits(mac_id, RTW89_H2C_MLO_LINK_CFG_W0_MACID) |
9556 			      H2C_FUNC_MLO_LINK_CFG, 0, 0,
9564 			  str_enable_disable(enable), rtwvif_link->link_id, ret);
9568 	return 0;
9575 	return memcmp(ext_ptr, zeros, ext_len) == 0;
9587 						     (ent_sz) - __var_sz);\
9599 						     (ent_sz) - __var_sz);\
9609 	if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
9612 	if (e->band >= RTW89_BAND_NUM || e->bw >= RTW89_BYR_BW_NUM)
9615 	switch (e->rs) {
9617 		if (e->shf + e->len > RTW89_RATE_CCK_NUM)
9621 		if (e->shf + e->len > RTW89_RATE_OFDM_NUM)
9625 		if (e->shf + e->len > __RTW89_RATE_MCS_NUM ||
9626 		    e->nss >= RTW89_NSS_NUM ||
9627 		    e->ofdma >= RTW89_OFDMA_NUM)
9631 		if (e->shf + e->len > RTW89_RATE_HEDCM_NUM ||
9632 		    e->nss >= RTW89_NSS_HEDCM_NUM ||
9633 		    e->ofdma >= RTW89_OFDMA_NUM)
9637 		if (e->shf + e->len > __RTW89_RATE_OFFSET_NUM)
9651 	const struct rtw89_txpwr_conf *conf = tbl->data;
9668 		byr_head = &rtwdev->byr[entry.band][entry.bw];
9674 		for (i = 0; i < entry.len; i++, data >>= 8) {
9677 			*byr = data & 0xff;
9687 	if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
9690 	if (e->bw >= RTW89_2G_BW_NUM)
9692 	if (e->nt >= RTW89_NTX_NUM)
9694 	if (e->rs >= RTW89_RS_LMT_NUM)
9696 	if (e->bf >= RTW89_BF_NUM)
9698 	if (e->regd >= RTW89_REGD_NUM)
9700 	if (e->ch_idx >= RTW89_2G_CH_NUM)
9709 	const struct rtw89_txpwr_conf *conf = &data->conf;
9721 		data->v[entry.bw][entry.nt][entry.rs][entry.bf][entry.regd]
9731 	if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
9734 	if (e->bw >= RTW89_5G_BW_NUM)
9736 	if (e->nt >= RTW89_NTX_NUM)
9738 	if (e->rs >= RTW89_RS_LMT_NUM)
9740 	if (e->bf >= RTW89_BF_NUM)
9742 	if (e->regd >= RTW89_REGD_NUM)
9744 	if (e->ch_idx >= RTW89_5G_CH_NUM)
9753 	const struct rtw89_txpwr_conf *conf = &data->conf;
9765 		data->v[entry.bw][entry.nt][entry.rs][entry.bf][entry.regd]
9775 	if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
9778 	if (e->bw >= RTW89_6G_BW_NUM)
9780 	if (e->nt >= RTW89_NTX_NUM)
9782 	if (e->rs >= RTW89_RS_LMT_NUM)
9784 	if (e->bf >= RTW89_BF_NUM)
9786 	if (e->regd >= RTW89_REGD_NUM)
9788 	if (e->reg_6ghz_power >= NUM_OF_RTW89_REG_6GHZ_POWER)
9790 	if (e->ch_idx >= RTW89_6G_CH_NUM)
9799 	const struct rtw89_txpwr_conf *conf = &data->conf;
9811 		data->v[entry.bw][entry.nt][entry.rs][entry.bf][entry.regd]
9821 	if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
9824 	if (e->ru >= RTW89_RU_NUM)
9826 	if (e->nt >= RTW89_NTX_NUM)
9828 	if (e->regd >= RTW89_REGD_NUM)
9830 	if (e->ch_idx >= RTW89_2G_CH_NUM)
9839 	const struct rtw89_txpwr_conf *conf = &data->conf;
9851 		data->v[entry.ru][entry.nt][entry.regd][entry.ch_idx] = entry.v;
9860 	if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
9863 	if (e->ru >= RTW89_RU_NUM)
9865 	if (e->nt >= RTW89_NTX_NUM)
9867 	if (e->regd >= RTW89_REGD_NUM)
9869 	if (e->ch_idx >= RTW89_5G_CH_NUM)
9878 	const struct rtw89_txpwr_conf *conf = &data->conf;
9890 		data->v[entry.ru][entry.nt][entry.regd][entry.ch_idx] = entry.v;
9899 	if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
9902 	if (e->ru >= RTW89_RU_NUM)
9904 	if (e->nt >= RTW89_NTX_NUM)
9906 	if (e->regd >= RTW89_REGD_NUM)
9908 	if (e->reg_6ghz_power >= NUM_OF_RTW89_REG_6GHZ_POWER)
9910 	if (e->ch_idx >= RTW89_6G_CH_NUM)
9919 	const struct rtw89_txpwr_conf *conf = &data->conf;
9931 		data->v[entry.ru][entry.nt][entry.regd][entry.reg_6ghz_power]
9941 	if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
9944 	if (e->band >= RTW89_BAND_NUM)
9946 	if (e->tx_shape_rs >= RTW89_RS_TX_SHAPE_NUM)
9948 	if (e->regd >= RTW89_REGD_NUM)
9957 	const struct rtw89_txpwr_conf *conf = &data->conf;
9969 		data->v[entry.band][entry.tx_shape_rs][entry.regd] = entry.v;
9978 	if (!__fw_txpwr_entry_acceptable(e, cursor, conf->ent_sz))
9981 	if (e->band >= RTW89_BAND_NUM)
9983 	if (e->regd >= RTW89_REGD_NUM)
9992 	const struct rtw89_txpwr_conf *conf = &data->conf;
10004 		data->v[entry.band][entry.regd] = entry.v;
10011 	const struct rtw89_chip_info *chip = rtwdev->chip;
10013 	if (chip->support_bands & BIT(NL80211_BAND_2GHZ) &&
10014 	    !(parms->rule_da_2ghz.lmt && parms->rule_da_2ghz.lmt_ru))
10017 	if (chip->support_bands & BIT(NL80211_BAND_5GHZ) &&
10018 	    !(parms->rule_da_5ghz.lmt && parms->rule_da_5ghz.lmt_ru))
10021 	if (chip->support_bands & BIT(NL80211_BAND_6GHZ) &&
10022 	    !(parms->rule_da_6ghz.lmt && parms->rule_da_6ghz.lmt_ru))
10032 	struct rtw89_rfe_data *rfe_data = rtwdev->rfe_data;
10038 	parms = &rfe_data->rfe_parms;
10042 	if (rtw89_txpwr_conf_valid(&rfe_data->byrate.conf)) {
10043 		rfe_data->byrate.tbl.data = &rfe_data->byrate.conf;
10044 		rfe_data->byrate.tbl.size = 0; /* don't care here */
10045 		rfe_data->byrate.tbl.load = rtw89_fw_load_txpwr_byrate;
10046 		parms->byr_tbl = &rfe_data->byrate.tbl;
10049 	if (rtw89_txpwr_conf_valid(&rfe_data->lmt_2ghz.conf)) {
10050 		rtw89_fw_load_txpwr_lmt_2ghz(&rfe_data->lmt_2ghz);
10051 		parms->rule_2ghz.lmt = &rfe_data->lmt_2ghz.v;
10054 	if (rtw89_txpwr_conf_valid(&rfe_data->lmt_5ghz.conf)) {
10055 		rtw89_fw_load_txpwr_lmt_5ghz(&rfe_data->lmt_5ghz);
10056 		parms->rule_5ghz.lmt = &rfe_data->lmt_5ghz.v;
10059 	if (rtw89_txpwr_conf_valid(&rfe_data->lmt_6ghz.conf)) {
10060 		rtw89_fw_load_txpwr_lmt_6ghz(&rfe_data->lmt_6ghz);
10061 		parms->rule_6ghz.lmt = &rfe_data->lmt_6ghz.v;
10064 	if (rtw89_txpwr_conf_valid(&rfe_data->da_lmt_2ghz.conf)) {
10065 		rtw89_fw_load_txpwr_lmt_2ghz(&rfe_data->da_lmt_2ghz);
10066 		parms->rule_da_2ghz.lmt = &rfe_data->da_lmt_2ghz.v;
10069 	if (rtw89_txpwr_conf_valid(&rfe_data->da_lmt_5ghz.conf)) {
10070 		rtw89_fw_load_txpwr_lmt_5ghz(&rfe_data->da_lmt_5ghz);
10071 		parms->rule_da_5ghz.lmt = &rfe_data->da_lmt_5ghz.v;
10074 	if (rtw89_txpwr_conf_valid(&rfe_data->da_lmt_6ghz.conf)) {
10075 		rtw89_fw_load_txpwr_lmt_6ghz(&rfe_data->da_lmt_6ghz);
10076 		parms->rule_da_6ghz.lmt = &rfe_data->da_lmt_6ghz.v;
10079 	if (rtw89_txpwr_conf_valid(&rfe_data->lmt_ru_2ghz.conf)) {
10080 		rtw89_fw_load_txpwr_lmt_ru_2ghz(&rfe_data->lmt_ru_2ghz);
10081 		parms->rule_2ghz.lmt_ru = &rfe_data->lmt_ru_2ghz.v;
10084 	if (rtw89_txpwr_conf_valid(&rfe_data->lmt_ru_5ghz.conf)) {
10085 		rtw89_fw_load_txpwr_lmt_ru_5ghz(&rfe_data->lmt_ru_5ghz);
10086 		parms->rule_5ghz.lmt_ru = &rfe_data->lmt_ru_5ghz.v;
10089 	if (rtw89_txpwr_conf_valid(&rfe_data->lmt_ru_6ghz.conf)) {
10090 		rtw89_fw_load_txpwr_lmt_ru_6ghz(&rfe_data->lmt_ru_6ghz);
10091 		parms->rule_6ghz.lmt_ru = &rfe_data->lmt_ru_6ghz.v;
10094 	if (rtw89_txpwr_conf_valid(&rfe_data->da_lmt_ru_2ghz.conf)) {
10095 		rtw89_fw_load_txpwr_lmt_ru_2ghz(&rfe_data->da_lmt_ru_2ghz);
10096 		parms->rule_da_2ghz.lmt_ru = &rfe_data->da_lmt_ru_2ghz.v;
10099 	if (rtw89_txpwr_conf_valid(&rfe_data->da_lmt_ru_5ghz.conf)) {
10100 		rtw89_fw_load_txpwr_lmt_ru_5ghz(&rfe_data->da_lmt_ru_5ghz);
10101 		parms->rule_da_5ghz.lmt_ru = &rfe_data->da_lmt_ru_5ghz.v;
10104 	if (rtw89_txpwr_conf_valid(&rfe_data->da_lmt_ru_6ghz.conf)) {
10105 		rtw89_fw_load_txpwr_lmt_ru_6ghz(&rfe_data->da_lmt_ru_6ghz);
10106 		parms->rule_da_6ghz.lmt_ru = &rfe_data->da_lmt_ru_6ghz.v;
10109 	if (rtw89_txpwr_conf_valid(&rfe_data->tx_shape_lmt.conf)) {
10110 		rtw89_fw_load_tx_shape_lmt(&rfe_data->tx_shape_lmt);
10111 		parms->tx_shape.lmt = &rfe_data->tx_shape_lmt.v;
10114 	if (rtw89_txpwr_conf_valid(&rfe_data->tx_shape_lmt_ru.conf)) {
10115 		rtw89_fw_load_tx_shape_lmt_ru(&rfe_data->tx_shape_lmt_ru);
10116 		parms->tx_shape.lmt_ru = &rfe_data->tx_shape_lmt_ru.v;
10119 	parms->has_da = rtw89_fw_has_da_txpwr_table(rtwdev, parms);