Lines Matching refs:seq_puts
235 seq_puts(m, "\n");
392 seq_puts(m, "\n");
394 seq_puts(m, "\n");
810 seq_puts(m, #_regd "\n"); \
878 seq_puts(m, "[Regulatory] ");
904 seq_puts(m, "[SAR]\n");
907 seq_puts(m, "[TAS]\n");
910 seq_puts(m, "[DAG]\n");
919 seq_puts(m, "\n[TX power byrate]\n");
924 seq_puts(m, "\n[TX power limit]\n");
929 seq_puts(m, "\n[TX power limit_ru]\n");
992 seq_puts(m, "Debug selected MAC page 0x00\n");
997 seq_puts(m, "Debug selected MAC page 0x30\n");
1002 seq_puts(m, "Debug selected MAC page 0x40\n");
1007 seq_puts(m, "Debug selected MAC page 0x80\n");
1012 seq_puts(m, "Debug selected MAC page 0xc0\n");
1017 seq_puts(m, "Debug selected MAC page 0xe0\n");
1022 seq_puts(m, "Debug selected BB register\n");
1027 seq_puts(m, "Debug selected IQK register\n");
1032 seq_puts(m, "Debug selected RFC register\n");
1037 seq_puts(m, "Selected invalid register page\n");
1049 seq_puts(m, "\n");
1122 seq_puts(m, "\n");
1290 seq_puts(m, "[DLE] : DMAC not enabled\n");
1337 seq_puts(m, "[DMAC] : DMAC not enabled\n");
1594 seq_puts(m, "[CMAC] : CMAC1 not enabled\n");
1596 seq_puts(m, "[CMAC] : CMAC0 not enabled\n");
2505 seq_puts(m, "Enable PTCL C0 dbgport.\n");
2512 seq_puts(m, "Enable PTCL C1 dbgport.\n");
2519 seq_puts(m, "Enable SCH C0 dbgport.\n");
2526 seq_puts(m, "Enable SCH C1 dbgport.\n");
2543 seq_puts(m, "Enable TMAC C0 dbgport.\n");
2560 seq_puts(m, "Enable TMAC C1 dbgport.\n");
2582 seq_puts(m, "Enable RMAC C0 dbgport.\n");
2604 seq_puts(m, "Enable RMAC C1 dbgport.\n");
2608 seq_puts(m, "Enable RMAC state C0 dbgport.\n");
2612 seq_puts(m, "Enable RMAC state C1 dbgport.\n");
2616 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n");
2620 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n");
2632 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n");
2644 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n");
2651 seq_puts(m, "Enable tx infol dump.\n");
2658 seq_puts(m, "Enable tx infoh dump.\n");
2665 seq_puts(m, "Enable tx infol dump.\n");
2672 seq_puts(m, "Enable tx infoh dump.\n");
2679 seq_puts(m, "Enable tx tf infol dump.\n");
2686 seq_puts(m, "Enable tx tf infoh dump.\n");
2693 seq_puts(m, "Enable tx tf infol dump.\n");
2700 seq_puts(m, "Enable tx tf infoh dump.\n");
2704 seq_puts(m, "Enable wde bufmgn freepg dump.\n");
2708 seq_puts(m, "Enable wde bufmgn quota dump.\n");
2712 seq_puts(m, "Enable wde bufmgn pagellt dump.\n");
2716 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n");
2720 seq_puts(m, "Enable wde quemgn prepkt dump.\n");
2724 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n");
2728 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n");
2732 seq_puts(m, "Enable wde quemgn qempty dump.\n");
2736 seq_puts(m, "Enable ple bufmgn freepg dump.\n");
2740 seq_puts(m, "Enable ple bufmgn quota dump.\n");
2744 seq_puts(m, "Enable ple bufmgn pagellt dump.\n");
2748 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n");
2752 seq_puts(m, "Enable ple quemgn prepkt dump.\n");
2756 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n");
2760 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n");
2764 seq_puts(m, "Enable ple quemgn qempty dump.\n");
2768 seq_puts(m, "Enable pktinfo dump.\n");
2795 seq_puts(m, "Enable Dispatcher hdt tx6 dump.\n");
2803 seq_puts(m, "Enable Dispatcher hdt tx7 dump.\n");
2811 seq_puts(m, "Enable Dispatcher hdt tx8 dump.\n");
2831 seq_puts(m, "Enable Dispatcher hdt txD dump.\n");
2839 seq_puts(m, "Enable Dispatcher cdt tx0 dump.\n");
2847 seq_puts(m, "Enable Dispatcher cdt tx1 dump.\n");
2855 seq_puts(m, "Enable Dispatcher cdt tx3 dump.\n");
2863 seq_puts(m, "Enable Dispatcher cdt tx4 dump.\n");
2883 seq_puts(m, "Enable Dispatcher cdt tx9 dump.\n");
2902 seq_puts(m, "Enable Dispatcher hdt rx0 dump.\n");
2920 seq_puts(m, "Enable Dispatcher hdt rx3 dump.\n");
2928 seq_puts(m, "Enable Dispatcher hdt rx4 dump.\n");
2936 seq_puts(m, "Enable Dispatcher hdt rx5 dump.\n");
2944 seq_puts(m, "Enable Dispatcher cdt rx part0 0 dump.\n");
2953 seq_puts(m, "Enable Dispatcher cdt rx part0 1 dump.\n");
2961 seq_puts(m, "Enable Dispatcher cdt rx part0 2 dump.\n");
2967 seq_puts(m, "Enable Dispatcher cdt rx part1 dump.\n");
2973 seq_puts(m, "Enable Dispatcher stf control dump.\n");
2979 seq_puts(m, "Enable Dispatcher addr control dump.\n");
2985 seq_puts(m, "Enable Dispatcher wde interface dump.\n");
2991 seq_puts(m, "Enable Dispatcher ple interface dump.\n");
2997 seq_puts(m, "Enable Dispatcher flow control dump.\n");
3005 seq_puts(m, "Enable pcie txdma dump.\n");
3013 seq_puts(m, "Enable pcie rxdma dump.\n");
3021 seq_puts(m, "Enable pcie cvt dump.\n");
3029 seq_puts(m, "Enable pcie cxpl dump.\n");
3037 seq_puts(m, "Enable pcie io dump.\n");
3045 seq_puts(m, "Enable pcie misc dump.\n");
3053 seq_puts(m, "Enable pcie misc2 dump.\n");
3056 seq_puts(m, "Dbg port select err\n");
3110 seq_puts(m, "Dump debug port " #__sel ":\n"); \
3632 seq_puts(m, "]\n");
3644 seq_puts(m, "]\t");
3722 seq_puts(m, "RX count:\n");
3734 seq_puts(m, "][");
3738 seq_puts(m, "]\n");
3767 seq_puts(m, "\n");
3793 seq_puts(m, "\n");
3832 seq_puts(m, "\tba_cam ");
3835 seq_puts(m, ", ");
3840 seq_puts(m, "\n");
3884 seq_puts(m, "map:\n");