Lines Matching +full:0 +full:x422
33 #define MASKBYTE0 0xff
34 #define MASKBYTE1 0xff00
35 #define MASKBYTE2 0xff0000
36 #define MASKBYTE3 0xff000000
37 #define MASKBYTE4 0xff00000000ULL
38 #define MASKHWORD 0xffff0000
39 #define MASKLWORD 0x0000ffff
40 #define MASKDWORD 0xffffffff
41 #define RFREG_MASK 0xfffff
42 #define INV_RF_DATA 0xffffffff
43 #define BYPASS_CR_DATA 0xbabecafe
57 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \
63 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
72 HTC_OM_CHANNEL_WIDTH_20 = 0,
84 #define RTW89_TF_PAD GENMASK(11, 0)
88 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
95 RTW89_CH_2G = 0,
179 RTW89_CORE_RX_TYPE_WIFI = 0,
197 RTW89_TXQ_F_AMPDU = 0,
203 RTW89_NET_TYPE_NO_LINK = 0,
256 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
257 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
258 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
261 RTW89_ADDR_CAM_SEC_NONE = 0,
268 RTW89_SEC_KEY_TYPE_NONE = 0,
282 RTW89_PORT_0 = 0,
291 RTW89_BAND_2G = 0,
298 RTW89_HW_RATE_CCK1 = 0x0,
299 RTW89_HW_RATE_CCK2 = 0x1,
300 RTW89_HW_RATE_CCK5_5 = 0x2,
301 RTW89_HW_RATE_CCK11 = 0x3,
302 RTW89_HW_RATE_OFDM6 = 0x4,
303 RTW89_HW_RATE_OFDM9 = 0x5,
304 RTW89_HW_RATE_OFDM12 = 0x6,
305 RTW89_HW_RATE_OFDM18 = 0x7,
306 RTW89_HW_RATE_OFDM24 = 0x8,
307 RTW89_HW_RATE_OFDM36 = 0x9,
308 RTW89_HW_RATE_OFDM48 = 0xA,
309 RTW89_HW_RATE_OFDM54 = 0xB,
310 RTW89_HW_RATE_MCS0 = 0x80,
311 RTW89_HW_RATE_MCS1 = 0x81,
312 RTW89_HW_RATE_MCS2 = 0x82,
313 RTW89_HW_RATE_MCS3 = 0x83,
314 RTW89_HW_RATE_MCS4 = 0x84,
315 RTW89_HW_RATE_MCS5 = 0x85,
316 RTW89_HW_RATE_MCS6 = 0x86,
317 RTW89_HW_RATE_MCS7 = 0x87,
318 RTW89_HW_RATE_MCS8 = 0x88,
319 RTW89_HW_RATE_MCS9 = 0x89,
320 RTW89_HW_RATE_MCS10 = 0x8A,
321 RTW89_HW_RATE_MCS11 = 0x8B,
322 RTW89_HW_RATE_MCS12 = 0x8C,
323 RTW89_HW_RATE_MCS13 = 0x8D,
324 RTW89_HW_RATE_MCS14 = 0x8E,
325 RTW89_HW_RATE_MCS15 = 0x8F,
326 RTW89_HW_RATE_MCS16 = 0x90,
327 RTW89_HW_RATE_MCS17 = 0x91,
328 RTW89_HW_RATE_MCS18 = 0x92,
329 RTW89_HW_RATE_MCS19 = 0x93,
330 RTW89_HW_RATE_MCS20 = 0x94,
331 RTW89_HW_RATE_MCS21 = 0x95,
332 RTW89_HW_RATE_MCS22 = 0x96,
333 RTW89_HW_RATE_MCS23 = 0x97,
334 RTW89_HW_RATE_MCS24 = 0x98,
335 RTW89_HW_RATE_MCS25 = 0x99,
336 RTW89_HW_RATE_MCS26 = 0x9A,
337 RTW89_HW_RATE_MCS27 = 0x9B,
338 RTW89_HW_RATE_MCS28 = 0x9C,
339 RTW89_HW_RATE_MCS29 = 0x9D,
340 RTW89_HW_RATE_MCS30 = 0x9E,
341 RTW89_HW_RATE_MCS31 = 0x9F,
342 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100,
343 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101,
344 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102,
345 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103,
346 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104,
347 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105,
348 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106,
349 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107,
350 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108,
351 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109,
352 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110,
353 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111,
354 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112,
355 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113,
356 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114,
357 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115,
358 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116,
359 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117,
360 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118,
361 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119,
362 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120,
363 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121,
364 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122,
365 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123,
366 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124,
367 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125,
368 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126,
369 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127,
370 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128,
371 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129,
372 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130,
373 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131,
374 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132,
375 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133,
376 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134,
377 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135,
378 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136,
379 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137,
380 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138,
381 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139,
382 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180,
383 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181,
384 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182,
385 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183,
386 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184,
387 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185,
388 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186,
389 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187,
390 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188,
391 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189,
392 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A,
393 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B,
394 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190,
395 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191,
396 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192,
397 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193,
398 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194,
399 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195,
400 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196,
401 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197,
402 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198,
403 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199,
404 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A,
405 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B,
406 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0,
407 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1,
408 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2,
409 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3,
410 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4,
411 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5,
412 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6,
413 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7,
414 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8,
415 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9,
416 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA,
417 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB,
418 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0,
419 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1,
420 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2,
421 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3,
422 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4,
423 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5,
424 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6,
425 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7,
426 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8,
427 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9,
428 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA,
429 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB,
431 RTW89_HW_RATE_V1_MCS0 = 0x100,
432 RTW89_HW_RATE_V1_MCS1 = 0x101,
433 RTW89_HW_RATE_V1_MCS2 = 0x102,
434 RTW89_HW_RATE_V1_MCS3 = 0x103,
435 RTW89_HW_RATE_V1_MCS4 = 0x104,
436 RTW89_HW_RATE_V1_MCS5 = 0x105,
437 RTW89_HW_RATE_V1_MCS6 = 0x106,
438 RTW89_HW_RATE_V1_MCS7 = 0x107,
439 RTW89_HW_RATE_V1_MCS8 = 0x108,
440 RTW89_HW_RATE_V1_MCS9 = 0x109,
441 RTW89_HW_RATE_V1_MCS10 = 0x10A,
442 RTW89_HW_RATE_V1_MCS11 = 0x10B,
443 RTW89_HW_RATE_V1_MCS12 = 0x10C,
444 RTW89_HW_RATE_V1_MCS13 = 0x10D,
445 RTW89_HW_RATE_V1_MCS14 = 0x10E,
446 RTW89_HW_RATE_V1_MCS15 = 0x10F,
447 RTW89_HW_RATE_V1_MCS16 = 0x110,
448 RTW89_HW_RATE_V1_MCS17 = 0x111,
449 RTW89_HW_RATE_V1_MCS18 = 0x112,
450 RTW89_HW_RATE_V1_MCS19 = 0x113,
451 RTW89_HW_RATE_V1_MCS20 = 0x114,
452 RTW89_HW_RATE_V1_MCS21 = 0x115,
453 RTW89_HW_RATE_V1_MCS22 = 0x116,
454 RTW89_HW_RATE_V1_MCS23 = 0x117,
455 RTW89_HW_RATE_V1_MCS24 = 0x118,
456 RTW89_HW_RATE_V1_MCS25 = 0x119,
457 RTW89_HW_RATE_V1_MCS26 = 0x11A,
458 RTW89_HW_RATE_V1_MCS27 = 0x11B,
459 RTW89_HW_RATE_V1_MCS28 = 0x11C,
460 RTW89_HW_RATE_V1_MCS29 = 0x11D,
461 RTW89_HW_RATE_V1_MCS30 = 0x11E,
462 RTW89_HW_RATE_V1_MCS31 = 0x11F,
463 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200,
464 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201,
465 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202,
466 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203,
467 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204,
468 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205,
469 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206,
470 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207,
471 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208,
472 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209,
473 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A,
474 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B,
475 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220,
476 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221,
477 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222,
478 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223,
479 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224,
480 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225,
481 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226,
482 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227,
483 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228,
484 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229,
485 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A,
486 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B,
487 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240,
488 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241,
489 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242,
490 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243,
491 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244,
492 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245,
493 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246,
494 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247,
495 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248,
496 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249,
497 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A,
498 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B,
499 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260,
500 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261,
501 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262,
502 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263,
503 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264,
504 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265,
505 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266,
506 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267,
507 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268,
508 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269,
509 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A,
510 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B,
511 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300,
512 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301,
513 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302,
514 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303,
515 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304,
516 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305,
517 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306,
518 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307,
519 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308,
520 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309,
521 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A,
522 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B,
523 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320,
524 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321,
525 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322,
526 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323,
527 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324,
528 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325,
529 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326,
530 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327,
531 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328,
532 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329,
533 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A,
534 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B,
535 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340,
536 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341,
537 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342,
538 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343,
539 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344,
540 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345,
541 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346,
542 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347,
543 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348,
544 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349,
545 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A,
546 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B,
547 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360,
548 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361,
549 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362,
550 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363,
551 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364,
552 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365,
553 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366,
554 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367,
555 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368,
556 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369,
557 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A,
558 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B,
559 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400,
560 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401,
561 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402,
562 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403,
563 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404,
564 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405,
565 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406,
566 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407,
567 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408,
568 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409,
569 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A,
570 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B,
571 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C,
572 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D,
573 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E,
574 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F,
575 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420,
576 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421,
577 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422,
578 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423,
579 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424,
580 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425,
581 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426,
582 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427,
583 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428,
584 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429,
585 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A,
586 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B,
587 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C,
588 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D,
589 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440,
590 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441,
591 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442,
592 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443,
593 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444,
594 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445,
595 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446,
596 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447,
597 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448,
598 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449,
599 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A,
600 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B,
601 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C,
602 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D,
603 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460,
604 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461,
605 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462,
606 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463,
607 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464,
608 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465,
609 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466,
610 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467,
611 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468,
612 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469,
613 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A,
614 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B,
615 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C,
616 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D,
622 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
624 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),
699 RTW89_NSS_1 = 0,
709 RTW89_1TX = 0,
715 RTW89_NONBF = 0,
721 RTW89_NON_OFDMA = 0,
727 RTW89_WW = 0,
747 RTW89_REG_6GHZ_POWER_VLP = 0,
764 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
818 RTW89_MAC_0 = 0,
824 RTW89_PHY_0 = 0,
830 RTW89_SUB_ENTITY_0 = 0,
838 RF_PATH_A = 0,
856 RF_A = BIT(0),
877 RTW89_CHANNEL_WIDTH_20 = 0,
892 RTW89_PS_MODE_NONE = 0,
905 RTW89_PE_DURATION_0 = 0,
912 RTW89_RU26 = 0,
921 RTW89_SC_DONT_CARE = 0,
1194 BTC_NCNT_POWER_ON = 0x0,
1219 BTC_BTINFO_L0 = 0,
1231 BTC_DCNT_RUN = 0x0,
1259 BTC_WCNT_SCANAP = 0x0,
1280 BTC_BCNT_RETRY = 0x0,
1306 BTC_BT_NOPROFILE = 0,
1307 BTC_BT_HFP = BIT(0),
1329 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */
1332 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */
1410 u8 rssi; /* 0%~110% (dBm = rssi -110) */
1664 u8 active; /* 0:rlink is under doze */
1764 u8 type; /* 0: none, 1:zigbee, 2:LTE */
1879 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */
1880 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */
1940 BTC_SCAN_INQ = 0,
1950 CXSCAN_BG = 0,
1956 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0)
2068 BTC_BCNT_RFK_REQ = 0,
2082 BTC_BCNT_RFK_REQ_V105 = 0,
2229 CXECTL_OFF = 0x0, /* tdma off */
2230 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
2231 CXECTL_EXT = 0x2,
2242 CXST_OFF = 0x0,
2243 CXST_B2W = 0x1,
2244 CXST_W1 = 0x2,
2245 CXST_W2 = 0x3,
2246 CXST_W2B = 0x4,
2247 CXST_B1 = 0x5,
2248 CXST_B2 = 0x6,
2249 CXST_B3 = 0x7,
2250 CXST_B4 = 0x8,
2251 CXST_LK = 0x9,
2252 CXST_BLK = 0xa,
2253 CXST_E2G = 0xb,
2254 CXST_E5G = 0xc,
2255 CXST_EBT = 0xd,
2256 CXST_ENULL = 0xe,
2257 CXST_WLK = 0xf,
2258 CXST_W1FDD = 0x10,
2259 CXST_B1FDD = 0x11,
2260 CXST_MAX = 0x12,
2264 CXEVNT_TDMA_ENTRY = 0x0,
2294 CXBCN_ALL = 0x0,
2302 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
2303 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
2308 CXT_BT = 0x0,
2309 CXT_WL = 0x1,
2314 CXT_FLCTRL_OFF = 0x0,
2315 CXT_FLCTRL_ON = 0x1,
2320 CXSTEP_NONE = 0x0,
2321 CXSTEP_EVNT = 0x1,
2322 CXSTEP_SLOT = 0x2,
2327 RPT_BT_AFH_SEQ_LEGACY = 0x10,
2328 RPT_BT_AFH_SEQ_LE = 0x20
2337 __le32 pre_state; /* the debug signal is 1 or 0 */
2419 __le16 cxtbl_l16; /* coex table [15:0] */
2556 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)
2563 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2568 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2570 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2574 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)
2581 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2586 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2588 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2596 u8 state_phase; /* [0:3] train state, [4:7] train phase */
2704 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2705 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2706 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
2713 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2714 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2715 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
2739 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2750 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2801 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
2803 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2815 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2886 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */
2917 BTF_EVNT_RPT = 0,
2929 BTC_RPT_TYPE_CTRL = 0x0,
2950 REG_MAC = 0x0,
2951 REG_BB = 0x1,
2952 REG_RF = 0x2,
2953 REG_BT_RF = 0x3,
2954 REG_BT_MODEM = 0x4,
2955 REG_BT_BLUEWIZE = 0x5,
2956 REG_BT_VENDOR = 0x6,
2957 REG_BT_LE = 0x7,
3036 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
3126 RTW89_BTC_HMSG_TMR_EN = 0x0,
3127 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1,
3128 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2,
3129 RTW89_BTC_HMSG_FW_EV = 0x3,
3130 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4,
3131 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5,
3137 RTW89_RA_MODE_CCK = BIT(0),
3155 RTW89_DIG_NOISY_LEVEL1 = 0,
3162 RTW89_GILTF_LGI_4XHE32 = 0,
3172 RTW89_RX_TYPE_MGNT = 0,
3179 RTW89_EFUSE_BLOCK_SYS = 0,
3618 RTW89_DMA_ACH0 = 0,
3638 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1),
3639 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2),
3642 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1),
3643 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2),
3645 DBCC_LEGACY = 0xffffffff,
3700 #define grp_0 0
3909 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0
4294 RTW89_HCIFC_POH = 0,
4312 RTW89_RPR_MODE_POH = 0,
4438 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF,
4439 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF,
4686 RTW89_RFK_STATE_START = 0x0,
4687 RTW89_RFK_STATE_OK = 0x1,
4688 RTW89_RFK_STATE_FAIL = 0x2,
4689 RTW89_RFK_STATE_TIMEOUT = 0x3,
4690 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4,
4862 RTW89_PKT_BASED_AVG_MODE = 0,
4868 RTW89_PHY_DCFO_STATE_NORMAL = 0,
4875 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
4912 RTW89_TSSI_NORMAL = 0,
4917 TSSI_ALIMK_2G = 0,
4982 RTW89_IFS_CLM_INIT = 0,
4992 RTW89_RAC_RELEASE = 0,
5015 RTW89_CCX_EDCCA_SEG0_P0 = 0,
5026 RTW89_CCX_EDCCA_BW20_0 = 0,
5098 RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
5105 RTW89_LAST_RPWM_PS = 0x0,
5106 RTW89_LAST_RPWM_ACTIVE = 0x6,
5135 RTW89_BB_GAIN_BAND_2G = 0,
5148 RTW89_BB_GAIN_BAND_2G_BE = 0,
5165 RTW89_BB_BW_20_40 = 0,
5180 RTW89_CMAC_BW_20M = 0,
5190 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
5191 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
5192 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
5235 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
5238 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
5639 int ret = 0;
5654 int ret = 0;
5805 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
5818 mask &= 0xffff;
5832 mask &= 0xff;
5981 case 0 ... 36:
6224 return 0x10;
6267 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx);
6363 return 0;