Lines Matching defs:wl
1936 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/
2090 struct rtw89_btc_wl_info wl;
2552 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
2553 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
2554 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2578 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2579 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2580 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2584 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2585 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2703 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2727 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2754 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
3663 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
6847 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
6851 chip->ops->cfg_ctrl_path(rtwdev, wl);