Lines Matching full:dm
774 struct rtw89_btc_dm *dm = &btc->dm;
779 dm->error.map.h2c_buffer_over = true;
834 memset(&btc->dm, 0, sizeof(btc->dm));
845 btc->dm.tdma_now = t_def[CXTD_OFF];
846 btc->dm.tdma = t_def[CXTD_OFF];
849 btc->dm.slot.v7[i].dur = s_def[i].dur;
850 btc->dm.slot.v7[i].cxtype = s_def[i].cxtype;
851 btc->dm.slot.v7[i].cxtbl = s_def[i].cxtbl;
853 memcpy(&btc->dm.slot_now.v7, &btc->dm.slot.v7,
854 sizeof(btc->dm.slot_now.v7));
856 memcpy(&btc->dm.slot_now.v1, s_def,
857 sizeof(btc->dm.slot_now.v1));
858 memcpy(&btc->dm.slot.v1, s_def,
859 sizeof(btc->dm.slot.v1));
865 btc->dm.coex_info_map = BTC_COEX_INFO_ALL;
866 btc->dm.wl_tx_limit.tx_time = BTC_MAX_TX_TIME_DEF;
867 btc->dm.wl_tx_limit.tx_retry = BTC_MAX_TX_RETRY_DEF;
868 btc->dm.wl_pre_agc_rb = BTC_PREAGC_NOTFOUND;
869 btc->dm.wl_btg_rx_rb = BTC_BTGCTRL_BB_GNT_NOTFOUND;
993 struct rtw89_btc_dm *dm = &btc->dm;
1004 dm->error.map.wl_ver_mismatch = true;
1007 dm->error.map.wl_ver_mismatch = false;
1011 if (dm->cnt_dm[BTC_DCNT_RPT] == cnt && btc->fwinfo.rpt_en_map)
1012 dm->cnt_dm[BTC_DCNT_RPT_HANG]++;
1014 dm->cnt_dm[BTC_DCNT_RPT_HANG] = 0;
1016 if (dm->cnt_dm[BTC_DCNT_RPT_HANG] >= BTC_CHK_HANG_MAX)
1017 dm->error.map.wl_fw_hang = true;
1019 dm->error.map.wl_fw_hang = false;
1021 dm->cnt_dm[BTC_DCNT_RPT] = cnt;
1024 if (dm->cnt_dm[BTC_DCNT_CYCLE] == cnt &&
1025 (dm->tdma_now.type != CXTDMA_OFF ||
1026 dm->tdma_now.ext_ctrl == CXECTL_EXT))
1027 dm->cnt_dm[BTC_DCNT_CYCLE_HANG]++;
1029 dm->cnt_dm[BTC_DCNT_CYCLE_HANG] = 0;
1031 if (dm->cnt_dm[BTC_DCNT_CYCLE_HANG] >= BTC_CHK_HANG_MAX)
1032 dm->error.map.cycle_hang = true;
1034 dm->error.map.cycle_hang = false;
1036 dm->cnt_dm[BTC_DCNT_CYCLE] = cnt;
1039 if (dm->cnt_dm[BTC_DCNT_W1] == cnt &&
1040 dm->tdma_now.type != CXTDMA_OFF)
1041 dm->cnt_dm[BTC_DCNT_W1_HANG]++;
1043 dm->cnt_dm[BTC_DCNT_W1_HANG] = 0;
1045 if (dm->cnt_dm[BTC_DCNT_W1_HANG] >= BTC_CHK_HANG_MAX)
1046 dm->error.map.w1_hang = true;
1048 dm->error.map.w1_hang = false;
1050 dm->cnt_dm[BTC_DCNT_W1] = cnt;
1053 if (dm->cnt_dm[BTC_DCNT_B1] == cnt &&
1054 dm->tdma_now.type != CXTDMA_OFF)
1055 dm->cnt_dm[BTC_DCNT_B1_HANG]++;
1057 dm->cnt_dm[BTC_DCNT_B1_HANG] = 0;
1059 if (dm->cnt_dm[BTC_DCNT_B1_HANG] >= BTC_CHK_HANG_MAX)
1060 dm->error.map.b1_hang = true;
1062 dm->error.map.b1_hang = false;
1064 dm->cnt_dm[BTC_DCNT_B1] = cnt;
1067 if (dm->cnt_dm[BTC_DCNT_E2G] == cnt &&
1068 dm->tdma_now.ext_ctrl == CXECTL_EXT)
1069 dm->cnt_dm[BTC_DCNT_E2G_HANG]++;
1071 dm->cnt_dm[BTC_DCNT_E2G_HANG] = 0;
1073 if (dm->cnt_dm[BTC_DCNT_E2G_HANG] >= BTC_CHK_HANG_MAX)
1074 dm->error.map.wl_e2g_hang = true;
1076 dm->error.map.wl_e2g_hang = false;
1078 dm->cnt_dm[BTC_DCNT_E2G] = cnt;
1082 dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC]++;
1084 dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC] = 0;
1086 if (dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC] >= BTC_CHK_HANG_MAX)
1087 dm->error.map.tdma_no_sync = true;
1089 dm->error.map.tdma_no_sync = false;
1093 dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC]++;
1095 dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC] = 0;
1097 if (dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC] >= BTC_CHK_HANG_MAX)
1098 dm->error.map.slot_no_sync = true;
1100 dm->error.map.slot_no_sync = false;
1106 dm->cnt_dm[BTC_DCNT_BTTX_HANG]++;
1108 dm->cnt_dm[BTC_DCNT_BTTX_HANG] = 0;
1110 if (dm->cnt_dm[BTC_DCNT_BTTX_HANG] >= BTC_CHK_HANG_MAX)
1111 dm->error.map.bt_tx_hang = true;
1113 dm->error.map.bt_tx_hang = false;
1122 dm->cnt_dm[BTC_DCNT_BTCNT_HANG]++;
1124 dm->cnt_dm[BTC_DCNT_BTCNT_HANG] = 0;
1126 if ((dm->cnt_dm[BTC_DCNT_BTCNT_HANG] >= BTC_CHK_HANG_MAX &&
1127 bt->enable.now) || (!dm->cnt_dm[BTC_DCNT_BTCNT_HANG] &&
1133 dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT]++;
1135 dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT] = 0;
1137 if (dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT] >= BTC_CHK_HANG_MAX)
1138 dm->error.map.wl_slot_drift = true;
1140 dm->error.map.wl_slot_drift = false;
1144 dm->cnt_dm[BTC_DCNT_BT_SLOT_DRIFT]++;
1146 dm->cnt_dm[BTC_DCNT_BT_SLOT_DRIFT] = 0;
1148 if (dm->cnt_dm[BTC_DCNT_BT_SLOT_DRIFT] >= BTC_CHK_HANG_MAX)
1149 dm->error.map.bt_slot_drift = true;
1151 dm->error.map.bt_slot_drift = false;
1298 struct rtw89_btc_dm *dm = &btc->dm;
1557 dm->wl_fw_cx_offload = !!prpt->v1.wl_fw_cx_offload;
1577 dm->wl_fw_cx_offload = !!le32_to_cpu(prpt->v4.wl_fw_info.cx_offload);
1580 memcpy(&dm->gnt.band[i], &prpt->v4.gnt_val[i],
1581 sizeof(dm->gnt.band[i]));
1603 dm->error.map.bt_rfk_timeout = bt->rfk_info.map.timeout;
1609 dm->wl_fw_cx_offload = 0;
1612 memcpy(&dm->gnt.band[i], &prpt->v5.gnt_val[i][0],
1613 sizeof(dm->gnt.band[i]));
1630 dm->error.map.bt_rfk_timeout = bt->rfk_info.map.timeout;
1636 dm->wl_fw_cx_offload = 0;
1639 memcpy(&dm->gnt.band[i], &prpt->v105.gnt_val[i][0],
1640 sizeof(dm->gnt.band[i]));
1657 dm->error.map.bt_rfk_timeout = bt->rfk_info.map.timeout;
1665 memcpy(&dm->gnt.band[i], &prpt->v8.gnt_val[i][0],
1666 sizeof(dm->gnt.band[i]));
1688 dm->error.map.h2c_c2h_buffer_mismatch = true;
1690 dm->error.map.h2c_c2h_buffer_mismatch = false;
1704 sizeof(dm->tdma_now));
1707 memcmp(&dm->tdma_now,
1709 sizeof(dm->tdma_now)));
1712 memcmp(&dm->tdma_now,
1714 sizeof(dm->tdma_now)));
1723 sizeof(dm->slot_now.v7));
1725 memcmp(dm->slot_now.v7,
1727 sizeof(dm->slot_now.v7)));
1732 sizeof(dm->slot_now.v1));
1734 memcmp(dm->slot_now.v1,
1736 sizeof(dm->slot_now.v1)));
1745 le32_to_cpu(pcysta->v2.leakrx_cnt) != 0 && dm->tdma_now.rxflctrl) {
1748 dm->leak_ap = 1;
1752 if (dm->tdma_now.type == CXTDMA_OFF &&
1753 dm->tdma_now.ext_ctrl == CXECTL_EXT) {
1755 wl_slot_set = le16_to_cpu(dm->slot_now.v1[CXST_E2G].dur);
1757 wl_slot_set = le16_to_cpu(dm->slot_now.v7[CXST_E2G].dur);
1760 wl_slot_set = le16_to_cpu(dm->slot_now.v1[CXST_W1].dur);
1762 wl_slot_set = le16_to_cpu(dm->slot_now.v7[CXST_W1].dur);
1786 dm->tdma_now.rxflctrl) {
1788 dm->leak_ap = 1;
1792 if (dm->tdma_now.type == CXTDMA_OFF) {
1794 wl_slot_set = le16_to_cpu(dm->slot_now.v1[CXST_W1].dur);
1796 wl_slot_set = le16_to_cpu(dm->slot_now.v7[CXST_W1].dur);
1805 if (dm->tdma_now.type == CXTDMA_OFF &&
1806 dm->tdma_now.ext_ctrl == CXECTL_EXT &&
1830 dm->tdma_now.rxflctrl) {
1832 dm->leak_ap = 1;
1836 if (dm->tdma_now.type == CXTDMA_OFF) {
1838 wl_slot_set = le16_to_cpu(dm->slot_now.v1[CXST_W1].dur);
1840 wl_slot_set = le16_to_cpu(dm->slot_now.v7[CXST_W1].dur);
1849 if (dm->tdma_now.type == CXTDMA_OFF &&
1850 dm->tdma_now.ext_ctrl == CXECTL_EXT &&
1867 if (dm->fddt_train == BTC_FDDT_ENABLE)
1874 dm->tdma_now.rxflctrl) {
1877 dm->leak_ap = 1;
1881 if (dm->tdma_now.type == CXTDMA_OFF) {
1883 wl_slot_set = le16_to_cpu(dm->slot_now.v1[CXST_W1].dur);
1885 wl_slot_set = le16_to_cpu(dm->slot_now.v7[CXST_W1].dur);
1899 if (dm->tdma_now.type == CXTDMA_OFF &&
1900 dm->tdma_now.ext_ctrl == CXECTL_EXT &&
1918 if (dm->fddt_train == BTC_FDDT_ENABLE)
1923 if (dm->tdma_now.type != CXTDMA_OFF) {
1934 if (dm->tdma_now.rxflctrl &&
1936 dm->leak_ap = 1;
1937 } else if (dm->tdma_now.ext_ctrl == CXECTL_EXT) {
1949 dm->slot_req_more = 1;
1951 dm->slot_req_more = 0;
1974 if (dm->wl_btg_rx == BTC_BTGCTRL_BB_GNT_FWCTRL)
1975 dm->wl_btg_rx_rb = BTC_BTGCTRL_BB_GNT_FWCTRL;
1977 dm->wl_btg_rx_rb = val;
1980 if (dm->wl_pre_agc == BTC_PREAGC_BB_FWCTRL)
1981 dm->wl_pre_agc_rb = BTC_PREAGC_BB_FWCTRL;
1983 dm->wl_pre_agc_rb = val;
2035 struct rtw89_btc_dm *dm = &btc->dm;
2043 !memcmp(&dm->tdma, &dm->tdma_now, sizeof(dm->tdma))) {
2055 *v = dm->tdma;
2059 tlv_v7->len = sizeof(dm->tdma);
2062 memcpy(tlv_v7->val, &dm->tdma, tlv_v7->len);
2068 v3->tdma = dm->tdma;
2074 __func__, dm->tdma.type, dm->tdma.rxflctrl,
2075 dm->tdma.txpause, dm->tdma.wtgle_n, dm->tdma.leak_n,
2076 dm->tdma.ext_ctrl);
2082 struct rtw89_btc_dm *dm = &btc->dm;
2094 !memcmp(&dm->slot.v1[i], &dm->slot_now.v1[i],
2095 sizeof(dm->slot.v1[i])))
2107 v->slot = dm->slot.v1[i];
2111 __func__, i, dm->slot.v1[i].dur, dm->slot.v1[i].cxtbl,
2112 dm->slot.v1[i].cxtype);
2128 struct rtw89_btc_dm *dm = &btc->dm;
2134 !memcmp(&dm->slot.v7[i], &dm->slot_now.v7[i],
2135 sizeof(dm->slot.v7[i])))
2150 tlv->len = sizeof(dm->slot.v7[0]) + BTC_TLV_SLOT_ID_LEN_V7;
2161 memcpy(&btc->policy[len + 1], &dm->slot.v7[i],
2162 sizeof(dm->slot.v7[0]));
2167 __func__, btc->policy_len, i, dm->slot.v7[i].dur,
2168 dm->slot.v7[i].cxtype, dm->slot.v7[i].cxtbl);
2340 struct rtw89_btc_dm *dm = &btc->dm;
2344 len = sizeof(*tlv_v7) + sizeof(dm->slot.v7);
2351 tlv_v7->len = ARRAY_SIZE(dm->slot.v7);
2352 memcpy(tlv_v7->val, dm->slot.v7, sizeof(dm->slot.v7));
2365 memcpy(tbl->tbls, dm->slot.v1, flex_array_size(tbl, tbls, CXST_MAX));
2485 struct rtw89_btc_dm *dm = &btc->dm;
2487 /* use ring-structure to store dm step */
2488 dm->dm_step.step[dm->dm_step.step_pos] = reason_or_action;
2489 dm->dm_step.step_pos++;
2491 if (dm->dm_step.step_pos >= ARRAY_SIZE(dm->dm_step.step)) {
2492 dm->dm_step.step_pos = 0;
2493 dm->dm_step.step_ov = true;
2501 struct rtw89_btc_dm *dm = &btc->dm;
2504 dm->run_action = action;
2522 if (dm->tdma.rxflctrl == CXFLC_NULLP ||
2523 dm->tdma.rxflctrl == CXFLC_QOSNULL)
2534 memcpy(&dm->tdma_now, &dm->tdma, sizeof(dm->tdma_now));
2536 memcpy(&dm->slot_now.v7, &dm->slot.v7, sizeof(dm->slot_now.v7));
2538 memcpy(&dm->slot_now.v1, &dm->slot.v1, sizeof(dm->slot_now.v1));
2552 struct rtw89_btc_dm *dm = &btc->dm;
2554 struct rtw89_btc_rf_trx_para rf_para = dm->rf_trx_para;
2584 dm->trx_info.tx_power = u32_get_bits(rf_para.wl_tx_power,
2586 dm->trx_info.rx_gain = u32_get_bits(rf_para.wl_rx_gain,
2588 dm->trx_info.bt_tx_power = u32_get_bits(rf_para.bt_tx_power,
2590 dm->trx_info.bt_rx_gain = u32_get_bits(rf_para.bt_rx_gain,
2592 dm->trx_info.cn = wl->cn_report;
2593 dm->trx_info.nhm = wl->nhm.pwr;
2636 struct rtw89_btc_dm *dm = &btc->dm;
2637 struct rtw89_mac_ax_gnt *g = dm->gnt.band;
2678 rtw89_chip_mac_cfg_gnt(rtwdev, &dm->gnt);
2685 struct rtw89_btc_dm *dm = &btc->dm;
2686 struct rtw89_mac_ax_gnt *g = dm->gnt.band;
2687 u8 i, bt_idx = dm->bt_select + 1;
2734 dm->gnt.bt[i].wlan_act_en = 0;
2735 dm->gnt.bt[i].wlan_act = 0;
2738 dm->gnt.bt[i].wlan_act_en = 1;
2739 dm->gnt.bt[i].wlan_act = 0;
2742 dm->gnt.bt[i].wlan_act_en = 1;
2743 dm->gnt.bt[i].wlan_act = 1;
2748 rtw89_mac_cfg_gnt_v2(rtwdev, &dm->gnt);
2781 btc->dm.rf_trx_para.wl_tx_power = level;
2812 btc->dm.rf_trx_para.wl_rx_gain = level;
2842 btc->dm.rf_trx_para.bt_tx_power = level;
2862 btc->dm.rf_trx_para.bt_rx_gain = level;
2881 struct rtw89_btc_dm *dm = &btc->dm;
2907 if ((btc->dm.wl_btg_rx && b->profile_cnt.now != 0) ||
2908 dm->bt_only == 1)
2909 dm->trx_para_level = 1; /* for better BT ACI issue */
2911 dm->trx_para_level = 0;
2913 dm->trx_para_level = 5;
2919 dm->trx_para_level = 6;
2921 dm->trx_para_level = 7;
2925 level_id = dm->trx_para_level;
2939 if (dm->fddt_train) {
2949 if (!bt->enable.now || dm->wl_only || wl_smap->rf_off ||
2958 if (wl_stb_chg != dm->wl_stb_chg) {
2959 dm->wl_stb_chg = wl_stb_chg;
2960 chip->ops->btc_wl_s1_standby(rtwdev, dm->wl_stb_chg);
3171 btc->dm.trx_para_level = 0;
3177 btc->dm.trx_para_level = 5;
3182 btc->dm.trx_para_level = 5;
3187 btc->dm.trx_para_level = 5;
3193 btc->dm.trx_para_level = 5;
3198 btc->dm.trx_para_level = 5;
3201 btc->dm.trx_para_level = 0;
3205 btc->dm.trx_para_level = 6;
3208 btc->dm.trx_para_level = 7;
3211 btc->dm.trx_para_level = 0;
3215 btc->dm.trx_para_level = 6;
3220 btc->dm.trx_para_level = 0;
3224 #define _tdma_set_flctrl(btc, flc) ({(btc)->dm.tdma.rxflctrl = flc; })
3225 #define _tdma_set_flctrl_role(btc, role) ({(btc)->dm.tdma.rxflctrl_role = role; })
3226 #define _tdma_set_tog(btc, wtg) ({(btc)->dm.tdma.wtgle_n = wtg; })
3227 #define _tdma_set_lek(btc, lek) ({(btc)->dm.tdma.leak_n = lek; })
3301 struct rtw89_btc_dm *dm = &btc->dm;
3302 struct rtw89_btc_fbtc_tdma *t = &dm->tdma;
3303 struct rtw89_btc_fbtc_slot *s = dm->slot.v1;
3443 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1],
3445 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1],
3500 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1],
3502 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1],
3524 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1],
3526 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1],
3561 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1],
3563 _slot_set(btc, CXST_B4, dm->slot_dur[CXST_B4],
3598 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1],
3600 _slot_set(btc, CXST_B4, dm->slot_dur[CXST_B4],
3612 struct rtw89_btc_dm *dm = &btc->dm;
3613 struct rtw89_btc_fbtc_tdma *t = &dm->tdma;
3632 if (dm->leak_ap &&
3731 dur_2 = dm->e2g_slot_limit;
3830 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1],
3832 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1],
3869 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1],
3871 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1],
3896 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1],
3898 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1],
3923 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1],
3925 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1],
3963 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1],
3965 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1],
3967 _slot_set(btc, CXST_B4, dm->slot_dur[CXST_B4],
4005 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1],
4007 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1],
4009 _slot_set(btc, CXST_B4, dm->slot_dur[CXST_B4],
4018 if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC && dm->tdma.rxflctrl) {
4019 null_role = FIELD_PREP(0x0f, dm->wl_scc.null_role1) |
4020 FIELD_PREP(0xf0, dm->wl_scc.null_role2);
4025 if (dm->leak_ap && dm->tdma.leak_n > 1)
4028 if (dm->tdma_instant_excute) {
4029 btc->dm.tdma.option_ctrl |= BIT(0);
4070 struct rtw89_btc_dm *dm = &btc->dm;
4088 if (btc->dm.run_reason == BTC_RSN_NTFY_POWEROFF ||
4089 btc->dm.run_reason == BTC_RSN_NTFY_RADIO_STATE ||
4090 btc->dm.run_reason == BTC_RSN_CMD_SET_COEX || dbcc_chg)
4093 if (!force_exec && ant_path_type == dm->set_ant_path) {
4102 } else if (btc->dm.run_reason != BTC_RSN_NTFY_WL_RFK &&
4109 dm->set_ant_path = ant_path_type;
4114 __func__, phy_map, dm->set_ant_path & 0xff);
4202 struct rtw89_btc_dm *dm = &btc->dm;
4205 if (btc->dm.run_reason == BTC_RSN_NTFY_POWEROFF ||
4206 btc->dm.run_reason == BTC_RSN_NTFY_RADIO_STATE ||
4207 btc->dm.run_reason == BTC_RSN_CMD_SET_COEX || wl_rinfo->dbcc_chg)
4211 btc->dm.wl_btg_rx == 2)
4214 if (!force_exec && ant_path_type == dm->set_ant_path) {
4223 } else if (btc->dm.run_reason != BTC_RSN_NTFY_WL_RFK &&
4230 dm->set_ant_path = ant_path_type;
4234 __func__, phy_map, dm->set_ant_path & 0xff);
4325 if (wl->status.map.rf_off || btc->dm.bt_only) {
4355 btc->dm.freerun = true;
4485 struct rtw89_btc_dm *dm = &btc->dm;
4491 if (a2dp.vendor_id == 0x4c || dm->leak_ap) {
4492 dm->slot_dur[CXST_W1] = 40;
4493 dm->slot_dur[CXST_B1] = 200;
4509 if (a2dp.vendor_id == 0x4c || dm->leak_ap) {
4510 dm->slot_dur[CXST_W1] = 40;
4511 dm->slot_dur[CXST_B1] = 200;
4586 struct rtw89_btc_dm *dm = &btc->dm;
4593 if (a2dp.vendor_id == 0x4c || dm->leak_ap) {
4594 dm->slot_dur[CXST_W1] = 40;
4595 dm->slot_dur[CXST_B1] = 200;
4612 if (a2dp.vendor_id == 0x4c || dm->leak_ap) {
4613 dm->slot_dur[CXST_W1] = 40;
4614 dm->slot_dur[CXST_B1] = 200;
4763 struct rtw89_btc_dm *dm = &btc->dm;
4765 u32 run_reason = btc->dm.run_reason;
4806 else if (dm->freerun)
4813 if (dm->wl_btg_rx_rb != dm->wl_btg_rx &&
4814 dm->wl_btg_rx_rb != BTC_BTGCTRL_BB_GNT_NOTFOUND) {
4816 dm->wl_btg_rx_rb = val;
4821 dm->wl_btg_rx_rb != dm->wl_btg_rx ||
4822 is_btg != dm->wl_btg_rx) {
4824 dm->wl_btg_rx = is_btg;
4842 struct rtw89_btc_dm *dm = &btc->dm;
4857 else if (dm->tdma_now.type != CXTDMA_OFF &&
4860 dm->fddt_train == BTC_FDDT_DISABLE)
4870 if (dm->wl_pre_agc_rb != dm->wl_pre_agc &&
4871 dm->wl_pre_agc_rb != BTC_PREAGC_NOTFOUND) {
4873 dm->wl_pre_agc_rb = val;
4877 (dm->run_reason == BTC_RSN_NTFY_INIT ||
4878 dm->run_reason == BTC_RSN_NTFY_SWBAND ||
4879 dm->wl_pre_agc_rb != dm->wl_pre_agc)) ||
4880 is_preagc != dm->wl_pre_agc) {
4881 dm->wl_pre_agc = is_preagc;
4885 chip->ops->ctrl_nbtg_bt_tx(rtwdev, dm->wl_pre_agc, RTW89_PHY_0);
4962 struct rtw89_btc_dm *dm = &btc->dm;
4997 if (btc->dm.freerun || igno_bt || b->profile_cnt.now == 0 ||
5016 if (dm->wl_tx_limit.enable == enable &&
5017 dm->wl_tx_limit.tx_time == tx_time &&
5018 dm->wl_tx_limit.tx_retry == tx_retry)
5021 if (!dm->wl_tx_limit.enable && enable)
5024 dm->wl_tx_limit.enable = enable;
5025 dm->wl_tx_limit.tx_time = tx_time;
5026 dm->wl_tx_limit.tx_retry = tx_retry;
5062 if (mode != BTC_WLINK_NOLINK && btc->dm.wl_btg_rx)
5085 struct rtw89_btc_dm *dm = &btc->dm;
5105 if (dm->run_reason == BTC_RSN_NTFY_INIT ||
5106 dm->run_reason == BTC_RSN_NTFY_RADIO_STATE ||
5107 dm->run_reason == BTC_RSN_NTFY_POWEROFF) {
5123 btc->dm.tdma_instant_excute = 0;
5230 btc->dm.e2g_slot_limit = BTC_E2G_LIMIT_DEF;
5299 struct rtw89_btc_dm *dm = &btc->dm;
5310 dm->wl_scc.null_role1 = RTW89_WIFI_ROLE_STATION;
5311 dm->wl_scc.null_role2 = RTW89_WIFI_ROLE_P2P_CLIENT;
5312 dm->wl_scc.ebt_null = 0; /* no ext-slot-control */
5316 dm->wl_scc.null_role1 = RTW89_WIFI_ROLE_STATION;
5317 dm->wl_scc.null_role2 = RTW89_WIFI_ROLE_STATION;
5318 dm->wl_scc.ebt_null = 0; /* no ext-slot-control */
5324 dm->wl_scc.null_role1 = RTW89_WIFI_ROLE_STATION;
5325 dm->wl_scc.null_role2 = RTW89_WIFI_ROLE_NONE;
5329 dm->wl_scc.ebt_null = 0;
5332 dm->wl_scc.ebt_null = 0;
5336 dm->wl_scc.ebt_null = 1; /* tx null at EBT */
5340 dm->wl_scc.ebt_null = 1; /* tx null at EBT */
5343 dm->wl_scc.ebt_null = 0;
5361 struct rtw89_btc_dm *dm = &btc->dm;
5372 dm->wl_scc.null_role1 = RTW89_WIFI_ROLE_STATION;
5373 dm->wl_scc.null_role2 = RTW89_WIFI_ROLE_P2P_CLIENT;
5374 dm->wl_scc.ebt_null = 0; /* no ext-slot-control */
5378 dm->wl_scc.null_role1 = RTW89_WIFI_ROLE_STATION;
5379 dm->wl_scc.null_role2 = RTW89_WIFI_ROLE_STATION;
5380 dm->wl_scc.ebt_null = 0; /* no ext-slot-control */
5386 dm->wl_scc.null_role1 = RTW89_WIFI_ROLE_STATION;
5387 dm->wl_scc.null_role2 = RTW89_WIFI_ROLE_NONE;
5391 dm->wl_scc.ebt_null = 0;
5394 dm->wl_scc.ebt_null = 0;
5398 dm->wl_scc.ebt_null = 1; /* tx null at EBT */
5402 dm->wl_scc.ebt_null = 1; /* tx null at EBT */
5405 dm->wl_scc.ebt_null = 0;
5423 struct rtw89_btc_dm *dm = &btc->dm;
5437 dm->e2g_slot_limit = BTC_E2G_LIMIT_DEF;
6206 btc->dm.leak_ap = 0;
6346 struct rtw89_btc_dm *dm = &rtwdev->btc.dm;
6352 dm->cnt_notify[BTC_NCNT_TIMER]++;
6367 struct rtw89_btc_dm *dm = &rtwdev->btc.dm;
6372 dm->cnt_notify[BTC_NCNT_TIMER]++;
6383 struct rtw89_btc_dm *dm = &rtwdev->btc.dm;
6389 dm->cnt_notify[BTC_NCNT_TIMER]++;
6394 dm->error.map.wl_rfk_timeout = true;
6492 struct rtw89_btc_dm *dm = &rtwdev->btc.dm;
6504 dm->run_reason = reason;
6530 __func__, dm->wl_only, dm->bt_only);
6544 "[BTC], %s(): return for Stop Coex DM!!\n",
6574 dm->freerun = false;
6575 dm->cnt_dm[BTC_DCNT_RUN]++;
6576 dm->fddt_train = BTC_FDDT_DISABLE;
6586 if (dm->wl_only) {
6592 if (wl->status.map.rf_off || wl->status.map.lps || dm->bt_only) {
6698 btc->dm.cnt_notify[BTC_NCNT_POWER_ON]++;
6707 btc->dm.cnt_notify[BTC_NCNT_POWER_OFF]++;
6726 struct rtw89_btc_dm *dm = &btc->dm;
6730 dm->init_info.init_v7.wl_only = (u8)dm->wl_only;
6731 dm->init_info.init_v7.bt_only = (u8)dm->bt_only;
6732 dm->init_info.init_v7.wl_init_ok = (u8)wl->status.map.init_ok;
6733 dm->init_info.init_v7.cx_other = btc->cx.other.type;
6734 dm->init_info.init_v7.wl_guard_ch = chip->afh_guard_ch;
6735 dm->init_info.init_v7.module = btc->mdinfo.md_v7;
6737 dm->init_info.init.wl_only = (u8)dm->wl_only;
6738 dm->init_info.init.bt_only = (u8)dm->bt_only;
6739 dm->init_info.init.wl_init_ok = (u8)wl->status.map.init_ok;
6740 dm->init_info.init.dbcc_en = rtwdev->dbcc_en;
6741 dm->init_info.init.cx_other = btc->cx.other.type;
6742 dm->init_info.init.wl_guard_ch = chip->afh_guard_ch;
6743 dm->init_info.init.module = btc->mdinfo.md;
6750 struct rtw89_btc_dm *dm = &rtwdev->btc.dm;
6756 btc->dm.run_reason = BTC_RSN_NONE;
6757 btc->dm.run_action = BTC_ACT_NONE;
6767 dm->cnt_notify[BTC_NCNT_INIT_COEX]++;
6768 dm->wl_only = mode == BTC_MODE_WL ? 1 : 0;
6769 dm->bt_only = mode == BTC_MODE_BT ? 1 : 0;
6779 dm->error.map.init = true;
6790 dm->error.map.pta_owner = true;
6815 btc->dm.cnt_notify[BTC_NCNT_SCAN_START]++;
6837 btc->dm.cnt_notify[BTC_NCNT_SCAN_FINISH]++;
6863 btc->dm.cnt_notify[BTC_NCNT_SWITCH_BAND]++;
6937 btc->dm.cnt_notify[BTC_NCNT_SPECIAL_PACKET]++;
7020 if (mode == BTC_WLINK_5G || rtwdev->btc.dm.freerun) {
7089 btc->dm.trx_info.bt_profile = u32_get_bits(btinfo.val, BT_PROFILE_PROTOCOL_MASK);
7107 btc->dm.trx_info.bt_rssi = bt->rssi_level;
7239 btc->dm.cnt_notify[BTC_NCNT_ROLE_INFO]++;
7277 btc->dm.leak_ap = 0;
7299 btc->dm.cnt_notify[BTC_NCNT_RADIO_STATE]++;
7344 btc->dm.cnt_dm[BTC_DCNT_BTCNT_HANG] = 0;
7345 btc->dm.tdma_instant_excute = 1;
7378 btc->dm.cnt_notify[BTC_NCNT_WL_RFK]++;
7415 __func__, btc->dm.cnt_notify[BTC_NCNT_WL_RFK], result);
7471 struct rtw89_btc_dm *dm = &btc->dm;
7560 dm->trx_info.tx_rate = link_info_t->tx_rate;
7561 dm->trx_info.rx_rate = link_info_t->rx_rate;
7577 dm->trx_info.tx_lvl = stats->tx_tfc_lv;
7578 dm->trx_info.rx_lvl = stats->rx_tfc_lv;
7579 dm->trx_info.tx_rate = rtwsta->ra_report.hw_rate;
7580 dm->trx_info.rx_rate = rtwsta->rx_hw_rate;
7583 dm->trx_info.tx_tp = link_info_t->tx_throughput;
7584 dm->trx_info.rx_tp = link_info_t->rx_throughput;
7587 if ((dm->wl_btg_rx_rb != dm->wl_btg_rx &&
7588 dm->wl_btg_rx_rb != BTC_BTGCTRL_BB_GNT_NOTFOUND) ||
7589 (dm->wl_pre_agc_rb != dm->wl_pre_agc &&
7590 dm->wl_pre_agc_rb != BTC_PREAGC_NOTFOUND))
7605 struct rtw89_btc_dm *dm = &btc->dm;
7615 btc->dm.cnt_notify[BTC_NCNT_WL_STA]++;
7624 if (dm->trx_info.wl_rssi != wl->rssi_level)
7625 dm->trx_info.wl_rssi = wl->rssi_level;
7638 } else if (btc->dm.cnt_notify[BTC_NCNT_WL_STA] >=
7639 btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] + BTC_NHM_CHK_INTVL) {
7640 btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] =
7641 btc->dm.cnt_notify[BTC_NCNT_WL_STA];
7642 } else if (btc->dm.cnt_notify[BTC_NCNT_WL_STA] <
7643 btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST]) {
7644 btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] =
7645 btc->dm.cnt_notify[BTC_NCNT_WL_STA];
7696 btc->dm.cnt_dm[BTC_DCNT_CX_RUNINFO]++;
7710 struct rtw89_btc_dm *dm = &btc->dm;
7716 if (!(dm->coex_info_map & BTC_COEX_INFO_CX))
7719 dm->cnt_notify[BTC_NCNT_SHOW_COEX_INFO]++;
7862 if (!(btc->dm.coex_info_map & BTC_COEX_INFO_WL))
7966 if (!(btc->dm.coex_info_map & BTC_COEX_INFO_BT))
8006 " %-15s : rssi:%ddBm(lvl:%d), tx_rate:%dM, %s%s%s",
8424 struct rtw89_btc_dm *dm = &btc->dm;
8428 len = dm->dm_step.step_ov ? RTW89_BTC_DM_MAXSTEP : dm->dm_step.step_pos;
8429 start_idx = dm->dm_step.step_ov ? dm->dm_step.step_pos : 0;
8431 seq_print_segment(m, "[dm_steps]", dm->dm_step.step, len, 6, start_idx,
8432 ARRAY_SIZE(dm->dm_step.step));
8439 struct rtw89_btc_dm *dm = &btc->dm;
8444 if (!(dm->coex_info_map & BTC_COEX_INFO_DM))
8454 steps_to_str(dm->run_reason),
8455 steps_to_str(dm->run_action | BTC_ACT_EXT_BIT),
8456 id_to_ant(FIELD_GET(GENMASK(7, 0), dm->set_ant_path)),
8458 dm->cnt_dm[BTC_DCNT_RUN]);
8468 "[dm_flag]", dm->wl_only, dm->bt_only, igno_bt,
8469 dm->freerun, btc->lps, dm->wl_mimo_ps);
8471 seq_printf(m, "leak_ap:%d, fw_offload:%s%s\n", dm->leak_ap,
8473 (dm->wl_fw_cx_offload == BTC_CX_FW_OFFLOAD ?
8476 if (dm->rf_trx_para.wl_tx_power == 0xff)
8479 "[trx_ctrl]", wl->rssi_level, dm->trx_para_level);
8484 "[trx_ctrl]", wl->rssi_level, dm->trx_para_level,
8485 dm->rf_trx_para.wl_tx_power);
8489 dm->rf_trx_para.wl_rx_gain, dm->rf_trx_para.bt_tx_power,
8490 dm->rf_trx_para.bt_rx_gain,
8491 (bt->hi_lna_rx ? "Hi" : "Ori"), dm->wl_btg_rx);
8495 "[dm_ctrl]", dm->wl_tx_limit.enable, dm->wl_tx_limit.tx_time,
8496 dm->wl_tx_limit.tx_retry, btc->bt_req_len, bt->scan_rx_low_pri);
8603 struct rtw89_btc_dm *dm = &btc->dm;
8610 dur = le16_to_cpu(dm->slot_now.v1[i].dur);
8611 tbl = le32_to_cpu(dm->slot_now.v1[i].cxtbl);
8612 cxtype = le16_to_cpu(dm->slot_now.v1[i].cxtype);
8614 dur = le16_to_cpu(dm->slot_now.v7[i].dur);
8615 tbl = le32_to_cpu(dm->slot_now.v7[i].cxtbl);
8616 cxtype = le16_to_cpu(dm->slot_now.v7[i].cxtype);
8643 struct rtw89_btc_dm *dm = &btc->dm;
8672 if (dm->tdma_now.rxflctrl) {
8745 r.val = dm->tdma_now.rxflctrl;
8772 struct rtw89_btc_dm *dm = &btc->dm;
8801 if (dm->tdma_now.rxflctrl)
8859 seq_printf(m, "(%d/%d/%dM/%d/%d/%d)",
8871 seq_printf(m, "(%d/%d/%dM/%d/%d/%d)",
8902 struct rtw89_btc_dm *dm = &btc->dm;
8931 if (dm->tdma_now.rxflctrl)
8991 seq_printf(m, "(%d/%d/%dM/%d/%d/%d)",
9003 seq_printf(m, "(%d/%d/%dM/%d/%d/%d)",
9034 struct rtw89_btc_dm *dm = &btc->dm;
9063 if (dm->tdma_now.rxflctrl)
9122 seq_printf(m, "(%d/%d/%dM/%d/%d/%d)",
9134 seq_printf(m, "(%d/%d/%dM/%d/%d/%d)",
9166 struct rtw89_btc_dm *dm = &rtwdev->btc.dm;
9187 if (dm->tdma_now.rxflctrl)
9206 dm->bt_slot_flood, dm->cnt_dm[BTC_DCNT_BT_SLOT_FLOOD],
9263 seq_printf(m, "(%d/%d/%d/%dM/%d/%d/%d)",
9277 seq_printf(m, "(%d/%d/%d/%dM/%d/%d/%d)",
9299 if (!btc->dm.tdma_now.rxflctrl)
9508 if (!(btc->dm.coex_info_map & BTC_COEX_INFO_DM))
9633 if (!(btc->dm.coex_info_map & BTC_COEX_INFO_MREG))
9644 btc->dm.pta_owner = rtw89_mac_get_ctrl_path(rtwdev);
9652 btc->dm.pta_owner == BTC_CTRL_BY_WL ? "WL" : "BT",
9711 if (!(btc->dm.coex_info_map & BTC_COEX_INFO_MREG))
9722 btc->dm.pta_owner = rtw89_mac_get_ctrl_path(rtwdev);
9730 btc->dm.pta_owner == BTC_CTRL_BY_WL ? "WL" : "BT",
9785 struct rtw89_btc_dm *dm = &btc->dm;
9789 if (!(dm->coex_info_map & BTC_COEX_INFO_MREG))
9801 dm->pta_owner = rtw89_mac_get_ctrl_path(rtwdev);
9807 dm->pta_owner == BTC_CTRL_BY_WL ? "WL" : "BT",
9810 gnt = &dm->gnt.band[RTW89_PHY_0];
9817 gnt = &dm->gnt.band[RTW89_PHY_1];
9852 struct rtw89_btc_dm *dm = &btc->dm;
9855 u32 cnt_sum = 0, *cnt = btc->dm.cnt_notify;
9858 if (!(dm->coex_info_map & BTC_COEX_INFO_SUMMARY))
9876 prptctrl->rpt_enable, dm->error.val);
9878 if (dm->error.map.wl_fw_hang)
9912 dm->error.map.wl_rfk_timeout = bt->rfk_info.map.timeout;
9924 cnt_sum += dm->cnt_notify[i];
9956 struct rtw89_btc_dm *dm = &btc->dm;
9959 u32 cnt_sum = 0, *cnt = btc->dm.cnt_notify;
9962 if (!(dm->coex_info_map & BTC_COEX_INFO_SUMMARY))
9984 dm->error.val);
9986 if (dm->error.map.wl_fw_hang)
10024 dm->error.map.wl_rfk_timeout = bt->rfk_info.map.timeout;
10036 cnt_sum += dm->cnt_notify[i];
10068 struct rtw89_btc_dm *dm = &btc->dm;
10070 u32 cnt_sum = 0, *cnt = btc->dm.cnt_notify;
10073 if (!(dm->coex_info_map & BTC_COEX_INFO_SUMMARY))
10096 if (dm->error.map.wl_fw_hang)
10148 cnt_sum += dm->cnt_notify[i];
10183 struct rtw89_btc_dm *dm = &btc->dm;
10185 u32 cnt_sum = 0, *cnt = btc->dm.cnt_notify;
10188 if (!(dm->coex_info_map & BTC_COEX_INFO_SUMMARY))
10211 if (dm->error.map.wl_fw_hang)
10263 cnt_sum += dm->cnt_notify[i];
10297 struct rtw89_btc_dm *dm = &rtwdev->btc.dm;
10299 u32 *cnt = rtwdev->btc.dm.cnt_notify;
10303 if (!(dm->coex_info_map & BTC_COEX_INFO_SUMMARY))
10327 if (dm->error.map.wl_fw_hang)
10366 cnt_sum += dm->cnt_notify[i];