Lines Matching +full:pga +full:- +full:gain
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
29 ether_addr_copy(efuse->addr, map->e.mac_addr);
35 ether_addr_copy(efuse->addr, map->u.mac_addr);
41 ether_addr_copy(efuse->addr, map->s.mac_addr);
46 struct rtw_efuse *efuse = &rtwdev->efuse;
52 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(7));
53 efuse->rfe_option = map->rfe_option;
54 efuse->rf_board_option = map->rf_board_option;
55 efuse->crystal_cap = map->xtal_k & XCAP_MASK;
56 efuse->channel_plan = map->channel_plan;
57 efuse->country_code[0] = map->country_code[0];
58 efuse->country_code[1] = map->country_code[1];
59 efuse->bt_setting = map->rf_bt_setting;
60 efuse->regd = map->rf_board_option & 0x7;
61 efuse->thermal_meter[RF_PATH_A] = map->path_a_thermal;
62 efuse->thermal_meter[RF_PATH_B] = map->path_b_thermal;
63 efuse->thermal_meter_k =
64 (map->path_a_thermal + map->path_b_thermal) >> 1;
65 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf;
68 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
82 return -ENOTSUPP;
202 for (i = 0; i < DACK_SN_8822C - 1; i++) {
203 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) {
216 for (i = 10; i < DACK_SN_8822C - 10; i++) {
218 m = (0x400 - vec[i]) + m;
224 t = p - m;
225 t = t / (DACK_SN_8822C - 20);
227 t = m - p;
228 t = t / (DACK_SN_8822C - 20);
230 t = 0x400 - t;
249 return -1;
268 return -1;
278 if ((value >= 0x200 && (0x400 - value) > 0x64) ||
324 i_delta = i_max - i_min;
326 i_delta = i_max - i_min;
328 i_delta = i_max + (0x400 - i_min);
331 q_delta = q_max - q_min;
333 q_delta = q_max - q_min;
335 q_delta = q_max + (0x400 - q_min);
351 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12;
352 qv[DACK_SN_8822C - 1] = temp & 0x3ff;
371 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a);
372 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b);
397 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
438 ic = 0x400 - ic;
442 qc = 0x400 - qc;
447 dm_info->dack_adck[path] = temp;
456 ic = 0x400 - ic;
458 qc = 0x400 - qc;
474 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
481 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]);
541 ic = 0x400 - ic;
543 qc = 0x400 - qc;
548 ic = (0x400 - ic) * 2 * 6 / 5;
549 ic = 0x7f - ic;
555 qc = (0x400 - qc) * 2 * 6 / 5;
556 qc = 0x7f - qc;
619 ic = ic - 0x10;
621 ic = 0x400 - (0x10 - ic);
624 qc = qc - 0x10;
626 qc = 0x400 - (0x10 - qc);
632 ic = 0x400 - ic;
634 qc = 0x400 - qc;
656 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
666 dm_info->dack_msbk[path][vec][i] = val;
692 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
696 dm_info->dack_dck[RF_PATH_A][0][0] = val;
698 dm_info->dack_dck[RF_PATH_A][0][1] = val;
700 dm_info->dack_dck[RF_PATH_A][1][0] = val;
702 dm_info->dack_dck[RF_PATH_A][1][1] = val;
705 dm_info->dack_dck[RF_PATH_B][0][0] = val;
707 dm_info->dack_dck[RF_PATH_B][1][0] = val;
709 dm_info->dack_dck[RF_PATH_B][0][1] = val;
711 dm_info->dack_dck[RF_PATH_B][1][1] = val;
725 /* backup path-A I/Q */
730 /* backup path-B I/Q */
746 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
750 val = dm_info->dack_dck[RF_PATH_A][0][0];
752 val = dm_info->dack_dck[RF_PATH_A][0][1];
756 val = dm_info->dack_dck[RF_PATH_A][1][0];
758 val = dm_info->dack_dck[RF_PATH_A][1][1];
762 val = dm_info->dack_dck[RF_PATH_B][0][0];
764 val = dm_info->dack_dck[RF_PATH_B][0][1];
768 val = dm_info->dack_dck[RF_PATH_B][1][0];
770 val = dm_info->dack_dck[RF_PATH_B][1][1];
846 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
863 value = dm_info->dack_msbk[path][0][i];
876 value = dm_info->dack_msbk[path][1][i];
904 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
908 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 &&
909 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 &&
910 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 &&
911 dm_info->dack_msbk[RF_PATH_B][1][0] == 0)
961 /* path-A */
977 /* path-B */
1034 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1077 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1098 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1117 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1125 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1135 struct rtw_dm_info *dm = &rtwdev->dm_info;
1144 if (!dm->is_bt_iqk_timeout) {
1152 dm->is_bt_iqk_timeout = true;
1184 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1389 static bool _rtw8822c_txgapk_gain_valid(struct rtw_dev *rtwdev, u32 gain)
1391 if ((FIELD_GET(BIT_GAIN_TX_PAD_H, gain) >= 0xc) &&
1392 (FIELD_GET(BIT_GAIN_TX_PAD_L, gain) >= 0xe))
1401 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1403 u8 gain, check_txgain;
1427 for (gain = 0; gain < RF_GAIN_NUM; gain++) {
1428 v = txgapk->rf3f_bp[band][gain][path];
1431 tmp_3f = txgapk->rf3f_bp[band][gain][path];
1436 txgapk->rf3f_bp[band][gain][path]);
1438 tmp_3f = txgapk->rf3f_bp[band][gain][path];
1442 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_I_GAIN, gain);
1457 __func__, rtwdev->dm_info.gapk.channel);
1460 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1473 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1474 u8 channel = txgapk->channel;
1519 txgapk->offset[0][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val);
1520 txgapk->offset[1][path] = (s8)FIELD_GET(BIT_GAPK_RPT1, val);
1521 txgapk->offset[2][path] = (s8)FIELD_GET(BIT_GAPK_RPT2, val);
1522 txgapk->offset[3][path] = (s8)FIELD_GET(BIT_GAPK_RPT3, val);
1523 txgapk->offset[4][path] = (s8)FIELD_GET(BIT_GAPK_RPT4, val);
1524 txgapk->offset[5][path] = (s8)FIELD_GET(BIT_GAPK_RPT5, val);
1525 txgapk->offset[6][path] = (s8)FIELD_GET(BIT_GAPK_RPT6, val);
1526 txgapk->offset[7][path] = (s8)FIELD_GET(BIT_GAPK_RPT7, val);
1531 txgapk->offset[8][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val);
1532 txgapk->offset[9][path] = (s8)FIELD_GET(BIT_GAPK_RPT1, val);
1535 if (txgapk->offset[i][path] & BIT(3))
1536 txgapk->offset[i][path] = txgapk->offset[i][path] |
1541 txgapk->offset[i][path], i, path);
1548 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1549 u8 channel = txgapk->channel;
1622 if (path >= rtwdev->hal.rf_path_num)
1630 static u32 rtw8822c_txgapk_cal_gain(struct rtw_dev *rtwdev, u32 gain, s8 offset)
1636 if (_rtw8822c_txgapk_gain_valid(rtwdev, gain)) {
1637 new_gain = gain;
1639 "[TXGAPK] gain=0x%03X(>=0xCEX) offset=%d new_gain=0x%03X\n",
1640 gain, offset, new_gain);
1644 gain_x2 = (gain << 1) + offset;
1648 "[TXGAPK] gain=0x%X offset=%d new_gain=0x%X\n",
1649 gain, offset, new_gain);
1656 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1659 u8 path, band = RF_BAND_2G_OFDM, channel = txgapk->channel;
1680 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1684 v = txgapk->rf3f_bp[band][j][path];
1688 offset_tmp[i] += txgapk->offset[j][path];
1689 txgapk->fianl_offset[i][path] = offset_tmp[i];
1692 v = txgapk->rf3f_bp[band][i][path];
1696 txgapk->rf3f_bp[band][i][path]);
1698 txgapk->rf3f_fs[path][i] = offset_tmp[i];
1711 txgapk->rf3f_bp[band][i][path],
1726 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1731 u8 path, band, gain, rf0_idx;
1734 if (rtwdev->dm_info.dm_flags & BIT(RTW_DM_CAP_TXGAPK))
1739 if (txgapk->read_txgain == 1) {
1741 "[TXGAPK] Already Read txgapk->read_txgain return!!!\n");
1747 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1760 gain = 0;
1766 txgapk->rf3f_bp[band][gain][path] = v & BIT_DATA_L;
1770 txgapk->rf3f_bp[band][gain][path],
1772 gain++;
1780 txgapk->read_txgain = 1;
1786 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1794 if (txgapk->read_txgain == 0) {
1796 "[TXGAPK] txgapk->read_txgain == 0 return!!!\n");
1800 if (rtwdev->efuse.power_track_type >= 4 &&
1801 rtwdev->efuse.power_track_type <= 7) {
1810 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1811 txgapk->channel = rtw_read_rf(rtwdev, path,
1827 struct rtw_dm_info *dm = &rtwdev->dm_info;
1829 if (dm->dm_flags & BIT(RTW_DM_CAP_TXGAPK)) {
1849 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1853 dm_info->delta_power_index[path] = 0;
1854 ewma_thermal_init(&dm_info->avg_thermal[path]);
1855 dm_info->thermal_avg[path] = 0xff;
1858 dm_info->pwr_trk_triggered = false;
1859 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
1860 dm_info->thermal_meter_lck = rtwdev->efuse.thermal_meter_k;
1865 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1866 struct rtw_hal *hal = &rtwdev->hal;
1889 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f;
1897 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
1906 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb));
1907 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb));
2078 /* Set beacon cotnrol - enable TSF and other related functions */
2266 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2);
2267 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2);
2555 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2559 s8 min_rx_power = -120;
2566 l_bnd = dm_info->cck_gi_l_bnd;
2567 u_bnd = dm_info->cck_gi_u_bnd;
2571 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1;
2573 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1;
2575 rx_power[RF_PATH_B] += (l_bnd - gain_b) << 1;
2577 rx_power[RF_PATH_B] -= (gain_b - u_bnd) << 1;
2579 rx_power[RF_PATH_A] -= 110;
2580 rx_power[RF_PATH_B] -= 110;
2586 pkt_stat->channel_invalid = true;
2588 pkt_stat->rx_power[RF_PATH_A] = rx_power[RF_PATH_A];
2589 pkt_stat->rx_power[RF_PATH_B] = rx_power[RF_PATH_B];
2591 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
2592 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
2593 dm_info->rssi[path] = rssi;
2596 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
2597 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
2598 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
2605 struct rtw_path_div *p_div = &rtwdev->dm_path_div;
2606 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2608 s8 min_rx_power = -120;
2615 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
2621 bw = rtwdev->hal.current_band_width;
2632 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
2633 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110;
2634 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2);
2635 pkt_stat->bw = bw;
2636 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
2637 pkt_stat->rx_power[RF_PATH_B],
2640 dm_info->curr_rx_rate = pkt_stat->rate;
2642 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status);
2643 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status);
2645 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status);
2646 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status);
2648 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status);
2649 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status);
2651 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
2652 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
2653 dm_info->rssi[path] = rssi;
2655 p_div->path_a_sum += rssi;
2656 p_div->path_a_cnt++;
2658 p_div->path_b_sum += rssi;
2659 p_div->path_b_cnt++;
2661 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1;
2662 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1;
2664 rx_evm = pkt_stat->rx_evm[path];
2670 evm_dbm = ((u8)-rx_evm >> 1);
2672 dm_info->rx_evm_dbm[path] = evm_dbm;
2701 struct rtw_hal *hal = &rtwdev->hal;
2706 for (path = 0; path < hal->rf_path_num; path++) {
2711 for (path = 0; path < hal->rf_path_num; path++) {
2742 struct rtw_hal *hal = &rtwdev->hal;
2744 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M],
2745 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]};
2746 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7],
2747 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]};
2756 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate];
2757 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate];
2759 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0];
2760 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1];
2762 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0];
2763 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1];
2767 rtw8822c_set_tx_power_diff(rtwdev, rate - 3,
2777 struct rtw_hal *hal = &rtwdev->hal;
2786 return -EINVAL;
2796 return -EINVAL;
2799 hal->antenna_tx = antenna_tx;
2800 hal->antenna_rx = antenna_rx;
2818 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2849 dm_info->cck_fa_cnt = cck_fa_cnt;
2850 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
2851 dm_info->total_fa_cnt = ofdm_fa_cnt;
2852 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
2855 dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
2856 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2858 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
2859 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2861 dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
2862 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2864 dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
2865 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2868 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16);
2869 dm_info->cck_cca_cnt = cca32_cnt & 0xffff;
2870 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
2872 dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
2936 /* enable PTA (3-wire function form BT side) */
2955 struct rtw_coex *coex = &rtwdev->coex;
2956 struct rtw_coex_stat *coex_stat = &coex->stat;
2957 struct rtw_efuse *efuse = &rtwdev->efuse;
2960 if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode)
2963 coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode;
2965 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun)
2970 /* BT at S1 for Shared-Ant */
2971 if (efuse->share_ant)
2976 /* WL-S0 2G RF TRX cannot be masked by GNT_BT
2977 * enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type
2980 * enable "DAC off if GNT_WL = 0" for non-shared-antenna
2984 if (coex_stat->wl_coex_mode == COEX_WLINK_2GFREE) {
2996 /* disable WL-S1 BB chage RF mode if GNT_BT
3002 /* disable WL-S0 BB chage RF mode if wifi is at 5G,
3005 if (coex_stat->wl_coex_mode == COEX_WLINK_2GFREE) {
3010 } else if (coex_stat->wl_coex_mode == COEX_WLINK_5G ||
3011 coex->under_5g || !efuse->share_ant) {
3012 if (coex_stat->kt_ver >= 3) {
3022 /* shared-antenna */
3025 if (coex_stat->kt_ver >= 3) {
3043 struct rtw_coex *coex = &rtwdev->coex;
3044 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
3045 struct rtw_efuse *efuse = &rtwdev->efuse;
3047 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
3048 coex_rfe->ant_switch_polarity = 0;
3049 coex_rfe->ant_switch_exist = false;
3050 coex_rfe->ant_switch_with_bt = false;
3051 coex_rfe->ant_switch_diversity = false;
3053 if (efuse->share_ant)
3054 coex_rfe->wlg_at_btg = true;
3056 coex_rfe->wlg_at_btg = false;
3066 struct rtw_coex *coex = &rtwdev->coex;
3067 struct rtw_coex_dm *coex_dm = &coex->dm;
3069 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
3072 coex_dm->cur_wl_pwr_lvl = wl_pwr;
3077 struct rtw_coex *coex = &rtwdev->coex;
3078 struct rtw_coex_dm *coex_dm = &coex->dm;
3080 if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
3083 coex_dm->cur_wl_rx_low_gain_en = low_gain;
3085 if (coex_dm->cur_wl_rx_low_gain_en) {
3086 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n");
3095 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n");
3117 if (vif->net_type == RTW_NET_AP_MODE)
3148 if (bfee->role == RTW_BFEE_SU)
3150 else if (bfee->role == RTW_BFEE_MU)
3165 const struct dpk_cfg_pair *p = tbl->data;
3166 const struct dpk_cfg_pair *end = p + tbl->size / 3;
3171 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data);
3176 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3179 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70);
3180 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38);
3185 dpk_info->gnt_value);
3186 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control);
3242 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3253 dpk_info->dpk_band = 1 << band_shift;
3254 dpk_info->dpk_ch = FIELD_GET(0xff, reg);
3255 dpk_info->dpk_bw = FIELD_GET(0x3000, reg);
3277 dc_i = 0x1000 - dc_i;
3279 dc_q = 0x1000 - dc_q;
3326 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3329 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G)
3353 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) {
3367 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80)
3382 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0;
3418 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
3431 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
3481 i_val = 0x10000 - i_val;
3483 q_val = 0x10000 - q_val;
3507 tindex = ARRAY_SIZE(table_fraction) - 1;
3511 result = val_integerd_b * 100 - val_fractiond_b;
3555 loss_db = 3 * rtw8822c_psd_log2base(loss >> 13) - 3870;
3567 u8 pga;
3580 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN,
3582 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC,
3585 if (data->loss_only) {
3590 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path,
3591 data->limited_pga);
3592 if (state == RTW_DPK_GAIN_CHECK && data->gain_only)
3598 data->agc_cnt++;
3599 if (data->agc_cnt >= 6)
3608 u8 pga = data->pga;
3610 if (pga > 0xe)
3611 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
3612 else if (pga > 0xb && pga < 0xf)
3613 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0);
3614 else if (pga < 0xc)
3615 data->limited_pga = 1;
3623 u8 pga = data->pga;
3625 if (pga < 0xc)
3626 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
3627 else if (pga > 0xb && pga < 0xf)
3628 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
3629 else if (pga > 0xe)
3630 data->limited_pga = 1;
3640 if (data->txbb == txbb_bound[is_large])
3644 data->txbb -= 2;
3646 data->txbb += 3;
3648 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb);
3649 data->limited_pga = 0;
3669 u8 path = data->path;
3725 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1;
3741 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3747 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev);
3768 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3773 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]);
3774 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]);
3786 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3801 coef = dpk_info->coef[path][addr];
3810 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3815 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6));
3819 dpk_info->result[path] = result;
3820 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC);
3827 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3850 tx_bb = tx_bb - tx_agc_search;
3854 tx_agc = ori_txagc - (ori_txbb - tx_bb);
3858 dpk_info->thermal_dpk_delta[path] = abs(t2 - t1);
3882 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3903 if (dpk_info->dpk_bw == DPK_CHANNEL_WIDTH_80) {
3947 dpk_info->dpk_gs[path] = tmp_gs;
3952 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3967 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3968 i_scaling = 0x16c00 / dpk_info->dpk_gs[path];
3985 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3992 if (test_bit(path, dpk_info->dpk_path_ok))
4017 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4020 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4021 clear_bit(path, dpk_info->dpk_path_ok);
4026 dpk_info->dpk_txagc[path] = 0;
4027 dpk_info->result[path] = 0;
4028 dpk_info->dpk_gs[path] = 0x5b;
4029 dpk_info->pre_pwsf[path] = 0;
4030 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev,
4037 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4052 if (dpk_info->result[path])
4053 set_bit(path, dpk_info->dpk_path_ok);
4067 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4073 dpk_info->is_dpk_pwr_on);
4075 dpk_info->is_dpk_pwr_on);
4077 if (test_bit(RF_PATH_A, dpk_info->dpk_path_ok)) {
4079 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]);
4081 if (test_bit(RF_PATH_B, dpk_info->dpk_path_ok)) {
4083 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]);
4089 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4092 if (!test_bit(RF_PATH_A, dpk_info->dpk_path_ok) &&
4093 !test_bit(RF_PATH_B, dpk_info->dpk_path_ok) &&
4094 dpk_info->dpk_ch == 0)
4097 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4100 if (dpk_info->dpk_band == RTW_BAND_2G)
4105 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]);
4108 test_bit(path, dpk_info->dpk_path_ok));
4116 dpk_info->dpk_gs[path]);
4119 dpk_info->dpk_gs[path]);
4126 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4129 dpk_info->is_reload = false;
4137 if (channel == dpk_info->dpk_ch) {
4139 "[DPK] DPK reload for CH%d!!\n", dpk_info->dpk_ch);
4141 dpk_info->is_reload = true;
4144 return dpk_info->is_reload;
4149 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4160 if (!dpk_info->is_dpk_pwr_on) {
4168 ewma_thermal_init(&dpk_info->avg_thermal[path]);
4184 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
4200 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4205 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0)
4210 ewma_thermal_add(&dpk_info->avg_thermal[path],
4213 ewma_thermal_read(&dpk_info->avg_thermal[path]);
4214 delta_dpk[path] = dpk_info->thermal_dpk[path] -
4216 offset[path] = delta_dpk[path] -
4217 dpk_info->thermal_dpk_delta[path];
4220 if (offset[path] != dpk_info->pre_pwsf[path]) {
4225 dpk_info->pre_pwsf[path] = offset[path];
4233 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4234 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
4238 cfo->crystal_cap = crystal_cap;
4244 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4245 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
4247 if (cfo->crystal_cap == crystal_cap)
4255 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4256 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
4258 cfo->is_adjust = true;
4260 if (cfo->crystal_cap > rtwdev->efuse.crystal_cap)
4261 rtw8822c_set_crystal_cap(rtwdev, cfo->crystal_cap - 1);
4262 else if (cfo->crystal_cap < rtwdev->efuse.crystal_cap)
4263 rtw8822c_set_crystal_cap(rtwdev, cfo->crystal_cap + 1);
4268 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4269 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
4271 cfo->crystal_cap = rtwdev->efuse.crystal_cap;
4272 cfo->is_adjust = true;
4278 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4279 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
4284 cfo_rpt_sum = REPORT_TO_KHZ(cfo->cfo_tail[i]);
4286 if (cfo->cfo_cnt[i])
4287 cfo_avg = cfo_rpt_sum / cfo->cfo_cnt[i];
4295 cfo->cfo_tail[i] = 0;
4296 cfo->cfo_cnt[i] = 0;
4304 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4305 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
4307 if (!cfo->is_adjust) {
4309 cfo->is_adjust = true;
4312 cfo->is_adjust = false;
4316 cfo->is_adjust = false;
4317 rtw8822c_set_crystal_cap(rtwdev, rtwdev->efuse.crystal_cap);
4323 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4324 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
4325 u8 path_num = rtwdev->hal.rf_path_num;
4326 s8 crystal_cap = cfo->crystal_cap;
4329 if (rtwdev->sta_cnt != 1) {
4334 if (cfo->packet_count == cfo->packet_count_pre)
4337 cfo->packet_count_pre = cfo->packet_count;
4341 if (cfo->is_adjust) {
4344 else if (cfo_avg < -CFO_TRK_ADJ_TH)
4345 crystal_cap--;
4407 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4416 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d) bw=%d nr=%d cck_fa_avg=%d\n",
4417 dm_info->cck_pd_lv[bw][nrx], new_lvl, bw, nrx,
4418 dm_info->cck_fa_avg);
4420 if (dm_info->cck_pd_lv[bw][nrx] == new_lvl)
4423 cur_lvl = dm_info->cck_pd_lv[bw][nrx];
4426 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
4429 pd_lvl[new_lvl] - pd_lvl[cur_lvl],
4430 cs_lvl[new_lvl] - cs_lvl[cur_lvl],
4432 dm_info->cck_pd_lv[bw][nrx] = new_lvl;
4438 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4443 dm_info->delta_power_index[rf_path]);
4447 dm_info->delta_power_index[rf_path]);
4458 if (rtwdev->efuse.thermal_meter[path] == 0xff)
4469 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4473 dm_info->delta_power_index[path] =
4486 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
4490 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
4496 struct rtw_efuse *efuse = &rtwdev->efuse;
4497 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4499 if (efuse->power_track_type != 0)
4502 if (!dm_info->pwr_trk_triggered) {
4511 dm_info->pwr_trk_triggered = true;
4516 dm_info->pwr_trk_triggered = false;
4533 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4537 igi = dm_info->igi_history[0];
4538 if (dm_info->edcca_mode == RTW_EDCCA_NORMAL) {
4540 h2l = l2h - EDCCA_L2H_H2L_DIFF_NORMAL;
4542 if (igi < dm_info->l2h_th_ini - EDCCA_ADC_BACKOFF)
4545 l2h = dm_info->l2h_th_ini;
4546 h2l = l2h - EDCCA_L2H_H2L_DIFF;
4574 const struct rtw_chip_info *chip = rtwdev->chip;
4577 words = (pkt_info->pkt_offset * 8 + chip->tx_pkt_desc_sz) / 2;
5009 /* Shared-Antenna Coex Table */
5011 {0xffffffff, 0xffffffff}, /* case-0 */
5016 {0xfafafafa, 0xfafafafa}, /* case-5 */
5021 {0x66555555, 0x6a5a5a5a}, /* case-10 */
5026 {0x66555555, 0xaaaaaaaa}, /* case-15 */
5031 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
5036 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
5041 {0x66556aaa, 0x6a5a6aaa}, /*case-30*/
5048 /* Non-Shared-Antenna Coex Table */
5050 {0xffffffff, 0xffffffff}, /* case-100 */
5055 {0xfafafafa, 0xfafafafa}, /* case-105 */
5060 {0x66555555, 0x6a5a5a5a}, /* case-110 */
5065 {0xffff55ff, 0xffff55ff}, /* case-115 */
5070 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
5076 /* Shared-Antenna TDMA */
5078 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
5079 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
5083 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
5088 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
5093 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
5098 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
5103 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
5108 /* Non-Shared-Antenna TDMA */
5110 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
5115 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
5120 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
5125 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
5130 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
5134 /* rssi in percentage % (dbm = % - 100) */
5142 {0, 16, false, 7}, /* for WL-CPT */
5152 {0, 16, false, 7}, /* for WL-CPT */
5414 .max_scan_ie_len = (RTW_PROBE_PG_CNT - 1) * TX_PAGE_SIZE,