Lines Matching +full:0 +full:x38000
21 #define IQK_DONE_8822C 0xaa
56 efuse->country_code[0] = map->country_code[0];
59 efuse->regd = map->rf_board_option & 0x7;
64 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf;
66 for (i = 0; i < 4; i++)
84 return 0;
114 u32 rf_addr[DACK_RF_8822C] = {0x8f};
115 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110,
116 0x1c3c, 0x1c24, 0x1d70, 0x9b4,
117 0x1a00, 0x1a14, 0x1d58, 0x1c38,
118 0x1e24, 0x1e28, 0x1860, 0x4160};
120 for (i = 0; i < DACK_REG_8822C; i++) {
126 for (path = 0; path < DACK_PATH_8822C; path++) {
127 for (i = 0; i < DACK_RF_8822C; i++) {
146 for (path = 0; path < DACK_PATH_8822C; path++) {
147 for (i = 0; i < DACK_RF_8822C; i++) {
158 if (value >= 0x200) {
159 if (*min >= 0x200) {
165 if (*max >= 0x200) {
170 if (*min < 0x200) {
175 if (*max >= 0x200) {
186 if (*v1 >= 0x200 && *v2 >= 0x200) {
189 } else if (*v1 < 0x200 && *v2 < 0x200) {
192 } else if (*v1 < 0x200 && *v2 >= 0x200) {
201 for (i = 0; i < DACK_SN_8822C - 1; i++) {
202 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) {
213 m = 0;
214 p = 0;
216 if (vec[i] > 0x200)
217 m = (0x400 - vec[i]) + m;
228 if (t != 0x0)
229 t = 0x400 - t;
241 base_addr = 0x1800;
244 base_addr = 0x4100;
260 base_addr = 0x2800;
263 base_addr = 0x4500;
277 if ((value >= 0x200 && (0x400 - value) > 0x64) ||
278 (value < 0x200 && value > 0x64)) {
289 int i = 0, cnt = 0;
293 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
294 iv[i] = (temp & 0x3ff000) >> 12;
295 qv[i] = temp & 0x3ff;
307 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0;
310 int i, cnt = 0;
313 i_min = iv[0];
314 i_max = iv[0];
315 q_min = qv[0];
316 q_max = qv[0];
317 for (i = 0; i < DACK_SN_8822C; i++) {
322 if (i_max < 0x200 && i_min < 0x200)
324 else if (i_max >= 0x200 && i_min >= 0x200)
327 i_delta = i_max + (0x400 - i_min);
329 if (q_max < 0x200 && q_min < 0x200)
331 else if (q_max >= 0x200 && q_min >= 0x200)
334 q_delta = q_max + (0x400 - q_min);
337 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n",
340 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n",
346 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
347 iv[0] = (temp & 0x3ff000) >> 12;
348 qv[0] = temp & 0x3ff;
349 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
350 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12;
351 qv[DACK_SN_8822C - 1] = temp & 0x3ff;
367 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK);
368 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK);
370 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a);
371 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b);
379 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff);
380 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2);
381 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3);
382 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e);
383 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0);
384 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0);
385 rtw_write32(rtwdev, 0x1b00, 0x00000008);
386 rtw_write8(rtwdev, 0x1bcc, 0x3f);
387 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
388 rtw_write8(rtwdev, 0x1bcc, 0x3f);
389 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0);
390 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3);
397 u32 ic = 0, qc = 0, temp = 0;
407 path_sel = 0xa0000;
410 path_sel = 0x80000;
418 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0);
420 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041);
421 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
422 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
423 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4);
424 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
425 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000);
426 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000);
427 for (i = 0; i < 10; i++) {
429 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003);
430 rtw_write32(rtwdev, 0x1c24, 0x00010002);
433 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc);
436 if (ic != 0x0) {
437 ic = 0x400 - ic;
440 if (qc != 0x0) {
441 qc = 0x400 - qc;
444 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10);
445 rtw_write32(rtwdev, base_addr + 0x68, temp);
447 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n",
448 base_addr + 0x68, temp);
450 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103);
453 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc);
454 if (ic >= 0x200)
455 ic = 0x400 - ic;
456 if (qc >= 0x200)
457 qc = 0x400 - qc;
463 rtw_write32(rtwdev, 0x1c3c, 0x00000003);
464 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
465 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
468 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1);
480 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]);
481 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
483 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
484 rtw_write32(rtwdev, 0x1c38, 0xffffffff);
486 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
487 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
488 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
489 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81);
490 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
491 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
492 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81);
493 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
494 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
496 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d);
498 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
499 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
501 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
502 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
504 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) ||
505 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff))
507 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
509 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
510 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
511 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
512 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
513 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
523 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0);
524 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8);
525 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0);
526 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8);
528 rtw_write32(rtwdev, 0x1b00, 0x00000008);
529 rtw_write8(rtwdev, 0x1bcc, 0x03f);
530 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
531 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
532 rtw_write32(rtwdev, 0x1c3c, 0x00088103);
539 if (ic != 0x0)
540 ic = 0x400 - ic;
541 if (qc != 0x0)
542 qc = 0x400 - qc;
543 if (ic < 0x300) {
545 ic = ic + 0x80;
547 ic = (0x400 - ic) * 2 * 6 / 5;
548 ic = 0x7f - ic;
550 if (qc < 0x300) {
552 qc = qc + 0x80;
554 qc = (0x400 - qc) * 2 * 6 / 5;
555 qc = 0x7f - qc;
561 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in);
562 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc);
580 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
581 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
582 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
583 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
584 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81);
585 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
586 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf);
587 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4);
588 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
589 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81);
590 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
591 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf);
592 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4);
593 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
595 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6);
597 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
598 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
600 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
601 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
603 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) ||
604 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc))
606 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
608 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3);
609 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
612 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10);
613 rtw_write32(rtwdev, base_addr + 0x68, temp);
614 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
615 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
617 if (ic >= 0x10)
618 ic = ic - 0x10;
620 ic = 0x400 - (0x10 - ic);
622 if (qc >= 0x10)
623 qc = qc - 0x10;
625 qc = 0x400 - (0x10 - qc);
630 if (ic >= 0x200)
631 ic = 0x400 - ic;
632 if (qc >= 0x200)
633 qc = 0x400 - qc;
639 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out);
646 rtw_write32(rtwdev, base_addr + 0x68, 0x0);
647 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
648 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0);
649 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1);
662 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
663 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i);
664 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000);
671 u32 w_off = 0x1c;
672 u32 r_off = 0x2c;
679 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0;
680 r_addr = rtw8822c_get_path_read_addr(path) + 0x10;
681 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr);
684 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
685 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off;
694 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000);
695 dm_info->dack_dck[RF_PATH_A][0][0] = val;
696 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf);
697 dm_info->dack_dck[RF_PATH_A][0][1] = val;
698 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000);
699 dm_info->dack_dck[RF_PATH_A][1][0] = val;
700 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf);
703 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000);
704 dm_info->dack_dck[RF_PATH_B][0][0] = val;
705 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf);
706 dm_info->dack_dck[RF_PATH_B][1][0] = val;
707 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000);
708 dm_info->dack_dck[RF_PATH_B][0][1] = val;
709 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf);
717 temp[0] = rtw_read32(rtwdev, 0x1860);
718 temp[1] = rtw_read32(rtwdev, 0x4160);
719 temp[2] = rtw_read32(rtwdev, 0x9b4);
722 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
725 rtw_write32_clr(rtwdev, 0x1830, BIT(30));
726 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
730 rtw_write32_clr(rtwdev, 0x4130, BIT(30));
731 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
735 rtw_write32_set(rtwdev, 0x1830, BIT(30));
736 rtw_write32_set(rtwdev, 0x4130, BIT(30));
738 rtw_write32(rtwdev, 0x1860, temp[0]);
739 rtw_write32(rtwdev, 0x4160, temp[1]);
740 rtw_write32(rtwdev, 0x9b4, temp[2]);
749 val = dm_info->dack_dck[RF_PATH_A][0][0];
750 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val);
751 val = dm_info->dack_dck[RF_PATH_A][0][1];
752 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val);
755 val = dm_info->dack_dck[RF_PATH_A][1][0];
756 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val);
758 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val);
761 val = dm_info->dack_dck[RF_PATH_B][0][0];
762 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val);
763 val = dm_info->dack_dck[RF_PATH_B][0][1];
764 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val);
767 val = dm_info->dack_dck[RF_PATH_B][1][0];
768 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val);
770 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val);
775 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
777 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0);
778 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0);
779 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0);
780 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0);
782 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0);
783 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
784 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1);
785 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1);
787 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0);
788 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
789 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1);
790 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1);
792 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0);
793 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0);
794 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0);
795 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0);
797 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0);
798 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0);
799 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1);
800 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1);
804 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7);
805 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7);
806 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7);
807 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7);
809 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1);
810 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1);
812 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0);
813 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0);
814 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0);
815 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0);
817 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0);
818 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0);
819 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1);
820 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1);
822 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1);
823 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1);
829 u32 cnt = 0;
832 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0);
833 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2);
835 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6)
846 u32 w_off = 0x1c;
847 u32 r_off = 0x2c;
852 w_i = rtw8822c_get_path_write_addr(path) + 0xb0;
853 r_i = rtw8822c_get_path_read_addr(path) + 0x08;
854 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
855 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off;
857 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8))
860 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
861 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
862 value = dm_info->dack_msbk[path][0][i];
863 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value);
864 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i);
865 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1);
868 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
870 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8))
873 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
874 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
876 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value);
877 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i);
878 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1);
880 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
882 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0);
883 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0);
884 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0);
885 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0);
907 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 &&
908 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 &&
909 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 &&
910 dm_info->dack_msbk[RF_PATH_B][1][0] == 0)
913 temp[0] = rtw_read32(rtwdev, 0x1860);
914 temp[1] = rtw_read32(rtwdev, 0x4160);
915 temp[2] = rtw_read32(rtwdev, 0x9b4);
918 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) ||
919 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) ||
920 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) ||
921 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff))
929 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1);
930 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
931 rtw_write32(rtwdev, 0x1860, temp[0]);
932 rtw_write32(rtwdev, 0x4160, temp[1]);
933 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1);
934 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1);
935 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1);
936 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1);
937 rtw_write32(rtwdev, 0x9b4, temp[2]);
946 u32 ic = 0, qc = 0, i;
947 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0;
948 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0;
949 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0;
962 for (i = 0; i < 10; i++) {
978 for (i = 0; i < 10; i++) {
992 rtw_write32(rtwdev, 0x1b00, 0x00000008);
993 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
994 rtw_write8(rtwdev, 0x1bcc, 0x0);
995 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
996 rtw_write8(rtwdev, 0x1bcc, 0x0);
1003 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a);
1004 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b);
1005 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a);
1006 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b);
1014 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15));
1016 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440);
1017 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D);
1018 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440);
1027 rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq); \
1028 rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK, \
1030 } while (0)
1033 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1034 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1);
1035 RF_SET_POWER_TRIM(path, 0x0, 0);
1036 RF_SET_POWER_TRIM(path, 0x1, 1);
1037 RF_SET_POWER_TRIM(path, 0x2, 2);
1038 RF_SET_POWER_TRIM(path, 0x3, 2);
1039 RF_SET_POWER_TRIM(path, 0x4, 3);
1040 RF_SET_POWER_TRIM(path, 0x5, 4);
1041 RF_SET_POWER_TRIM(path, 0x6, 5);
1042 RF_SET_POWER_TRIM(path, 0x7, 6);
1043 RF_SET_POWER_TRIM(path, 0x8, 7);
1044 RF_SET_POWER_TRIM(path, 0x9, 3);
1045 RF_SET_POWER_TRIM(path, 0xa, 4);
1046 RF_SET_POWER_TRIM(path, 0xb, 5);
1047 RF_SET_POWER_TRIM(path, 0xc, 6);
1048 RF_SET_POWER_TRIM(path, 0xd, 7);
1049 RF_SET_POWER_TRIM(path, 0xe, 7);
1050 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0);
1057 u8 pg_pwr = 0xff, i, path, idx;
1066 for (i = 0; i < ARRAY_SIZE(rf_efuse_2g); i++) {
1075 for (i = 0; i < ARRAY_SIZE(rf_efuse_5g[0]); i++) {
1076 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1095 u8 pg_therm = 0xff, thermal[2] = {0}, path;
1097 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1101 /* Efuse value of BIT(0) shall be move to BIT(3), and the value
1105 thermal[path] |= FIELD_PREP(BIT(3), pg_therm & BIT(0));
1106 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]);
1114 u8 pg_pa_bias = 0xff, path;
1116 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1124 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1145 u4b_tmp == 0, 20, 600000, false,
1183 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1186 is_power_save ? 0 : 1);
1195 for (i = 0; i < reg_num; i++) {
1198 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Backup BB 0x%x = 0x%x\n",
1209 for (i = 0; i < reg_num; i++) {
1211 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Reload BB 0x%x = 0x%x\n",
1237 rtw_write32_mask(rtwdev, REG_TX_FIFO, BIT_STOP_TX, 0x2);
1251 rtw_write32_mask(rtwdev, REG_ENFN, BIT_IQK_DPK_EN, 0x1);
1253 BIT_IQK_DPK_CLOCK_SRC, 0x1);
1255 BIT_IQK_DPK_RESET_SRC, 0x1);
1256 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_EN_IOQ_IQK_DPK, 0x1);
1257 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_TST_IQK2SET_SRC, 0x0);
1258 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x1ff);
1262 BIT_RFTXEN_GCK_FORCE_ON, 0x1);
1263 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x1);
1265 BIT_TX_SCALE_0DB, 0x1);
1266 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x0);
1269 BIT_RFTXEN_GCK_FORCE_ON, 0x1);
1271 BIT_DIS_SHARERX_TXGAT, 0x1);
1273 BIT_TX_SCALE_0DB, 0x1);
1274 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x0);
1276 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x2);
1295 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001);
1296 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001);
1297 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x701f0001);
1298 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x702f0001);
1299 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x703f0001);
1300 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x704f0001);
1301 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705f0001);
1302 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x706f0001);
1303 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707f0001);
1304 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708f0001);
1305 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709f0001);
1306 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70af0001);
1307 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bf0001);
1308 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cf0001);
1309 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70df0001);
1310 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ef0001);
1311 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001);
1312 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001);
1329 rtw_write32_mask(rtwdev, REG_IQK_CTRL, MASKDWORD, 0xffa1005e);
1330 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700b8041);
1331 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70144041);
1332 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70244041);
1333 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70344041);
1334 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70444041);
1335 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705b8041);
1336 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70644041);
1337 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707b8041);
1338 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708b8041);
1339 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709b8041);
1340 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ab8041);
1341 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bb8041);
1342 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cb8041);
1343 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70db8041);
1344 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70eb8041);
1345 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70fb8041);
1352 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x0);
1353 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TIA_BYPASS, 0x0);
1354 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TXBB, 0x0);
1356 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0);
1357 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1358 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0);
1359 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00);
1360 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x1);
1361 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1362 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0);
1363 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00);
1364 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0);
1365 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x0);
1369 BIT_RFTXEN_GCK_FORCE_ON, 0x0);
1370 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x0);
1372 BIT_TX_SCALE_0DB, 0x0);
1373 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x3);
1376 BIT_RFTXEN_GCK_FORCE_ON, 0x0);
1378 BIT_DIS_SHARERX_TXGAT, 0x0);
1380 BIT_TX_SCALE_0DB, 0x0);
1381 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x3);
1384 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x0);
1385 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_CFIR_EN, 0x5);
1390 if ((FIELD_GET(BIT_GAIN_TX_PAD_H, gain) >= 0xc) &&
1391 (FIELD_GET(BIT_GAIN_TX_PAD_L, gain) >= 0xe))
1401 u32 v, tmp_3f = 0;
1408 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0);
1411 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2);
1414 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3);
1417 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4);
1423 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, MASKBYTE0, 0x88);
1425 check_txgain = 0;
1426 for (gain = 0; gain < RF_GAIN_NUM; gain++) {
1434 "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n",
1442 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x1);
1443 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x0);
1446 "[TXGAPK] Band=%d 0x1b98[11:0]=0x%03X path=%d\n",
1458 for (band = 0; band < RF_BAND_MAX; band++) {
1459 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1468 static const u32 cfg1_1b00[2] = {0x00000d18, 0x00000d2a};
1469 static const u32 cfg2_1b00[2] = {0x00000d19, 0x00000d2b};
1486 rtw_write32_mask(rtwdev, REG_TXLGMAP, MASKDWORD, 0xe4e40000);
1487 rtw_write32_mask(rtwdev, REG_TXANTSEG, BIT_ANTSEG, 0x3);
1488 rtw_write32_mask(rtwdev, path_setting[path], MASK20BITS, 0x33312);
1489 rtw_write32_mask(rtwdev, path_setting[path], BIT_PATH_EN, 0x1);
1490 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x0);
1491 rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT_TXA_TANK, 0x1);
1492 rtw_write_rf(rtwdev, path, RF_IDAC, BIT_TX_MODE, 0x820);
1494 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0);
1496 rtw_write32_mask(rtwdev, REG_TX_TONE_IDX, MASKBYTE0, 0x018);
1508 val == 0x55, 1000, 100000, false,
1511 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x2);
1513 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_EN, 0x1);
1514 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x12);
1515 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x3);
1518 txgapk->offset[0][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val);
1527 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x4);
1533 for (i = 0; i < RF_HW_OFFSET_NUM; i++)
1536 0xf0;
1537 for (i = 0; i < RF_HW_OFFSET_NUM; i++)
1549 u32 reg_backup[ARRAY_SIZE(bb_reg)] = {0};
1559 REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0);
1561 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f);
1562 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1563 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
1564 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x5000f);
1565 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x0);
1566 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x1);
1567 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0f);
1568 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
1569 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
1570 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
1571 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1);
1573 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x00);
1574 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0);
1581 REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0);
1583 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f);
1584 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1585 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
1586 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50011);
1587 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x3);
1588 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x3);
1589 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
1591 RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0x2);
1592 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x12);
1593 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
1594 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
1595 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1);
1596 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x5);
1598 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0);
1602 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2);
1605 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3);
1608 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4);
1624 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x3);
1625 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x0);
1626 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x0);
1638 "[TXGAPK] gain=0x%03X(>=0xCEX) offset=%d new_gain=0x%03X\n",
1644 new_gain = (gain_x2 >> 1) | (gain_x2 & BIT(0) ? BIT_GAIN_EXT : 0);
1647 "[TXGAPK] gain=0x%X offset=%d new_gain=0x%X\n",
1656 u32 i, j, tmp = 0x20, tmp_3f, v;
1657 s8 offset_tmp[RF_GAIN_NUM] = {0};
1663 tmp = 0x20;
1666 tmp = 0x200;
1669 tmp = 0x280;
1672 tmp = 0x300;
1679 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1680 for (i = 0; i < RF_GAIN_NUM; i++) {
1681 offset_tmp[i] = 0;
1694 "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n",
1704 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x10000);
1705 for (i = 0; i < RF_GAIN_NUM; i++) {
1716 "[TXGAPK] 0x33=0x%05X 0x3f=0x%04X\n",
1719 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x0);
1728 static const u8 band_num[RF_BAND_MAX] = {0x0, 0x0, 0x1, 0x3, 0x5};
1729 static const u8 cck[RF_BAND_MAX] = {0x1, 0x0, 0x0, 0x0, 0x0};
1745 for (band = 0; band < RF_BAND_MAX; band++) {
1746 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1750 three_wire[path], BIT_3WIRE_EN, 0x0);
1759 gain = 0;
1768 "[TXGAPK] 0x5f=0x%03X band=%d path=%d\n",
1775 three_wire[path], BIT_3WIRE_EN, 0x3);
1793 if (txgapk->read_txgain == 0) {
1795 "[TXGAPK] txgapk->read_txgain == 0 return!!!\n");
1809 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1852 dm_info->delta_power_index[path] = 0;
1854 dm_info->thermal_avg[path] = 0xff;
1867 u8 cck_gi_u_bnd_msb = 0;
1868 u8 cck_gi_u_bnd_lsb = 0;
1869 u8 cck_gi_l_bnd_msb = 0;
1870 u8 cck_gi_l_bnd_lsb = 0;
1888 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f;
1889 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00,
1900 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000);
1901 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000);
1902 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0);
1903 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000);
1914 #define WLAN_TXQ_RPT_EN 0x1F
1915 #define WLAN_SLOT_TIME 0x09
1916 #define WLAN_PIFS_TIME 0x1C
1917 #define WLAN_SIFS_CCK_CONT_TX 0x0A
1918 #define WLAN_SIFS_OFDM_CONT_TX 0x0E
1919 #define WLAN_SIFS_CCK_TRX 0x0A
1920 #define WLAN_SIFS_OFDM_TRX 0x10
1921 #define WLAN_NAV_MAX 0xC8
1922 #define WLAN_RDG_NAV 0x05
1923 #define WLAN_TXOP_NAV 0x1B
1924 #define WLAN_CCK_RX_TSF 0x30
1925 #define WLAN_OFDM_RX_TSF 0x30
1926 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
1927 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
1928 #define WLAN_DRV_EARLY_INT 0x04
1929 #define WLAN_BCN_CTRL_CLT0 0x10
1930 #define WLAN_BCN_DMA_TIME 0x02
1931 #define WLAN_BCN_MAX_ERR 0xFF
1932 #define WLAN_SIFS_CCK_DUR_TUNE 0x0A
1933 #define WLAN_SIFS_OFDM_DUR_TUNE 0x10
1934 #define WLAN_SIFS_CCK_CTX 0x0A
1935 #define WLAN_SIFS_CCK_IRX 0x0A
1936 #define WLAN_SIFS_OFDM_CTX 0x0E
1937 #define WLAN_SIFS_OFDM_IRX 0x0E
1938 #define WLAN_EIFS_DUR_TUNE 0x40
1939 #define WLAN_EDCA_VO_PARAM 0x002FA226
1940 #define WLAN_EDCA_VI_PARAM 0x005EA328
1941 #define WLAN_EDCA_BE_PARAM 0x005EA42B
1942 #define WLAN_EDCA_BK_PARAM 0x0000A44F
1944 #define WLAN_RX_FILTER0 0xFFFFFFFF
1945 #define WLAN_RX_FILTER2 0xFFFF
1946 #define WLAN_RCR_CFG 0xE400220E
1950 #define WLAN_AMPDU_MAX_TIME 0x70
1951 #define WLAN_RTS_LEN_TH 0xFF
1952 #define WLAN_RTS_TX_TIME_TH 0x08
1953 #define WLAN_MAX_AGG_PKT_LIMIT 0x3f
1954 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x3f
1955 #define WLAN_PRE_TXCNT_TIME_TH 0x1E0
1956 #define FAST_EDCA_VO_TH 0x06
1957 #define FAST_EDCA_VI_TH 0x06
1958 #define FAST_EDCA_BE_TH 0x06
1959 #define FAST_EDCA_BK_TH 0x06
1960 #define WLAN_BAR_RETRY_LIMIT 0x01
1961 #define WLAN_BAR_ACK_TYPE 0x05
1962 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
1963 #define WLAN_RESP_TXRATE 0x84
1964 #define WLAN_ACK_TO 0x21
1965 #define WLAN_ACK_TO_CCK 0x6A
1966 #define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000
1967 #define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504
1968 #define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504
1969 #define WLAN_DATA_RATE_FB_RATE0 0xFE01F010
1970 #define WLAN_DATA_RATE_FB_RATE0_H 0x40000000
1971 #define WLAN_RTS_RATE_FB_RATE1 0x003FF010
1972 #define WLAN_RTS_RATE_FB_RATE1_H 0x40000000
1973 #define WLAN_RTS_RATE_FB_RATE4 0x0600F010
1974 #define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0
1975 #define WLAN_RTS_RATE_FB_RATE5 0x0600F015
1976 #define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0
1977 #define WLAN_MULTI_ADDR 0xFFFFFFFF
1979 #define WLAN_TX_FUNC_CFG1 0x30
1980 #define WLAN_TX_FUNC_CFG2 0x30
1981 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
1982 #define WLAN_MAC_OPT_LB_FUNC1 0x80
1983 #define WLAN_MAC_OPT_FUNC2 0xb0810041
1984 #define WLAN_MAC_INT_MIG_CFG 0x33330000
2001 #define EFUSE_PCB_INFO_OFFSET 0xCA
2038 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
2073 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
2106 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F;
2110 value16 = 0;
2116 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF);
2121 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07);
2129 return 0;
2132 #define FWCD_SIZE_REG_8822C 0x2000
2133 #define FWCD_SIZE_DMEM_8822C 0x10000
2134 #define FWCD_SIZE_IMEM_8822C 0x10000
2135 #define FWCD_SIZE_EMEM_8822C 0x20000
2136 #define FWCD_SIZE_ROM_8822C 0x10000
2158 ret = rtw_dump_reg(rtwdev, 0x0, FWCD_SIZE_REG_8822C);
2174 return 0;
2182 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1);
2183 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1);
2184 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1);
2186 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0);
2193 #define RF18_BAND_2G (0)
2204 u32 rf_reg18 = 0;
2205 u32 rf_rxbb = 0;
2208 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
2229 rf_rxbb = 0x18;
2234 rf_rxbb = 0x10;
2238 rf_rxbb = 0x8;
2244 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01);
2245 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12);
2246 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb);
2247 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00);
2249 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01);
2250 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12);
2251 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb);
2252 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00);
2264 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f);
2265 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2);
2266 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2);
2267 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi);
2268 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi);
2279 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF);
2284 0x5);
2286 0x5);
2288 0x6);
2290 0x6);
2294 0x4);
2296 0x4);
2298 0x0);
2300 0x0);
2304 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969);
2306 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a);
2308 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa);
2310 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0);
2312 0x4962c931);
2313 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3);
2314 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b);
2315 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7);
2316 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0);
2318 0xff012455);
2319 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff);
2321 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284);
2323 0x3e18fec8);
2324 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88);
2325 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4);
2326 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2);
2328 0x00faf0de);
2330 0x00122344);
2332 0x0fffffff);
2335 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
2337 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1);
2343 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22);
2344 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
2347 0x1);
2349 0x1);
2352 0x2);
2354 0x2);
2357 0x3);
2359 0x3);
2363 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494);
2365 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493);
2367 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453);
2369 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452);
2371 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412);
2373 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411);
2378 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B);
2379 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
2380 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0);
2381 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7);
2382 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6);
2383 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
2384 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2385 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
2389 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0));
2390 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5);
2391 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
2392 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
2394 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1);
2395 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2396 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
2399 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa);
2400 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
2401 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
2403 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6);
2404 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
2407 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
2408 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
2409 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1);
2410 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4);
2411 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4);
2412 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
2413 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2414 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
2417 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
2418 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
2419 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2);
2420 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6);
2421 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5);
2422 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
2423 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2424 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
2441 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0);
2442 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0);
2444 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1);
2445 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1);
2449 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0);
2451 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5);
2453 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1);
2459 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0);
2460 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0);
2461 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0);
2462 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0);
2463 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0);
2465 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1);
2466 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1);
2467 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1);
2468 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1);
2469 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1);
2472 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path);
2473 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path);
2486 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
2488 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4);
2491 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc);
2493 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
2502 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11);
2503 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
2505 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12);
2506 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
2509 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33);
2510 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404);
2512 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x32);
2513 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400);
2515 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31);
2516 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400);
2536 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312);
2538 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111);
2540 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312);
2542 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111);
2582 if (channel == 0)
2589 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
2608 u8 evm_dbm = 0;
2647 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
2662 if (rx_evm < 0) {
2664 evm_dbm = 0;
2678 page = *phy_status & 0xf;
2681 case 0:
2701 memset(pkt_stat, 0, sizeof(*pkt_stat));
2740 u32 txref_cck[2] = {0x18a0, 0x41a0};
2741 u32 txref_ofdm[2] = {0x18e8, 0x41e8};
2744 for (path = 0; path < hal->rf_path_num; path++) {
2745 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
2746 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000,
2749 for (path = 0; path < hal->rf_path_num; path++) {
2750 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
2751 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00,
2759 u32 offset_txagc = 0x3a00;
2760 u8 rate_idx = rate & 0xfc;
2765 for (i = 0; i < 4; i++)
2766 pwr_idx[i] = diff_idx[i] & 0x7f;
2768 phy_pwr_idx = pwr_idx[0] |
2773 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0);
2791 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) {
2792 for (j = 0; j < rtw_rate_size[rs]; j++) {
2796 if (rs == 0) {
2797 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0];
2800 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0];
2823 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx);
2833 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx);
2842 return 0;
2876 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2);
2878 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3);
2879 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4);
2881 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5);
2890 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
2892 crc32_cnt = rtw_read32(rtwdev, 0x2c04);
2893 dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
2894 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2895 crc32_cnt = rtw_read32(rtwdev, 0x2c14);
2896 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
2897 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2898 crc32_cnt = rtw_read32(rtwdev, 0x2c10);
2899 dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
2900 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2901 crc32_cnt = rtw_read32(rtwdev, 0x2c0c);
2902 dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
2903 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2905 cca32_cnt = rtw_read32(rtwdev, 0x2c08);
2906 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16);
2907 dm_info->cck_cca_cnt = cca32_cnt & 0xffff;
2912 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0);
2914 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0);
2928 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_CTRL, RFREG_MASK, 0x80010);
2929 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0FA);
2931 rtw_write_rf(rtwdev, RF_PATH_A, RF_AAC_CTRL, RFREG_MASK, 0x80000);
2932 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_AAC, RFREG_MASK, 0x80001);
2933 read_poll_timeout(rtw_read_rf, val, val != 0x1, 1000, 100000,
2934 true, rtwdev, RF_PATH_A, RF_AAC_CTRL, 0x1000);
2935 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0F8);
2936 rtw_write_rf(rtwdev, RF_PATH_B, RF_SYN_CTRL, RFREG_MASK, 0x80010);
2938 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000);
2939 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x4f000);
2941 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000);
2946 struct rtw_iqk_para para = {0};
2958 rtw_write8(rtwdev, REG_IQKSTAT, 0x0);
2968 /* 0x790[5:0]=0x5 */
2969 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
2972 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
2988 rtw_write_rf(rtwdev, RF_PATH_B, RF_MODOPT, 0xfffff, 0x40000);
3003 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun)
3004 rf_0x1 = 0x40021;
3006 rf_0x1 = 0x40000;
3012 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1);
3016 * disable:0x1860[3] = 1, enable:0x1860[3] = 0
3018 * enable "DAC off if GNT_WL = 0" for non-shared-antenna
3019 * disable 0x1c30[22] = 0,
3020 * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1
3024 BIT_ANAPAR_BTPS >> 16, 0);
3029 BIT_DAC_OFF_ENABLE, 0);
3052 BIT_PI_IGNORE_GNT_BT, 0);
3062 BIT_PI_IGNORE_GNT_BT, 0);
3065 BIT_NOMASK_TXBT_ENABLE, 0);
3072 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0);
3073 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0);
3074 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0);
3075 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0);
3076 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0);
3086 coex_rfe->ant_switch_polarity = 0;
3097 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);
3098 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
3099 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
3127 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x22);
3128 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x36);
3129 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x22);
3130 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x36);
3136 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x20);
3137 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x0);
3138 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x20);
3139 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x0);
3147 u8 csi_rsc = 0;
3160 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550);
3217 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70);
3218 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38);
3219 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1);
3220 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77);
3222 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD,
3224 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control);
3233 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3234 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4);
3243 for (i = 0; i < reg_num; i++) {
3256 for (i = 0; i < DPK_RF_REG_NUM; i++) {
3270 for (i = 0; i < DPK_RF_REG_NUM; i++) {
3285 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
3292 dpk_info->dpk_ch = FIELD_GET(0xff, reg);
3293 dpk_info->dpk_bw = FIELD_GET(0x3000, reg);
3298 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
3300 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801);
3302 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
3310 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0);
3312 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0));
3315 dc_i = 0x1000 - dc_i;
3317 dc_q = 0x1000 - dc_q;
3319 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
3320 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0));
3326 return 0;
3333 u16 count = 0;
3335 rtw_write8(rtwdev, 0x522, 0xff);
3336 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2);
3339 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000);
3340 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000);
3364 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3365 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0);
3366 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
3368 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000);
3370 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000);
3371 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4);
3372 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3);
3374 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3375 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b);
3376 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347);
3383 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017);
3386 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
3387 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1);
3388 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_BB_GAIN, 0x0);
3392 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x1);
3393 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0);
3395 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0);
3396 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6);
3397 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
3398 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0);
3401 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
3402 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
3403 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
3406 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2);
3408 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
3410 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1);
3414 return ori_txbb & 0x1f;
3420 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0;
3424 cmd = 0x14 + path;
3427 cmd = 0x16 + path + bw;
3430 cmd = 0x1a + path;
3433 cmd = 0x1c + path + bw;
3436 return 0;
3439 return (cmd << 8) | 0x48;
3445 u8 result = 0;
3450 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1);
3451 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0);
3452 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
3454 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) {
3460 0x8 | (path << 1));
3461 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
3467 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) {
3472 0x8 | (path << 1));
3473 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
3478 rtw_write8(rtwdev, 0x1b10, 0x0);
3487 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3488 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0);
3497 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
3498 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0);
3499 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
3502 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e);
3509 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
3510 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
3511 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001);
3512 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
3513 rtw_write32(rtwdev, 0x1b4c, 0x00080000);
3519 i_val = 0x10000 - i_val;
3521 q_val = 0x10000 - q_val;
3523 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
3532 u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174,
3534 42, 32, 23, 15, 7, 0};
3536 if (val == 0)
3537 return 0;
3558 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3559 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1);
3560 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000);
3562 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0);
3564 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
3572 u8 result = 0;
3591 if (loss < 0x4000000)
3648 if (pga > 0xe)
3649 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
3650 else if (pga > 0xb && pga < 0xf)
3651 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0);
3652 else if (pga < 0xc)
3663 if (pga < 0xc)
3664 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
3665 else if (pga > 0xb && pga < 0xf)
3666 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
3667 else if (pga > 0xe)
3676 u8 txbb_bound[] = {0x1f, 0};
3687 data->limited_pga = 0;
3701 return rtw8822c_gl_state(rtwdev, data, 0);
3725 struct rtw8822c_dpk_data data = {0};
3746 if (coef_i == 0x1000 || coef_i == 0x0fff ||
3747 coef_q == 0x1000 || coef_q == 0x0fff)
3755 u32 reg = 0;
3756 u16 coef_i = 0, coef_q = 0;
3760 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff;
3761 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff;
3763 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1;
3771 0x000400f0, 0x040400f0, 0x080400f0, 0x010400f0, 0x050400f0,
3772 0x090400f0, 0x020400f0, 0x060400f0, 0x0a0400f0, 0x030400f0,
3773 0x070400f0, 0x0b0400f0, 0x0c0400f0, 0x100400f0, 0x0d0400f0,
3774 0x110400f0, 0x0e0400f0, 0x120400f0, 0x0f0400f0, 0x130400f0,
3782 for (i = 0; i < 20; i++) {
3791 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
3794 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0);
3795 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080);
3797 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1);
3798 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080);
3810 for (addr = 0; addr < 20; addr++) {
3811 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]);
3812 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]);
3815 result = 0;
3825 u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64};
3829 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
3830 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
3832 for (addr = 0; addr < 20; addr++) {
3833 if (result == 0) {
3835 coef = 0x04001fff;
3837 coef = 0x00001fff;
3850 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3855 rtw_write8(rtwdev, REG_DPD_AGC, 0x00);
3886 tx_bb = 0;
3907 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3911 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14);
3921 u32 tmp_gs = 0;
3923 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3924 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0);
3925 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
3926 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
3927 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1);
3928 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3929 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf);
3933 0x1066680);
3934 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1);
3937 0x1066680);
3938 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1);
3942 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310);
3943 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310);
3944 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db);
3945 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db);
3946 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
3948 0x05020000 | (BIT(path) << 28));
3950 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c);
3951 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c);
3952 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14);
3953 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14);
3954 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
3956 0x05020008 | (BIT(path) << 28));
3959 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path);
3963 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0);
3964 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3965 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
3966 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0);
3967 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3970 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b);
3972 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b);
3974 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
3991 u32 offset[DPK_RF_PATH_NUM] = {0, 0x58};
3995 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
3996 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
3997 rtw_write32(rtwdev, REG_NCTL0, 0x00001148);
3998 rtw_write32(rtwdev, REG_NCTL0, 0x00001149);
4000 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55);
4002 rtw_write8(rtwdev, 0x1b10, 0x0);
4003 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
4005 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4006 i_scaling = 0x16c00 / dpk_info->dpk_gs[path];
4008 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD,
4011 GENMASK(31, 28), 0x9);
4013 GENMASK(31, 28), 0x1);
4015 GENMASK(31, 28), 0x0);
4017 BIT(14), 0x0);
4027 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
4028 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
4058 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4061 0x8 | (path << 1));
4062 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0);
4064 dpk_info->dpk_txagc[path] = 0;
4065 dpk_info->result[path] = 0;
4066 dpk_info->dpk_gs[path] = 0x5b;
4067 dpk_info->pre_pwsf[path] = 0;
4108 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
4116 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0);
4120 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0);
4132 dpk_info->dpk_ch == 0)
4135 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4137 0x8 | (path << 1));
4139 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000);
4141 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000);
4150 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
4170 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff);
4172 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK) & 0xff);
4191 0x520, 0x820, 0x824, 0x1c3c, 0x1d58, 0x1864,
4192 0x4164, 0x180c, 0x410c, 0x186c, 0x416c,
4193 0x1a14, 0x1e70, 0x80c, 0x1d70, 0x1e7c, 0x18a4, 0x41a4};
4195 0x0, 0x1a, 0x55, 0x63, 0x87, 0x8f, 0xde};
4222 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
4240 u8 thermal_value[DPK_RF_PATH_NUM] = {0};
4243 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0)
4246 for (path = 0; path < DPK_RF_PATH_NUM; path++) {
4256 offset[path] &= 0x7f;
4260 0x8 | (path << 1));
4261 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0),
4273 u32 val = 0;
4318 s32 cfo_avg, cfo_path_sum = 0, cfo_rpt_sum;
4321 for (i = 0; i < path_num; i++) {
4327 cfo_avg = 0;
4332 for (i = 0; i < path_num; i++) {
4333 cfo->cfo_tail[i] = 0;
4334 cfo->cfo_cnt[i] = 0;
4365 s32 cfo_avg = 0;
4385 crystal_cap = clamp_t(s8, crystal_cap, 0, XCAP_MASK);
4393 {0x1ac8, 0x00ff, 0x1ad0, 0x01f},
4394 {0x1ac8, 0xff00, 0x1ad0, 0x3e0}
4397 {0x1acc, 0x00ff, 0x1ad0, 0x01F00000},
4398 {0x1acc, 0xff00, 0x1ad0, 0x3E000000}
4439 "is_linked=%d, bw=%d, nrx=%d, cs_ratio=0x%x, pd_th=0x%x\n",
4446 s8 pd_lvl[CCK_PD_LV_MAX] = {0, 2, 4, 6, 8};
4447 s8 cs_lvl[CCK_PD_LV_MAX] = {0, 2, 2, 2, 4};
4451 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000);
4452 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc);
4473 #define PWR_TRACK_MASK 0x7f
4480 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK,
4484 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK,
4496 if (rtwdev->efuse.thermal_meter[path] == 0xff)
4499 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e);
4524 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
4528 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
4537 if (efuse->power_track_type != 0)
4541 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01);
4542 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00);
4543 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01);
4545 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01);
4546 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00);
4547 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01);
4575 igi = dm_info->igi_history[0];
4603 {0x0086,
4607 RTW_PWR_CMD_WRITE, BIT(0), 0},
4608 {0x0086,
4613 {0x002E,
4618 {0x002D,
4622 RTW_PWR_CMD_WRITE, BIT(0), 0},
4623 {0x007F,
4627 RTW_PWR_CMD_WRITE, BIT(7), 0},
4628 {0x004A,
4632 RTW_PWR_CMD_WRITE, BIT(0), 0},
4633 {0x0005,
4637 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
4638 {0xFFFF,
4641 0,
4642 RTW_PWR_CMD_END, 0, 0},
4646 {0x0000,
4650 RTW_PWR_CMD_WRITE, BIT(5), 0},
4651 {0x0005,
4655 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
4656 {0x0075,
4660 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4661 {0x0006,
4666 {0x0075,
4670 RTW_PWR_CMD_WRITE, BIT(0), 0},
4671 {0xFF1A,
4675 RTW_PWR_CMD_WRITE, 0xFF, 0},
4676 {0x002E,
4680 RTW_PWR_CMD_WRITE, BIT(3), 0},
4681 {0x0006,
4685 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4686 {0x0005,
4690 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
4691 {0x1018,
4696 {0x0005,
4700 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4701 {0x0005,
4705 RTW_PWR_CMD_POLLING, BIT(0), 0},
4706 {0x0074,
4711 {0x0071,
4715 RTW_PWR_CMD_WRITE, BIT(4), 0},
4716 {0x0062,
4722 {0x0061,
4726 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
4727 {0x001F,
4732 {0x00EF,
4737 {0x1045,
4742 {0x0010,
4747 {0x1064,
4752 {0xFFFF,
4755 0,
4756 RTW_PWR_CMD_END, 0, 0},
4760 {0x0093,
4764 RTW_PWR_CMD_WRITE, BIT(3), 0},
4765 {0x001F,
4769 RTW_PWR_CMD_WRITE, 0xFF, 0},
4770 {0x00EF,
4774 RTW_PWR_CMD_WRITE, 0xFF, 0},
4775 {0x1045,
4779 RTW_PWR_CMD_WRITE, BIT(4), 0},
4780 {0xFF1A,
4784 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
4785 {0x0049,
4789 RTW_PWR_CMD_WRITE, BIT(1), 0},
4790 {0x0006,
4794 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4795 {0x0002,
4799 RTW_PWR_CMD_WRITE, BIT(1), 0},
4800 {0x0005,
4805 {0x0005,
4809 RTW_PWR_CMD_POLLING, BIT(1), 0},
4810 {0x0000,
4815 {0xFFFF,
4818 0,
4819 RTW_PWR_CMD_END, 0, 0},
4823 {0x0005,
4828 {0x0007,
4832 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
4833 {0x0067,
4837 RTW_PWR_CMD_WRITE, BIT(5), 0},
4838 {0x004A,
4842 RTW_PWR_CMD_WRITE, BIT(0), 0},
4843 {0x0081,
4847 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
4848 {0x0090,
4852 RTW_PWR_CMD_WRITE, BIT(1), 0},
4853 {0x0092,
4857 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
4858 {0x0093,
4862 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
4863 {0x0005,
4868 {0x0005,
4873 {0x0086,
4877 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4878 {0xFFFF,
4881 0,
4882 RTW_PWR_CMD_END, 0, 0},
4898 {0xFFFF, 0x00,
4905 {0xFFFF, 0x0000,
4912 {0xFFFF, 0x0000,
4919 {0xFFFF, 0x0000,
4937 [0] = RTW_DEF_RFE(8822c, 0, 0),
4938 [1] = RTW_DEF_RFE(8822c, 0, 0),
4939 [2] = RTW_DEF_RFE(8822c, 0, 0),
4940 [3] = RTW_DEF_RFE(8822c, 0, 0),
4941 [4] = RTW_DEF_RFE(8822c, 0, 0),
4942 [5] = RTW_DEF_RFE(8822c, 0, 5),
4943 [6] = RTW_DEF_RFE(8822c, 0, 0),
4947 [0] = { .addr = 0x1d70, .mask = 0x7f },
4948 [1] = { .addr = 0x1d70, .mask = 0x7f00 },
4960 {64, 64, 0, 0, 1},
4961 {64, 64, 64, 0, 1},
5038 {0xffffffff, 0xffffffff}, /* case-0 */
5039 {0x55555555, 0x55555555},
5040 {0x66555555, 0x66555555},
5041 {0xaaaaaaaa, 0xaaaaaaaa},
5042 {0x5a5a5a5a, 0x5a5a5a5a},
5043 {0xfafafafa, 0xfafafafa}, /* case-5 */
5044 {0x6a5a5555, 0xaaaaaaaa},
5045 {0x6a5a56aa, 0x6a5a56aa},
5046 {0x6a5a5a5a, 0x6a5a5a5a},
5047 {0x66555555, 0x5a5a5a5a},
5048 {0x66555555, 0x6a5a5a5a}, /* case-10 */
5049 {0x66555555, 0x6a5a5aaa},
5050 {0x66555555, 0x5a5a5aaa},
5051 {0x66555555, 0x6aaa5aaa},
5052 {0x66555555, 0xaaaa5aaa},
5053 {0x66555555, 0xaaaaaaaa}, /* case-15 */
5054 {0xffff55ff, 0xfafafafa},
5055 {0xffff55ff, 0x6afa5afa},
5056 {0xaaffffaa, 0xfafafafa},
5057 {0xaa5555aa, 0x5a5a5a5a},
5058 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
5059 {0xaa5555aa, 0xaaaaaaaa},
5060 {0xffffffff, 0x5a5a5a5a},
5061 {0xffffffff, 0x5a5a5a5a},
5062 {0xffffffff, 0x55555555},
5063 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
5064 {0x55555555, 0x5a5a5a5a},
5065 {0x55555555, 0xaaaaaaaa},
5066 {0x55555555, 0x6a5a6a5a},
5067 {0x66556655, 0x66556655},
5068 {0x66556aaa, 0x6a5a6aaa}, /*case-30*/
5069 {0xffffffff, 0x5aaa5aaa},
5070 {0x56555555, 0x5a5a5aaa},
5071 {0xdaffdaff, 0xdaffdaff},
5072 {0xddffddff, 0xddffddff},
5077 {0xffffffff, 0xffffffff}, /* case-100 */
5078 {0x55555555, 0x55555555},
5079 {0x66555555, 0x66555555},
5080 {0xaaaaaaaa, 0xaaaaaaaa},
5081 {0x5a5a5a5a, 0x5a5a5a5a},
5082 {0xfafafafa, 0xfafafafa}, /* case-105 */
5083 {0x5afa5afa, 0x5afa5afa},
5084 {0x55555555, 0xfafafafa},
5085 {0x66555555, 0xfafafafa},
5086 {0x66555555, 0x5a5a5a5a},
5087 {0x66555555, 0x6a5a5a5a}, /* case-110 */
5088 {0x66555555, 0xaaaaaaaa},
5089 {0xffff55ff, 0xfafafafa},
5090 {0xffff55ff, 0x5afa5afa},
5091 {0xffff55ff, 0xaaaaaaaa},
5092 {0xffff55ff, 0xffff55ff}, /* case-115 */
5093 {0xaaffffaa, 0x5afa5afa},
5094 {0xaaffffaa, 0xaaaaaaaa},
5095 {0xffffffff, 0xfafafafa},
5096 {0xffffffff, 0x5afa5afa},
5097 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
5098 {0x55ff55ff, 0x5afa5afa},
5099 {0x55ff55ff, 0xaaaaaaaa},
5100 {0x55ff55ff, 0x55ff55ff}
5105 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
5106 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
5107 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
5108 { {0x61, 0x30, 0x03, 0x11, 0x11} },
5109 { {0x61, 0x20, 0x03, 0x11, 0x11} },
5110 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
5111 { {0x61, 0x45, 0x03, 0x11, 0x10} },
5112 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
5113 { {0x61, 0x30, 0x03, 0x11, 0x10} },
5114 { {0x61, 0x20, 0x03, 0x11, 0x10} },
5115 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
5116 { {0x61, 0x08, 0x03, 0x11, 0x14} },
5117 { {0x61, 0x08, 0x03, 0x10, 0x14} },
5118 { {0x51, 0x08, 0x03, 0x10, 0x54} },
5119 { {0x51, 0x08, 0x03, 0x10, 0x55} },
5120 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
5121 { {0x51, 0x45, 0x03, 0x10, 0x50} },
5122 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
5123 { {0x51, 0x30, 0x03, 0x10, 0x50} },
5124 { {0x51, 0x20, 0x03, 0x10, 0x50} },
5125 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
5126 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
5127 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
5128 { {0x55, 0x08, 0x03, 0x10, 0x54} },
5129 { {0x65, 0x10, 0x03, 0x11, 0x10} },
5130 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
5131 { {0x51, 0x08, 0x03, 0x10, 0x50} },
5132 { {0x61, 0x08, 0x03, 0x11, 0x11} }
5137 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
5138 { {0x61, 0x45, 0x03, 0x11, 0x11} },
5139 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
5140 { {0x61, 0x30, 0x03, 0x11, 0x11} },
5141 { {0x61, 0x20, 0x03, 0x11, 0x11} },
5142 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
5143 { {0x61, 0x45, 0x03, 0x11, 0x10} },
5144 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
5145 { {0x61, 0x30, 0x03, 0x11, 0x10} },
5146 { {0x61, 0x20, 0x03, 0x11, 0x10} },
5147 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
5148 { {0x61, 0x08, 0x03, 0x11, 0x14} },
5149 { {0x61, 0x08, 0x03, 0x10, 0x14} },
5150 { {0x51, 0x08, 0x03, 0x10, 0x54} },
5151 { {0x51, 0x08, 0x03, 0x10, 0x55} },
5152 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
5153 { {0x51, 0x45, 0x03, 0x10, 0x50} },
5154 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
5155 { {0x51, 0x30, 0x03, 0x10, 0x50} },
5156 { {0x51, 0x20, 0x03, 0x10, 0x50} },
5157 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
5158 { {0x51, 0x08, 0x03, 0x10, 0x50} }
5164 static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} };
5168 {0, 0, false, 7}, /* for normal */
5169 {0, 16, false, 7}, /* for WL-CPT */
5174 {0, 21, true, 4} /* for gamg hid */
5178 {0, 0, false, 7}, /* for normal */
5179 {0, 16, false, 7}, /* for WL-CPT */
5183 {0, 28, true, 5},
5184 {0, 28, true, 5} /* for gamg hid */
5195 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
5198 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
5201 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
5208 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5211 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5214 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5221 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
5224 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
5227 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
5234 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5237 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5240 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5246 0, 1, 2, 3, 4, 4, 5, 6, 7, 8,
5252 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5258 0, 1, 2, 2, 3, 4, 4, 5, 6, 6,
5264 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5270 0, 1, 2, 3, 4, 5, 5, 6, 7, 8,
5276 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5282 0, 1, 2, 3, 3, 4, 5, 6, 6, 7,
5288 0, 1, 2, 3, 4, 5, 5, 6, 7, 8,
5318 {.addr = 0x84c, .mask = MASKBYTE2}, .offset = 0x80
5321 {.addr = 0x84c, .mask = MASKBYTE3}, .offset = 0x80
5338 {0x1860, BIT(3), RTW_REG_DOMAIN_MAC8},
5339 {0x4160, BIT(3), RTW_REG_DOMAIN_MAC8},
5340 {0x1c32, BIT(6), RTW_REG_DOMAIN_MAC8},
5341 {0x1c38, BIT(28), RTW_REG_DOMAIN_MAC32},
5342 {0, 0, RTW_REG_DOMAIN_NL},
5343 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
5344 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
5345 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
5346 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
5347 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
5348 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
5349 {0, 0, RTW_REG_DOMAIN_NL},
5350 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
5351 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
5352 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
5353 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
5354 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B},
5355 {0, 0, RTW_REG_DOMAIN_NL},
5356 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
5357 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
5358 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
5359 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
5380 .max_power_index = 0x7f,
5384 .dig_min = 0x20,
5391 .sys_func_en = 0xD8,
5400 .rf_base_addr = {0x3c00, 0x4c00},
5401 .rf_sipi_addr = {0x1808, 0x4108},
5430 .coex_para_ver = 0x22020720,
5431 .bt_desired_ver = 0x20,
5453 .bt_afh_span_bw20 = 0x24,
5454 .bt_afh_span_bw40 = 0x36,
5461 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680},