Lines Matching defs:rtwdev
23 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
44 static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
46 struct rtw_efuse *efuse = &rtwdev->efuse;
70 switch (rtw_hci_type(rtwdev)) {
88 static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre)
90 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
91 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON);
92 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
93 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON);
96 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
98 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
101 static void rtw8822c_bb_reset(struct rtw_dev *rtwdev)
103 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB);
104 rtw_write16_clr(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB);
105 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB);
108 static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev,
124 backup[i].val = rtw_read32(rtwdev, addrs[i]);
130 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK);
137 static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev,
145 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C);
151 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val);
156 static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value,
185 static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2)
198 static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
204 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]);
205 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]);
210 static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val)
274 static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value)
281 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n");
287 static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
294 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
298 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) &&
299 rtw8822c_dac_iq_check(rtwdev, qv[i]))
304 static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev,
319 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max);
320 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max);
337 rtw_dbg(rtwdev, RTW_DBG_RFK,
340 rtw_dbg(rtwdev, RTW_DBG_RFK,
344 rtw8822c_dac_iq_sort(rtwdev, iv, qv);
347 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
350 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
358 rtw8822c_dac_iq_offset(rtwdev, iv, i_value);
359 rtw8822c_dac_iq_offset(rtwdev, qv, q_value);
362 static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev,
368 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK);
369 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK);
371 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a);
372 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b);
374 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv);
375 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value);
378 static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev)
380 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff);
381 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2);
382 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3);
383 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e);
384 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0);
385 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0);
386 rtw_write32(rtwdev, 0x1b00, 0x00000008);
387 rtw_write8(rtwdev, 0x1bcc, 0x3f);
388 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
389 rtw_write8(rtwdev, 0x1bcc, 0x3f);
390 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0);
391 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3);
394 static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev,
397 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
403 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path);
419 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0);
421 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041);
422 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
423 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
424 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4);
425 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
426 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000);
427 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000);
429 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i);
430 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003);
431 rtw_write32(rtwdev, 0x1c24, 0x00010002);
432 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
433 rtw_dbg(rtwdev, RTW_DBG_RFK,
446 rtw_write32(rtwdev, base_addr + 0x68, temp);
448 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n",
451 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103);
452 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
453 rtw_dbg(rtwdev, RTW_DBG_RFK,
464 rtw_write32(rtwdev, 0x1c3c, 0x00000003);
465 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
466 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
469 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1);
472 static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path)
474 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
481 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]);
482 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
484 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
485 rtw_write32(rtwdev, 0x1c38, 0xffffffff);
487 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
488 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
489 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
490 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81);
491 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
492 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
493 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81);
494 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
495 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
497 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d);
499 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
500 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
502 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
503 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
505 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) ||
506 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff))
507 rtw_err(rtwdev, "failed to wait for dack ready\n");
508 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
510 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
511 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
512 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
513 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
514 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
517 static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev,
524 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0);
525 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8);
526 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0);
527 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8);
529 rtw_write32(rtwdev, 0x1b00, 0x00000008);
530 rtw_write8(rtwdev, 0x1bcc, 0x03f);
531 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
532 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
533 rtw_write32(rtwdev, 0x1c3c, 0x00088103);
535 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in);
562 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in);
563 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc);
566 static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path,
581 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
582 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
583 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
584 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
585 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81);
586 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
587 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf);
588 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4);
589 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
590 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81);
591 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
592 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf);
593 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4);
594 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
596 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6);
598 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
599 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
601 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
602 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
604 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) ||
605 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc))
606 rtw_err(rtwdev, "failed to write IQ vector to hardware\n");
607 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
609 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3);
610 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
614 rtw_write32(rtwdev, base_addr + 0x68, temp);
615 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
616 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
617 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
639 rtw_dbg(rtwdev, RTW_DBG_RFK,
643 static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path)
647 rtw_write32(rtwdev, base_addr + 0x68, 0x0);
648 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
649 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0);
650 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1);
653 static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev,
656 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
664 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i);
665 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000);
670 static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path)
682 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr);
687 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr);
690 static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev)
692 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
695 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000);
697 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf);
699 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000);
701 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf);
704 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000);
706 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf);
708 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000);
710 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf);
714 static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev)
718 temp[0] = rtw_read32(rtwdev, 0x1860);
719 temp[1] = rtw_read32(rtwdev, 0x4160);
720 temp[2] = rtw_read32(rtwdev, 0x9b4);
723 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
726 rtw_write32_clr(rtwdev, 0x1830, BIT(30));
727 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
728 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A);
731 rtw_write32_clr(rtwdev, 0x4130, BIT(30));
732 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
733 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B);
735 rtw8822c_dac_cal_backup_dck(rtwdev);
736 rtw_write32_set(rtwdev, 0x1830, BIT(30));
737 rtw_write32_set(rtwdev, 0x4130, BIT(30));
739 rtw_write32(rtwdev, 0x1860, temp[0]);
740 rtw_write32(rtwdev, 0x4160, temp[1]);
741 rtw_write32(rtwdev, 0x9b4, temp[2]);
744 static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev)
746 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
749 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19));
751 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val);
753 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val);
755 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19));
757 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val);
759 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val);
761 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19));
763 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val);
765 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val);
767 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19));
769 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val);
771 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val);
774 static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev)
776 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
778 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0);
779 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0);
780 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0);
781 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0);
783 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0);
784 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
785 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1);
786 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1);
788 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0);
789 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
790 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1);
791 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1);
793 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0);
794 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0);
795 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0);
796 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0);
798 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0);
799 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0);
800 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1);
801 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1);
803 rtw8822c_dac_cal_restore_dck(rtwdev);
805 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7);
806 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7);
807 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7);
808 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7);
810 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1);
811 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1);
813 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0);
814 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0);
815 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0);
816 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0);
818 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0);
819 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0);
820 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1);
821 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1);
823 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1);
824 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1);
827 static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev,
833 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0);
834 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2);
836 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6)
844 static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path)
846 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
858 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8))
862 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
864 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value);
865 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i);
866 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1);
869 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
871 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8))
875 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
877 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value);
878 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i);
879 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1);
881 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
883 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0);
884 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0);
885 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0);
886 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0);
891 static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
893 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A))
896 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B))
902 static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
904 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
914 temp[0] = rtw_read32(rtwdev, 0x1860);
915 temp[1] = rtw_read32(rtwdev, 0x4160);
916 temp[2] = rtw_read32(rtwdev, 0x9b4);
918 rtw8822c_dac_cal_restore_prepare(rtwdev);
919 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) ||
920 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) ||
921 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) ||
922 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff))
925 if (!__rtw8822c_dac_cal_restore(rtwdev)) {
926 rtw_err(rtwdev, "failed to restore dack vectors\n");
930 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1);
931 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
932 rtw_write32(rtwdev, 0x1860, temp[0]);
933 rtw_write32(rtwdev, 0x4160, temp[1]);
934 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1);
935 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1);
936 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1);
937 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1);
938 rtw_write32(rtwdev, 0x9b4, temp[2]);
943 static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev)
952 if (rtw8822c_dac_cal_restore(rtwdev))
957 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf);
959 rtw8822c_dac_bb_setting(rtwdev);
962 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a);
964 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A);
965 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc);
969 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a,
975 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A);
978 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b);
980 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B);
981 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc);
985 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b,
991 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B);
993 rtw_write32(rtwdev, 0x1b00, 0x00000008);
994 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
995 rtw_write8(rtwdev, 0x1bcc, 0x0);
996 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
997 rtw_write8(rtwdev, 0x1bcc, 0x0);
999 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf);
1002 rtw8822c_dac_cal_backup(rtwdev);
1004 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a);
1005 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b);
1006 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a);
1007 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b);
1010 static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev)
1015 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15));
1017 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440);
1018 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D);
1019 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440);
1024 static void rtw8822c_set_power_trim(struct rtw_dev *rtwdev, s8 bb_gain[2][8])
1028 rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq); \
1029 rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK, \
1034 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1035 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1);
1051 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0);
1056 static void rtw8822c_power_trim(struct rtw_dev *rtwdev)
1068 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[i], &pg_pwr);
1077 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1078 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path][i],
1088 rtw8822c_set_power_trim(rtwdev, bb_gain);
1090 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL);
1093 static void rtw8822c_thermal_trim(struct rtw_dev *rtwdev)
1098 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1099 rtw_read8_physical_efuse(rtwdev, rf_efuse[path], &pg_therm);
1107 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]);
1111 static void rtw8822c_pa_bias(struct rtw_dev *rtwdev)
1117 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1118 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[path],
1123 rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_2G_MASK, pg_pa_bias);
1125 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1126 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path],
1129 rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_5G_MASK, pg_pa_bias);
1133 static void rtw8822c_rfk_handshake(struct rtw_dev *rtwdev, bool is_before_k)
1135 struct rtw_dm_info *dm = &rtwdev->dm_info;
1141 rtw_dbg(rtwdev, RTW_DBG_RFK,
1147 rtwdev, REG_PMC_DBG_CTRL1,
1150 rtw_dbg(rtwdev, RTW_DBG_RFK,
1156 rtw_fw_inform_rfk_status(rtwdev, true);
1160 rtwdev, REG_ARFR4, BIT_WL_RFK);
1162 rtw_dbg(rtwdev, RTW_DBG_RFK,
1165 rtw_fw_inform_rfk_status(rtwdev, false);
1168 rtwdev, REG_ARFR4,
1171 rtw_dbg(rtwdev, RTW_DBG_RFK,
1174 rtw_dbg(rtwdev, RTW_DBG_RFK,
1179 static void rtw8822c_rfk_power_save(struct rtw_dev *rtwdev,
1184 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1185 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1186 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_PS_EN,
1191 static void rtw8822c_txgapk_backup_bb_reg(struct rtw_dev *rtwdev, const u32 reg[],
1197 reg_backup[i] = rtw_read32(rtwdev, reg[i]);
1199 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Backup BB 0x%x = 0x%x\n",
1204 static void rtw8822c_txgapk_reload_bb_reg(struct rtw_dev *rtwdev,
1211 rtw_write32(rtwdev, reg[i], reg_backup[i]);
1212 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Reload BB 0x%x = 0x%x\n",
1217 static bool check_rf_status(struct rtw_dev *rtwdev, u8 status)
1221 reg_rf0_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A,
1223 reg_rf0_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B,
1232 static void rtw8822c_txgapk_tx_pause(struct rtw_dev *rtwdev)
1237 rtw_write8(rtwdev, REG_TXPAUSE, BIT_AC_QUEUE);
1238 rtw_write32_mask(rtwdev, REG_TX_FIFO, BIT_STOP_TX, 0x2);
1241 2, 5000, false, rtwdev, 2);
1243 rtw_warn(rtwdev, "failed to pause TX\n");
1245 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Tx pause!!\n");
1248 static void rtw8822c_txgapk_bb_dpk(struct rtw_dev *rtwdev, u8 path)
1250 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1252 rtw_write32_mask(rtwdev, REG_ENFN, BIT_IQK_DPK_EN, 0x1);
1253 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2,
1255 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2,
1257 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_EN_IOQ_IQK_DPK, 0x1);
1258 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_TST_IQK2SET_SRC, 0x0);
1259 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x1ff);
1262 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_A,
1264 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x1);
1265 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_A,
1267 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x0);
1269 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_B,
1271 rtw_write32_mask(rtwdev, REG_3WIRE2,
1273 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_B,
1275 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x0);
1277 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x2);
1280 static void rtw8822c_txgapk_afe_dpk(struct rtw_dev *rtwdev, u8 path)
1284 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1291 rtw_err(rtwdev, "[TXGAPK] unknown path %d!!\n", path);
1295 rtw_write32_mask(rtwdev, REG_IQK_CTRL, MASKDWORD, MASKDWORD);
1296 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001);
1297 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001);
1298 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x701f0001);
1299 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x702f0001);
1300 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x703f0001);
1301 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x704f0001);
1302 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705f0001);
1303 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x706f0001);
1304 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707f0001);
1305 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708f0001);
1306 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709f0001);
1307 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70af0001);
1308 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bf0001);
1309 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cf0001);
1310 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70df0001);
1311 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ef0001);
1312 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001);
1313 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001);
1316 static void rtw8822c_txgapk_afe_dpk_restore(struct rtw_dev *rtwdev, u8 path)
1320 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1327 rtw_err(rtwdev, "[TXGAPK] unknown path %d!!\n", path);
1330 rtw_write32_mask(rtwdev, REG_IQK_CTRL, MASKDWORD, 0xffa1005e);
1331 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700b8041);
1332 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70144041);
1333 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70244041);
1334 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70344041);
1335 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70444041);
1336 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705b8041);
1337 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70644041);
1338 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707b8041);
1339 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708b8041);
1340 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709b8041);
1341 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ab8041);
1342 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bb8041);
1343 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cb8041);
1344 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70db8041);
1345 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70eb8041);
1346 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70fb8041);
1349 static void rtw8822c_txgapk_bb_dpk_restore(struct rtw_dev *rtwdev, u8 path)
1351 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1353 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x0);
1354 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TIA_BYPASS, 0x0);
1355 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TXBB, 0x0);
1357 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0);
1358 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1359 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0);
1360 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00);
1361 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x1);
1362 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1363 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0);
1364 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00);
1365 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0);
1366 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x0);
1369 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_A,
1371 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x0);
1372 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_A,
1374 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x3);
1376 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_B,
1378 rtw_write32_mask(rtwdev, REG_3WIRE2,
1380 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_B,
1382 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x3);
1385 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x0);
1386 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_CFIR_EN, 0x5);
1389 static bool _rtw8822c_txgapk_gain_valid(struct rtw_dev *rtwdev, u32 gain)
1398 static void _rtw8822c_txgapk_write_gain_bb_table(struct rtw_dev *rtwdev,
1401 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1405 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1409 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0);
1412 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2);
1415 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3);
1418 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4);
1424 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, MASKBYTE0, 0x88);
1429 if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) {
1434 rtw_dbg(rtwdev, RTW_DBG_RFK,
1441 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN, tmp_3f);
1442 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_I_GAIN, gain);
1443 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x1);
1444 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x0);
1446 rtw_dbg(rtwdev, RTW_DBG_RFK,
1452 static void rtw8822c_txgapk_write_gain_bb_table(struct rtw_dev *rtwdev)
1456 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s channel=%d\n",
1457 __func__, rtwdev->dm_info.gapk.channel);
1460 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1461 _rtw8822c_txgapk_write_gain_bb_table(rtwdev,
1467 static void rtw8822c_txgapk_read_offset(struct rtw_dev *rtwdev, u8 path)
1473 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1482 rtw_warn(rtwdev, "[TXGAPK] wrong path %d\n", path);
1486 rtw_write32_mask(rtwdev, REG_ANTMAP0, BIT_ANT_PATH, path + 1);
1487 rtw_write32_mask(rtwdev, REG_TXLGMAP, MASKDWORD, 0xe4e40000);
1488 rtw_write32_mask(rtwdev, REG_TXANTSEG, BIT_ANTSEG, 0x3);
1489 rtw_write32_mask(rtwdev, path_setting[path], MASK20BITS, 0x33312);
1490 rtw_write32_mask(rtwdev, path_setting[path], BIT_PATH_EN, 0x1);
1491 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x0);
1492 rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT_TXA_TANK, 0x1);
1493 rtw_write_rf(rtwdev, path, RF_IDAC, BIT_TX_MODE, 0x820);
1494 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1495 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0);
1497 rtw_write32_mask(rtwdev, REG_TX_TONE_IDX, MASKBYTE0, 0x018);
1500 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, BIT_2G_SWING);
1502 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, BIT_5G_SWING);
1505 rtw_write32_mask(rtwdev, REG_NCTL0, MASKDWORD, cfg1_1b00[path]);
1506 rtw_write32_mask(rtwdev, REG_NCTL0, MASKDWORD, cfg2_1b00[path]);
1510 rtwdev, REG_RPT_CIP, BIT_RPT_CIP_STATUS);
1512 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x2);
1513 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1514 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_EN, 0x1);
1515 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x12);
1516 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x3);
1517 val = rtw_read32(rtwdev, REG_STAT_RPT);
1528 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x4);
1529 val = rtw_read32(rtwdev, REG_STAT_RPT);
1539 rtw_dbg(rtwdev, RTW_DBG_RFK,
1544 static void rtw8822c_txgapk_calculate_offset(struct rtw_dev *rtwdev, u8 path)
1548 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1552 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s channel=%d\n",
1555 rtw8822c_txgapk_backup_bb_reg(rtwdev, bb_reg,
1559 rtw_write32_mask(rtwdev,
1561 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1562 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f);
1563 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1564 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
1565 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x5000f);
1566 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x0);
1567 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x1);
1568 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0f);
1569 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
1570 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
1571 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
1572 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1);
1574 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x00);
1575 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0);
1577 rtw8822c_txgapk_read_offset(rtwdev, path);
1578 rtw_dbg(rtwdev, RTW_DBG_RFK, "=============================\n");
1581 rtw_write32_mask(rtwdev,
1583 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1584 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f);
1585 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1586 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
1587 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50011);
1588 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x3);
1589 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x3);
1590 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
1591 rtw_write_rf(rtwdev, path,
1593 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x12);
1594 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
1595 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
1596 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1);
1597 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x5);
1599 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0);
1602 rtw_write32_mask(rtwdev,
1605 rtw_write32_mask(rtwdev,
1608 rtw_write32_mask(rtwdev,
1611 rtw8822c_txgapk_read_offset(rtwdev, path);
1612 rtw_dbg(rtwdev, RTW_DBG_RFK, "=============================\n");
1614 rtw8822c_txgapk_reload_bb_reg(rtwdev, bb_reg,
1618 static void rtw8822c_txgapk_rf_restore(struct rtw_dev *rtwdev, u8 path)
1620 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1622 if (path >= rtwdev->hal.rf_path_num)
1625 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x3);
1626 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x0);
1627 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x0);
1630 static u32 rtw8822c_txgapk_cal_gain(struct rtw_dev *rtwdev, u32 gain, s8 offset)
1634 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1636 if (_rtw8822c_txgapk_gain_valid(rtwdev, gain)) {
1638 rtw_dbg(rtwdev, RTW_DBG_RFK,
1647 rtw_dbg(rtwdev, RTW_DBG_RFK,
1654 static void rtw8822c_txgapk_write_tx_gain(struct rtw_dev *rtwdev)
1656 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1661 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1676 rtw_err(rtwdev, "[TXGAPK] unknown channel %d!!\n", channel);
1680 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1685 if (_rtw8822c_txgapk_gain_valid(rtwdev, v))
1693 if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) {
1694 rtw_dbg(rtwdev, RTW_DBG_RFK,
1699 rtw_dbg(rtwdev, RTW_DBG_RFK,
1705 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x10000);
1707 rtw_write_rf(rtwdev, path,
1710 tmp_3f = rtw8822c_txgapk_cal_gain(rtwdev,
1713 rtw_write_rf(rtwdev, path, RF_LUTWD0,
1716 rtw_dbg(rtwdev, RTW_DBG_RFK,
1720 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x0);
1724 static void rtw8822c_txgapk_save_all_tx_gain_table(struct rtw_dev *rtwdev)
1726 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1734 if (rtwdev->dm_info.dm_flags & BIT(RTW_DM_CAP_TXGAPK))
1737 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1740 rtw_dbg(rtwdev, RTW_DBG_RFK,
1742 rtw8822c_txgapk_write_gain_bb_table(rtwdev);
1747 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1748 rf18 = rtw_read_rf(rtwdev, path, RF_CFGCH, RFREG_MASK);
1750 rtw_write32_mask(rtwdev,
1752 rtw_write_rf(rtwdev, path,
1754 rtw_write_rf(rtwdev, path,
1756 rtw_write_rf(rtwdev, path,
1758 rtw_write_rf(rtwdev, path,
1762 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC,
1764 v = rtw_read_rf(rtwdev, path,
1768 rtw_dbg(rtwdev, RTW_DBG_RFK,
1774 rtw_write_rf(rtwdev, path, RF_CFGCH, RFREG_MASK, rf18);
1775 rtw_write32_mask(rtwdev,
1779 rtw8822c_txgapk_write_gain_bb_table(rtwdev);
1783 static void rtw8822c_txgapk(struct rtw_dev *rtwdev)
1786 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1790 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1792 rtw8822c_txgapk_save_all_tx_gain_table(rtwdev);
1795 rtw_dbg(rtwdev, RTW_DBG_RFK,
1800 if (rtwdev->efuse.power_track_type >= 4 &&
1801 rtwdev->efuse.power_track_type <= 7) {
1802 rtw_dbg(rtwdev, RTW_DBG_RFK,
1807 rtw8822c_txgapk_backup_bb_reg(rtwdev, bb_reg,
1809 rtw8822c_txgapk_tx_pause(rtwdev);
1810 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1811 txgapk->channel = rtw_read_rf(rtwdev, path,
1813 rtw8822c_txgapk_bb_dpk(rtwdev, path);
1814 rtw8822c_txgapk_afe_dpk(rtwdev, path);
1815 rtw8822c_txgapk_calculate_offset(rtwdev, path);
1816 rtw8822c_txgapk_rf_restore(rtwdev, path);
1817 rtw8822c_txgapk_afe_dpk_restore(rtwdev, path);
1818 rtw8822c_txgapk_bb_dpk_restore(rtwdev, path);
1820 rtw8822c_txgapk_write_tx_gain(rtwdev);
1821 rtw8822c_txgapk_reload_bb_reg(rtwdev, bb_reg,
1825 static void rtw8822c_do_gapk(struct rtw_dev *rtwdev)
1827 struct rtw_dm_info *dm = &rtwdev->dm_info;
1830 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] feature disable!!!\n");
1833 rtw8822c_rfk_handshake(rtwdev, true);
1834 rtw8822c_txgapk(rtwdev);
1835 rtw8822c_rfk_handshake(rtwdev, false);
1838 static void rtw8822c_rf_init(struct rtw_dev *rtwdev)
1840 rtw8822c_rf_dac_cal(rtwdev);
1841 rtw8822c_rf_x2_check(rtwdev);
1842 rtw8822c_thermal_trim(rtwdev);
1843 rtw8822c_power_trim(rtwdev);
1844 rtw8822c_pa_bias(rtwdev);
1847 static void rtw8822c_pwrtrack_init(struct rtw_dev *rtwdev)
1849 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1859 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
1860 dm_info->thermal_meter_lck = rtwdev->efuse.thermal_meter_k;
1863 static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev)
1865 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1866 struct rtw_hal *hal = &rtwdev->hal;
1875 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN,
1877 rtw_write8_set(rtwdev, REG_RF_CTRL,
1879 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN);
1882 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL);
1885 rtw8822c_header_file_init(rtwdev, true);
1887 rtw_phy_load_tables(rtwdev);
1889 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f;
1890 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00,
1894 rtw8822c_header_file_init(rtwdev, false);
1897 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
1899 rtw_phy_init(rtwdev);
1901 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000);
1902 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000);
1903 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0);
1904 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000);
1909 rtw8822c_rf_init(rtwdev);
1910 rtw8822c_pwrtrack_init(rtwdev);
1912 rtw_bf_phy_init(rtwdev);
2004 static int rtw8822c_mac_init(struct rtw_dev *rtwdev)
2012 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL);
2014 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8);
2015 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);
2017 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE);
2018 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
2019 rtw_write16(rtwdev, REG_RESP_SIFS_CCK,
2021 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM,
2024 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4);
2025 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8);
2026 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8);
2027 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0);
2028 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H);
2029 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1);
2030 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H);
2031 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4);
2032 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H);
2033 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5);
2034 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H);
2036 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
2037 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
2039 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
2040 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
2044 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
2045 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
2047 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
2048 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
2049 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
2050 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
2052 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN);
2053 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC);
2056 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM);
2057 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM);
2058 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM);
2059 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM);
2060 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
2061 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
2062 rtw_write8_set(rtwdev, REG_RD_CTRL + 1,
2067 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL);
2068 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED);
2069 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED);
2071 rtw_write8_set(rtwdev, REG_MISC_CTRL,
2073 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
2074 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
2075 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
2076 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
2077 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
2079 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2081 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
2082 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
2083 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0);
2084 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
2085 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR);
2088 rtw_write32(rtwdev, REG_MAR, WLAN_MULTI_ADDR);
2089 rtw_write32(rtwdev, REG_MAR + 4, WLAN_MULTI_ADDR);
2090 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE);
2091 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO);
2092 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK);
2093 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE);
2094 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX);
2095 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE);
2096 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
2097 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
2098 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
2099 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
2100 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
2101 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
2102 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN);
2103 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
2104 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1);
2107 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F;
2110 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16);
2116 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
2117 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF);
2119 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL);
2123 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
2124 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL,
2128 rtw_write32(rtwdev, REG_INT_MIG, WLAN_MAC_INT_MIG_CFG);
2152 static int rtw8822c_dump_fw_crash(struct rtw_dev *rtwdev)
2159 ret = rtw_dump_reg(rtwdev, 0x0, FWCD_SIZE_REG_8822C);
2162 ret = __dump_fw_8822c(rtwdev, DMEM);
2165 ret = __dump_fw_8822c(rtwdev, IMEM);
2168 ret = __dump_fw_8822c(rtwdev, EMEM);
2171 ret = __dump_fw_8822c(rtwdev, ROM);
2180 static void rtw8822c_rstb_3wire(struct rtw_dev *rtwdev, bool enable)
2183 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1);
2184 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1);
2185 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1);
2187 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0);
2191 static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
2209 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
2211 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK);
2243 rtw8822c_rstb_3wire(rtwdev, false);
2245 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01);
2246 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12);
2247 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb);
2248 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00);
2250 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01);
2251 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12);
2252 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb);
2253 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00);
2255 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18);
2256 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18);
2258 rtw8822c_rstb_3wire(rtwdev, true);
2261 static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev)
2265 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f);
2266 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2);
2267 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2);
2268 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi);
2269 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi);
2272 static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
2276 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
2277 rtw_write32_set(rtwdev, REG_TXF4, BIT(20));
2278 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
2279 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
2280 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF);
2284 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
2286 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
2288 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
2290 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
2294 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
2296 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
2298 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
2300 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
2305 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969);
2307 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a);
2309 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa);
2311 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0);
2312 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
2314 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3);
2315 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b);
2316 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7);
2317 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0);
2318 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
2320 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff);
2322 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284);
2323 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
2325 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88);
2326 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4);
2327 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2);
2328 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD,
2330 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
2332 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD,
2336 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
2338 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1);
2340 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
2341 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
2342 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
2343 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20));
2344 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22);
2345 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
2347 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
2349 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
2352 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
2354 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
2357 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
2359 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
2364 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494);
2366 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493);
2368 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453);
2370 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452);
2372 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412);
2374 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411);
2379 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B);
2380 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
2381 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0);
2382 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7);
2383 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6);
2384 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
2385 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2386 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
2389 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4),
2391 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5);
2392 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
2393 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
2395 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1);
2396 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2397 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
2400 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa);
2401 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
2402 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
2404 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6);
2405 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
2408 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
2409 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
2410 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1);
2411 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4);
2412 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4);
2413 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
2414 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2415 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
2418 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
2419 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
2420 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2);
2421 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6);
2422 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5);
2423 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
2424 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2425 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
2430 static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
2433 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
2434 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
2435 rtw8822c_set_channel_rf(rtwdev, channel, bw);
2436 rtw8822c_toggle_igi(rtwdev);
2439 static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
2442 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0);
2443 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0);
2445 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1);
2446 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1);
2450 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0);
2452 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5);
2454 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1);
2457 static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
2460 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0);
2461 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0);
2462 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0);
2463 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0);
2464 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0);
2466 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1);
2467 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1);
2468 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1);
2469 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1);
2470 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1);
2473 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path);
2474 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path);
2477 static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
2479 rtw8822c_config_cck_rx_path(rtwdev, rx_path);
2480 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path);
2483 static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
2487 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
2489 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4);
2492 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc);
2494 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
2496 rtw8822c_bb_reset(rtwdev);
2499 static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
2503 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11);
2504 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
2506 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12);
2507 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
2510 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33);
2511 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404);
2513 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x32);
2514 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400);
2516 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31);
2517 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400);
2520 rtw8822c_bb_reset(rtwdev);
2523 static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
2528 rtw8822c_config_cck_tx_path(rtwdev, tx_path_cck, is_tx2_path);
2529 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, tx_path_sel_1ss);
2530 rtw8822c_bb_reset(rtwdev);
2533 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
2537 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312);
2539 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111);
2541 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312);
2543 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111);
2545 rtw8822c_config_rx_path(rtwdev, rx_path);
2546 rtw8822c_config_tx_path(rtwdev, tx_path, BB_PATH_A, BB_PATH_A,
2549 rtw8822c_toggle_igi(rtwdev);
2552 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
2555 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2591 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
2602 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
2605 struct rtw_path_div *p_div = &rtwdev->dm_path_div;
2606 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2621 bw = rtwdev->hal.current_band_width;
2651 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
2674 rtw_phy_parsing_cfo(rtwdev, pkt_stat);
2677 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
2686 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
2689 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
2692 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
2698 rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck,
2701 struct rtw_hal *hal = &rtwdev->hal;
2707 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
2708 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000,
2712 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
2713 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00,
2718 static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate,
2735 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0);
2736 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD,
2740 static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev)
2742 struct rtw_hal *hal = &rtwdev->hal;
2752 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm);
2767 rtw8822c_set_tx_power_diff(rtwdev, rate - 3,
2773 static int rtw8822c_set_antenna(struct rtw_dev *rtwdev,
2777 struct rtw_hal *hal = &rtwdev->hal;
2785 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx);
2795 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx);
2802 rtw8822c_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false);
2807 static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
2811 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC);
2813 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr);
2816 static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev)
2818 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2828 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN;
2829 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT);
2831 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1);
2832 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2);
2833 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3);
2834 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4);
2835 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5);
2854 crc32_cnt = rtw_read32(rtwdev, 0x2c04);
2857 crc32_cnt = rtw_read32(rtwdev, 0x2c14);
2860 crc32_cnt = rtw_read32(rtwdev, 0x2c10);
2863 crc32_cnt = rtw_read32(rtwdev, 0x2c0c);
2867 cca32_cnt = rtw_read32(rtwdev, 0x2c08);
2874 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0);
2875 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2);
2876 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0);
2877 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2);
2880 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
2881 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
2882 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
2883 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
2886 static void rtw8822c_do_lck(struct rtw_dev *rtwdev)
2890 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_CTRL, RFREG_MASK, 0x80010);
2891 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0FA);
2893 rtw_write_rf(rtwdev, RF_PATH_A, RF_AAC_CTRL, RFREG_MASK, 0x80000);
2894 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_AAC, RFREG_MASK, 0x80001);
2896 true, rtwdev, RF_PATH_A, RF_AAC_CTRL, 0x1000);
2897 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0F8);
2898 rtw_write_rf(rtwdev, RF_PATH_B, RF_SYN_CTRL, RFREG_MASK, 0x80010);
2900 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000);
2901 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x4f000);
2903 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000);
2906 static void rtw8822c_do_iqk(struct rtw_dev *rtwdev)
2913 rtw_fw_do_iqk(rtwdev, ¶);
2916 20000, 300000, false, rtwdev, REG_RPT_CIP);
2918 rtw_warn(rtwdev, "failed to poll iqk status bit\n");
2920 rtw_write8(rtwdev, REG_IQKSTAT, 0x0);
2924 static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev)
2927 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2931 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
2934 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
2937 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
2938 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
2941 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
2943 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
2945 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
2947 rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL);
2950 rtw_write_rf(rtwdev, RF_PATH_B, RF_MODOPT, 0xfffff, 0x40000);
2953 static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
2955 struct rtw_coex *coex = &rtwdev->coex;
2957 struct rtw_efuse *efuse = &rtwdev->efuse;
2974 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1);
2985 rtw_write8_mask(rtwdev, REG_ANAPAR + 2,
2988 rtw_write8_mask(rtwdev, REG_ANAPAR + 2,
2990 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 1,
2992 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 3,
2999 rtw_write8_mask(rtwdev, REG_IGN_GNTBT4,
3006 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3008 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT,
3013 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3015 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT,
3018 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3023 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3026 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT,
3032 static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
3034 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0);
3035 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0);
3036 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0);
3037 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0);
3038 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0);
3041 static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
3043 struct rtw_coex *coex = &rtwdev->coex;
3045 struct rtw_efuse *efuse = &rtwdev->efuse;
3047 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
3059 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);
3060 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
3061 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
3064 static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
3066 struct rtw_coex *coex = &rtwdev->coex;
3075 static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
3077 struct rtw_coex *coex = &rtwdev->coex;
3086 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n");
3089 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x22);
3090 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x36);
3091 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x22);
3092 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x36);
3095 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n");
3098 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x20);
3099 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x0);
3100 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x20);
3101 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x0);
3105 static void rtw8822c_bf_enable_bfee_su(struct rtw_dev *rtwdev,
3112 rtw_bf_enable_bfee_su(rtwdev, vif, bfee);
3114 tmp6dc = rtw_read32(rtwdev, REG_BBPSF_CTRL) |
3118 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc | BIT(12));
3120 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc & ~BIT(12));
3122 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550);
3125 static void rtw8822c_bf_config_bfee_su(struct rtw_dev *rtwdev,
3130 rtw8822c_bf_enable_bfee_su(rtwdev, vif, bfee);
3132 rtw_bf_remove_bfee_su(rtwdev, bfee);
3135 static void rtw8822c_bf_config_bfee_mu(struct rtw_dev *rtwdev,
3140 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee);
3142 rtw_bf_remove_bfee_mu(rtwdev, bfee);
3145 static void rtw8822c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
3149 rtw8822c_bf_config_bfee_su(rtwdev, vif, bfee, enable);
3151 rtw8822c_bf_config_bfee_mu(rtwdev, vif, bfee, enable);
3153 rtw_warn(rtwdev, "wrong bfee role\n");
3162 void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev,
3171 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data);
3174 static void rtw8822c_dpk_set_gnt_wl(struct rtw_dev *rtwdev, bool is_before_k)
3176 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3179 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70);
3180 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38);
3181 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1);
3182 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77);
3184 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD,
3186 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control);
3191 rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num,
3194 rtw_restore_reg(rtwdev, bckp, reg_num);
3195 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3196 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4);
3200 rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg,
3208 bckp[i].val = rtw_read32(rtwdev, reg[i]);
3212 static void rtw8822c_dpk_backup_rf_registers(struct rtw_dev *rtwdev,
3219 rf_reg_bak[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A,
3221 rf_reg_bak[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B,
3226 static void rtw8822c_dpk_reload_rf_registers(struct rtw_dev *rtwdev,
3233 rtw_write_rf(rtwdev, RF_PATH_A, rf_reg[i], RFREG_MASK,
3235 rtw_write_rf(rtwdev, RF_PATH_B, rf_reg[i], RFREG_MASK,
3240 static void rtw8822c_dpk_information(struct rtw_dev *rtwdev)
3242 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3247 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
3249 reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK);
3258 static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path)
3260 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
3262 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801);
3264 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
3267 static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path)
3272 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0);
3273 dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
3274 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0));
3281 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
3282 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0));
3283 rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8));
3292 static void rtw8822c_dpk_tx_pause(struct rtw_dev *rtwdev)
3297 rtw_write8(rtwdev, 0x522, 0xff);
3298 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2);
3301 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000);
3302 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000);
3308 static void rtw8822c_dpk_mac_bb_setting(struct rtw_dev *rtwdev)
3310 rtw8822c_dpk_tx_pause(rtwdev);
3311 rtw_load_table(rtwdev, &rtw8822c_dpk_mac_bb_tbl);
3314 static void rtw8822c_dpk_afe_setting(struct rtw_dev *rtwdev, bool is_do_dpk)
3317 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_is_dpk_tbl);
3319 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_no_dpk_tbl);
3322 static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev)
3326 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3327 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0);
3328 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
3329 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G)
3330 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000);
3332 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000);
3333 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4);
3334 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3);
3336 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3337 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b);
3338 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347);
3341 static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path)
3345 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017);
3346 ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK);
3348 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
3349 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1);
3350 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_BB_GAIN, 0x0);
3351 rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb);
3353 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) {
3354 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x1);
3355 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0);
3357 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0);
3358 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6);
3359 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
3360 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0);
3363 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
3364 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
3365 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
3367 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80)
3368 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2);
3370 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
3372 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1);
3379 static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path)
3382 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0;
3404 static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action)
3409 rtw8822c_dpk_set_gnt_wl(rtwdev, true);
3412 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1);
3413 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0);
3414 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
3416 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) {
3418 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
3421 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3423 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
3425 dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path);
3426 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd);
3427 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd + 1);
3429 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) {
3431 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
3433 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3435 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
3438 rtw8822c_dpk_set_gnt_wl(rtwdev, false);
3440 rtw_write8(rtwdev, 0x1b10, 0x0);
3445 static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path)
3449 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3450 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0);
3452 dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
3457 static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path)
3459 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
3460 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0);
3461 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
3464 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e);
3467 static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path)
3471 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
3472 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
3473 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001);
3474 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
3475 rtw_write32(rtwdev, 0x1b4c, 0x00080000);
3477 q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD);
3478 i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD);
3485 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
3516 static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path)
3520 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3521 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1);
3522 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000);
3524 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0);
3526 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
3531 static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path,
3537 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
3538 dgain = rtw8822c_dpk_dgain_read(rtwdev, path);
3548 static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path)
3552 loss = rtw8822c_dpk_pas_read(rtwdev, path);
3575 static u8 rtw8822c_gain_check_state(struct rtw_dev *rtwdev,
3580 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN,
3582 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC,
3590 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path,
3605 static u8 rtw8822c_gain_large_state(struct rtw_dev *rtwdev,
3611 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
3613 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0);
3620 static u8 rtw8822c_gain_less_state(struct rtw_dev *rtwdev,
3626 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
3628 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
3635 static u8 rtw8822c_gl_state(struct rtw_dev *rtwdev,
3648 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb);
3654 static u8 rtw8822c_gl_large_state(struct rtw_dev *rtwdev,
3657 return rtw8822c_gl_state(rtwdev, data, 1);
3660 static u8 rtw8822c_gl_less_state(struct rtw_dev *rtwdev,
3663 return rtw8822c_gl_state(rtwdev, data, 0);
3666 static u8 rtw8822c_loss_check_state(struct rtw_dev *rtwdev,
3672 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_GAIN_LOSS);
3673 state = rtw8822c_dpk_agc_loss_chk(rtwdev, path);
3678 static u8 (*dpk_state[])(struct rtw_dev *rtwdev,
3684 static u8 rtw8822c_dpk_pas_agc(struct rtw_dev *rtwdev, u8 path,
3688 u8 (*func)(struct rtw_dev *rtwdev, struct rtw8822c_dpk_data *data);
3697 state = func(rtwdev, &data);
3705 static bool rtw8822c_dpk_coef_iq_check(struct rtw_dev *rtwdev,
3715 static u32 rtw8822c_dpk_coef_transfer(struct rtw_dev *rtwdev)
3720 reg = rtw_read32(rtwdev, REG_STAT_RPT);
3722 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff;
3723 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff;
3739 static void rtw8822c_dpk_coef_tbl_apply(struct rtw_dev *rtwdev, u8 path)
3741 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3745 rtw_write32(rtwdev, REG_RXSRAM_CTL,
3747 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev);
3751 static void rtw8822c_dpk_get_coef(struct rtw_dev *rtwdev, u8 path)
3753 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
3756 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0);
3757 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080);
3759 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1);
3760 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080);
3763 rtw8822c_dpk_coef_tbl_apply(rtwdev, path);
3766 static u8 rtw8822c_dpk_coef_read(struct rtw_dev *rtwdev, u8 path)
3768 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3776 if (rtw8822c_dpk_coef_iq_check(rtwdev, coef_i, coef_q)) {
3784 static void rtw8822c_dpk_coef_write(struct rtw_dev *rtwdev, u8 path, u8 result)
3786 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3791 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
3792 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
3803 rtw_write32(rtwdev, reg[path] + addr * 4, coef);
3807 static void rtw8822c_dpk_fill_result(struct rtw_dev *rtwdev, u32 dpk_txagc,
3810 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3812 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3815 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6));
3817 rtw_write8(rtwdev, REG_DPD_AGC, 0x00);
3820 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC);
3822 rtw8822c_dpk_coef_write(rtwdev, path, result);
3825 static u32 rtw8822c_dpk_gainloss(struct rtw_dev *rtwdev, u8 path)
3827 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3830 ori_txbb = rtw8822c_dpk_rf_setting(rtwdev, path);
3831 ori_txagc = (u8)rtw_read_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_TXAGC);
3833 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3834 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
3835 rtw8822c_dpk_dgain_read(rtwdev, path);
3837 if (rtw8822c_dpk_dc_corr_check(rtwdev, path)) {
3838 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3839 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
3840 rtw8822c_dpk_dc_corr_check(rtwdev, path);
3843 t1 = rtw8822c_dpk_thermal_read(rtwdev, path);
3844 tx_bb = rtw8822c_dpk_pas_agc(rtwdev, path, false, true);
3845 tx_agc_search = rtw8822c_dpk_gainloss_result(rtwdev, path);
3852 rtw_write_rf(rtwdev, path, RF_TX_GAIN, BIT_GAIN_TXBB, tx_bb);
3856 t2 = rtw8822c_dpk_thermal_read(rtwdev, path);
3863 static u8 rtw8822c_dpk_by_path(struct rtw_dev *rtwdev, u32 tx_agc, u8 path)
3867 result = rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DO_DPK);
3869 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3871 result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26));
3873 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14);
3875 rtw8822c_dpk_get_coef(rtwdev, path);
3880 static void rtw8822c_dpk_cal_gs(struct rtw_dev *rtwdev, u8 path)
3882 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3885 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3886 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0);
3887 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
3888 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
3889 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1);
3890 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3891 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf);
3894 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF,
3896 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1);
3898 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF,
3900 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1);
3904 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310);
3905 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310);
3906 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db);
3907 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db);
3908 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
3909 rtw_write32(rtwdev, REG_DPD_CTL15,
3912 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c);
3913 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c);
3914 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14);
3915 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14);
3916 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
3917 rtw_write32(rtwdev, REG_DPD_CTL15,
3921 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path);
3923 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_CAL_PWR);
3925 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0);
3926 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3927 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
3928 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0);
3929 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3932 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b);
3934 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b);
3936 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
3938 tmp_gs = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, BIT_RPT_DGAIN);
3943 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, tmp_gs);
3945 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, tmp_gs);
3950 static void rtw8822c_dpk_cal_coef1(struct rtw_dev *rtwdev)
3952 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3957 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
3958 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
3959 rtw_write32(rtwdev, REG_NCTL0, 0x00001148);
3960 rtw_write32(rtwdev, REG_NCTL0, 0x00001149);
3962 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55);
3964 rtw_write8(rtwdev, 0x1b10, 0x0);
3965 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
3967 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3970 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD,
3972 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
3974 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
3976 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
3978 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0 + offset[path],
3983 static void rtw8822c_dpk_on(struct rtw_dev *rtwdev, u8 path)
3985 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3987 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON);
3989 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3990 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
3993 rtw8822c_dpk_cal_gs(rtwdev, path);
3996 static bool rtw8822c_dpk_check_pass(struct rtw_dev *rtwdev, bool is_fail,
4002 if (rtw8822c_dpk_coef_read(rtwdev, path))
4010 rtw8822c_dpk_fill_result(rtwdev, dpk_txagc, path, result);
4015 static void rtw8822c_dpk_result_reset(struct rtw_dev *rtwdev)
4017 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4020 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4022 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
4024 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0);
4030 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev,
4035 static void rtw8822c_dpk_calibrate(struct rtw_dev *rtwdev, u8 path)
4037 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4041 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk start\n", path);
4043 dpk_txagc = rtw8822c_dpk_gainloss(rtwdev, path);
4045 dpk_fail = rtw8822c_dpk_by_path(rtwdev, dpk_txagc, path);
4047 if (!rtw8822c_dpk_check_pass(rtwdev, dpk_fail, dpk_txagc, path))
4048 rtw_err(rtwdev, "failed to do dpk calibration\n");
4050 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk finish\n", path);
4056 static void rtw8822c_dpk_path_select(struct rtw_dev *rtwdev)
4058 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_A);
4059 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_B);
4060 rtw8822c_dpk_on(rtwdev, RF_PATH_A);
4061 rtw8822c_dpk_on(rtwdev, RF_PATH_B);
4062 rtw8822c_dpk_cal_coef1(rtwdev);
4065 static void rtw8822c_dpk_enable_disable(struct rtw_dev *rtwdev)
4067 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4070 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
4072 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN,
4074 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN,
4078 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0);
4079 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]);
4082 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0);
4083 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]);
4087 static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev)
4089 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4097 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4098 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
4101 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000);
4103 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000);
4105 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]);
4107 rtw8822c_dpk_coef_write(rtwdev, path,
4110 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON);
4112 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
4115 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF,
4118 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF,
4121 rtw8822c_dpk_cal_coef1(rtwdev);
4124 static bool rtw8822c_dpk_reload(struct rtw_dev *rtwdev)
4126 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4132 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff);
4134 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK) & 0xff);
4138 rtw_dbg(rtwdev, RTW_DBG_RFK,
4140 rtw8822c_dpk_reload_data(rtwdev);
4147 static void rtw8822c_do_dpk(struct rtw_dev *rtwdev)
4149 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4161 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] Skip DPK due to DPD PWR off\n");
4163 } else if (rtw8822c_dpk_reload(rtwdev)) {
4170 rtw8822c_dpk_information(rtwdev);
4172 rtw8822c_dpk_backup_registers(rtwdev, bb_reg, DPK_BB_REG_NUM, bckp);
4173 rtw8822c_dpk_backup_rf_registers(rtwdev, rf_reg, rf_reg_backup);
4175 rtw8822c_dpk_mac_bb_setting(rtwdev);
4176 rtw8822c_dpk_afe_setting(rtwdev, true);
4177 rtw8822c_dpk_pre_setting(rtwdev);
4178 rtw8822c_dpk_result_reset(rtwdev);
4179 rtw8822c_dpk_path_select(rtwdev);
4180 rtw8822c_dpk_afe_setting(rtwdev, false);
4181 rtw8822c_dpk_enable_disable(rtwdev);
4183 rtw8822c_dpk_reload_rf_registers(rtwdev, rf_reg, rf_reg_backup);
4184 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
4185 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
4186 rtw8822c_dpk_restore_registers(rtwdev, DPK_BB_REG_NUM, bckp);
4189 static void rtw8822c_phy_calibration(struct rtw_dev *rtwdev)
4191 rtw8822c_rfk_power_save(rtwdev, false);
4192 rtw8822c_do_gapk(rtwdev);
4193 rtw8822c_do_iqk(rtwdev);
4194 rtw8822c_do_dpk(rtwdev);
4195 rtw8822c_rfk_power_save(rtwdev, true);
4198 static void rtw8822c_dpk_track(struct rtw_dev *rtwdev)
4200 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4209 thermal_value[path] = rtw8822c_dpk_thermal_read(rtwdev, path);
4221 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
4223 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0),
4231 static void rtw8822c_set_crystal_cap_reg(struct rtw_dev *rtwdev, u8 crystal_cap)
4233 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4239 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, BIT_XCAP_0, val);
4242 static void rtw8822c_set_crystal_cap(struct rtw_dev *rtwdev, u8 crystal_cap)
4244 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4250 rtw8822c_set_crystal_cap_reg(rtwdev, crystal_cap);
4253 static void rtw8822c_cfo_tracking_reset(struct rtw_dev *rtwdev)
4255 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4260 if (cfo->crystal_cap > rtwdev->efuse.crystal_cap)
4261 rtw8822c_set_crystal_cap(rtwdev, cfo->crystal_cap - 1);
4262 else if (cfo->crystal_cap < rtwdev->efuse.crystal_cap)
4263 rtw8822c_set_crystal_cap(rtwdev, cfo->crystal_cap + 1);
4266 static void rtw8822c_cfo_init(struct rtw_dev *rtwdev)
4268 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4271 cfo->crystal_cap = rtwdev->efuse.crystal_cap;
4276 static s32 rtw8822c_cfo_calc_avg(struct rtw_dev *rtwdev, u8 path_num)
4278 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4302 static void rtw8822c_cfo_need_adjust(struct rtw_dev *rtwdev, s32 cfo_avg)
4304 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4315 if (!rtw_coex_disabled(rtwdev)) {
4317 rtw8822c_set_crystal_cap(rtwdev, rtwdev->efuse.crystal_cap);
4321 static void rtw8822c_cfo_track(struct rtw_dev *rtwdev)
4323 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4325 u8 path_num = rtwdev->hal.rf_path_num;
4329 if (rtwdev->sta_cnt != 1) {
4330 rtw8822c_cfo_tracking_reset(rtwdev);
4338 cfo_avg = rtw8822c_cfo_calc_avg(rtwdev, path_num);
4339 rtw8822c_cfo_need_adjust(rtwdev, cfo_avg);
4348 rtw8822c_set_crystal_cap(rtwdev, (u8)crystal_cap);
4369 rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev,
4377 pd = rtw_read32_mask(rtwdev,
4380 cs = rtw_read32_mask(rtwdev,
4391 rtw_write32_mask(rtwdev,
4395 rtw_write32_mask(rtwdev,
4400 rtw_dbg(rtwdev, RTW_DBG_PHY,
4402 rtw_is_assoc(rtwdev), bw, nrx, cs, pd);
4405 static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
4407 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4413 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000);
4414 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc);
4416 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d) bw=%d nr=%d cck_fa_avg=%d\n",
4428 rtw8822c_phy_cck_pd_set_reg(rtwdev,
4436 static void rtw8822c_pwrtrack_set(struct rtw_dev *rtwdev, u8 rf_path)
4438 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4442 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK,
4446 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK,
4454 static void rtw8822c_pwr_track_stats(struct rtw_dev *rtwdev, u8 path)
4458 if (rtwdev->efuse.thermal_meter[path] == 0xff)
4461 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e);
4462 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, path);
4465 static void rtw8822c_pwr_track_path(struct rtw_dev *rtwdev,
4469 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4472 delta = rtw_phy_pwrtrack_get_delta(rtwdev, path);
4474 rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, path, path,
4476 rtw8822c_pwrtrack_set(rtwdev, path);
4479 static void __rtw8822c_pwr_track(struct rtw_dev *rtwdev)
4484 rtw_phy_config_swing_table(rtwdev, &swing_table);
4486 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
4487 rtw8822c_pwr_track_stats(rtwdev, i);
4488 if (rtw_phy_pwrtrack_need_lck(rtwdev))
4489 rtw8822c_do_lck(rtwdev);
4490 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
4491 rtw8822c_pwr_track_path(rtwdev, &swing_table, i);
4494 static void rtw8822c_pwr_track(struct rtw_dev *rtwdev)
4496 struct rtw_efuse *efuse = &rtwdev->efuse;
4497 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4503 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01);
4504 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00);
4505 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01);
4507 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01);
4508 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00);
4509 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01);
4515 __rtw8822c_pwr_track(rtwdev);
4519 static void rtw8822c_adaptivity_init(struct rtw_dev *rtwdev)
4521 rtw_phy_set_edcca_th(rtwdev, RTW8822C_EDCCA_MAX, RTW8822C_EDCCA_MAX);
4524 rtw_write32_clr(rtwdev, REG_TX_PTCL_CTRL, BIT_DIS_EDCCA);
4525 rtw_write32_set(rtwdev, REG_RD_CTRL, BIT_EDCCA_MSK_CNTDOWN_EN);
4528 rtw_write32_clr(rtwdev, REG_EDCCA_DECISION, BIT_EDCCA_OPTION);
4531 static void rtw8822c_adaptivity(struct rtw_dev *rtwdev)
4533 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4549 rtw_phy_set_edcca_th(rtwdev, l2h, h2l);
4555 struct rtw_dev *rtwdev = container_of(led, struct rtw_dev, led_cdev);
4558 ledcfg = rtw_read32(rtwdev, REG_LED_CFG);
4567 rtw_write32(rtwdev, REG_LED_CFG, ledcfg);
4570 static void rtw8822c_fill_txdesc_checksum(struct rtw_dev *rtwdev,
4574 const struct rtw_chip_info *chip = rtwdev->chip;