Lines Matching +full:0 +full:xc00
13 u8 res4[4]; /* 0xd0 */
15 u8 res5[0x1e];
17 u8 serial[0x0b]; /* 0xf5 */
18 u8 vid; /* 0x100 */
22 u8 mac_addr[ETH_ALEN]; /* 0x107 */
24 u8 vendor_name[0x07];
26 u8 device_name[0x14];
27 u8 res11[0xcf];
28 u8 package_type; /* 0x1fb */
29 u8 res12[0x4];
33 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
41 u8 ltr_cap; /* 0xe3 */
46 u8 res0:2; /* 0xf4 */
69 u8 res4[0x4a]; /* 0xd0 */
70 u8 mac_addr[ETH_ALEN]; /* 0x11a */
75 u8 res0[0x0e];
80 u8 channel_plan; /* 0xb8 */
84 u8 pa_type; /* 0xbc */
85 u8 lna_type_2g[2]; /* 0xbd */
95 u8 rf_antenna_option; /* 0xc9 */
109 /* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */ in _rtw_write32s_mask()
111 rtw_write32_mask(rtwdev, addr + 0x200, mask, data); in _rtw_write32s_mask()
116 BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00); \
119 } while (0)
123 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
127 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
129 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
131 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
133 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
135 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
137 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
139 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
141 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
143 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
145 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
147 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
149 #define RTW8822B_EDCCA_MAX 0x7f
151 #define REG_HTSTFWT 0x800
152 #define REG_RXPSEL 0x808
154 #define REG_TXPSEL 0x80c
155 #define REG_RXCCAMSK 0x814
156 #define REG_CCASEL 0x82c
157 #define REG_PDMFTH 0x830
158 #define REG_CCA2ND 0x838
159 #define REG_L1WT 0x83c
160 #define REG_L1PKWT 0x840
161 #define REG_MRC 0x850
162 #define REG_CLKTRK 0x860
163 #define REG_EDCCA_POW_MA 0x8a0
164 #define BIT_MA_LEVEL GENMASK(1, 0)
165 #define REG_ADCCLK 0x8ac
166 #define REG_ADC160 0x8c4
167 #define REG_ADC40 0x8c8
168 #define REG_EDCCA_DECISION 0x8dc
170 #define REG_CDDTXP 0x93c
171 #define REG_TXPSEL1 0x940
172 #define REG_EDCCA_SOURCE 0x944
174 #define REG_ACBB0 0x948
175 #define REG_ACBBRXFIR 0x94c
176 #define REG_ACGG2TBL 0x958
177 #define REG_RXSB 0xa00
178 #define REG_ADCINI 0xa04
179 #define REG_TXSF2 0xa24
180 #define REG_TXSF6 0xa28
181 #define REG_RXDESC 0xa2c
182 #define REG_ENTXCCK 0xa80
183 #define REG_AGCTR_A 0xc08
184 #define REG_TXDFIR 0xc20
185 #define REG_RXIGI_A 0xc50
186 #define REG_TRSW 0xca0
187 #define REG_RFESEL0 0xcb0
188 #define REG_RFESEL8 0xcb4
189 #define REG_RFECTL 0xcb8
190 #define REG_RFEINV 0xcbc
191 #define REG_AGCTR_B 0xe08
192 #define REG_RXIGI_B 0xe50
193 #define REG_ANTWT 0x1904
194 #define REG_IQKFAILMSK 0x1bf0