Lines Matching +full:tx +full:- +full:swing +full:- +full:low
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
9 #include "tx.h"
26 ether_addr_copy(efuse->addr, map->e.mac_addr);
32 ether_addr_copy(efuse->addr, map->u.mac_addr);
38 ether_addr_copy(efuse->addr, map->s.mac_addr);
43 struct rtw_efuse *efuse = &rtwdev->efuse;
49 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(7));
50 efuse->rfe_option = map->rfe_option;
51 efuse->rf_board_option = map->rf_board_option;
52 efuse->crystal_cap = map->xtal_k;
53 efuse->pa_type_2g = map->pa_type;
54 efuse->pa_type_5g = map->pa_type;
55 efuse->lna_type_2g = map->lna_type_2g[0];
56 efuse->lna_type_5g = map->lna_type_5g[0];
57 efuse->channel_plan = map->channel_plan;
58 efuse->country_code[0] = map->country_code[0];
59 efuse->country_code[1] = map->country_code[1];
60 efuse->bt_setting = map->rf_bt_setting;
61 efuse->regd = map->rf_board_option & 0x7;
62 efuse->thermal_meter[RF_PATH_A] = map->thermal_meter;
63 efuse->thermal_meter_k = map->thermal_meter;
66 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
80 return -ENOTSUPP;
113 u32 swing, table_value;
115 swing = rtw_read32_mask(rtwdev, 0xc1c, 0xffe00000);
118 if (swing == table_value)
127 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
132 dm_info->default_ofdm_index = 24;
134 dm_info->default_ofdm_index = swing_idx;
136 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
137 ewma_thermal_init(&dm_info->avg_thermal[path]);
138 dm_info->delta_power_index[path] = 0;
140 dm_info->pwr_trk_triggered = false;
141 dm_info->pwr_trk_init_trigger = true;
142 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
154 struct rtw_hal *hal = &rtwdev->hal;
170 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
178 rtw8822b_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
268 /* Set beacon cotnrol - enable TSF and other related functions */
292 struct rtw_hal *hal = &rtwdev->hal;
306 if (hal->antenna_rx == BB_PATH_AB ||
307 hal->antenna_tx == BB_PATH_AB) {
308 /* 2TX or 2RX */
310 } else if (hal->antenna_rx == hal->antenna_tx) {
321 struct rtw_hal *hal = &rtwdev->hal;
336 if (hal->antenna_rx == BB_PATH_AB ||
337 hal->antenna_tx == BB_PATH_AB) {
338 /* 2TX or 2RX */
340 } else if (hal->antenna_rx == hal->antenna_tx) {
387 *reg82c = cca_ccut->reg82c[col];
388 *reg830 = cca_ccut->reg830[col];
389 *reg838 = cca_ccut->reg838[col];
424 struct rtw_hal *hal = &rtwdev->hal;
425 struct rtw_efuse *efuse = &rtwdev->efuse;
432 cca_ccut = rfe_info->cca_ccut_2g;
434 if (hal->antenna_rx == BB_PATH_A ||
435 hal->antenna_rx == BB_PATH_B)
440 cca_ccut = rfe_info->cca_ccut_5g;
442 if (hal->antenna_rx == BB_PATH_A ||
443 hal->antenna_rx == BB_PATH_B)
451 switch (rfe_info->fem) {
455 if (rfe_info->ifem_ext)
470 if ((hal->cut_version == RTW_CHIP_VER_CUT_B &&
475 (efuse->rfe_option == 5 && col == CCUT_IDX_2R_5G))
483 if (is_efem_cca && !(hal->cut_version == RTW_CHIP_VER_CUT_B))
513 struct rtw_hal *hal = &rtwdev->hal;
546 rf_reg_be = low_band[(channel - 36) >> 1];
548 rf_reg_be = middle_band[(channel - 100) >> 1];
550 rf_reg_be = high_band[(channel - 149) >> 1];
563 if (hal->rf_type > RF_1T1R)
577 struct rtw_hal *hal = &rtwdev->hal;
581 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2);
583 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2);
588 hal->antenna_rx | (hal->antenna_rx << 4));
614 struct rtw_efuse *efuse = &rtwdev->efuse;
615 u8 rfe_option = efuse->rfe_option;
720 struct rtw_efuse *efuse = &rtwdev->efuse;
723 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info),
724 "rfe_option %d is out of boundary\n", efuse->rfe_option))
727 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option];
735 (*rfe_info->rtw_set_channel_rfe)(rtwdev, channel);
741 struct rtw_efuse *efuse = &rtwdev->efuse;
743 u8 ch = rtwdev->hal.current_channel;
747 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info),
748 "rfe_option %d is out of boundary\n", efuse->rfe_option))
751 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option];
784 if (is_tx2_path || rtwdev->mp_mode) {
811 for (counter = 100; counter > 0; counter--) {
836 (*rfe_info->rtw_set_channel_rfe)(rtwdev, ch);
842 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
843 s8 min_rx_power = -120;
847 pkt_stat->rx_power[RF_PATH_A] = pwdb - 110;
848 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
849 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
850 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
852 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
858 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
860 s8 min_rx_power = -120;
866 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
880 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
881 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110;
882 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2);
883 pkt_stat->bw = bw;
884 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
885 pkt_stat->rx_power[RF_PATH_B],
888 dm_info->curr_rx_rate = pkt_stat->rate;
890 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status);
891 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status);
893 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status);
894 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status);
896 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status);
897 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status);
899 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
900 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
901 dm_info->rssi[path] = rssi;
902 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1;
903 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1;
905 rx_evm = pkt_stat->rx_evm[path];
911 evm_dbm = ((u8)-rx_evm >> 1);
913 dm_info->rx_evm_dbm[path] = evm_dbm;
940 struct rtw_hal *hal = &rtwdev->hal;
948 pwr_index = hal->tx_pwr_tbl[path][rate];
962 struct rtw_hal *hal = &rtwdev->hal;
965 for (path = 0; path < hal->rf_path_num; path++) {
987 struct rtw_hal *hal = &rtwdev->hal;
989 rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n",
993 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx);
994 return -EINVAL;
999 return -EINVAL;
1002 hal->antenna_tx = antenna_tx;
1003 hal->antenna_rx = antenna_rx;
1021 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1032 dm_info->cck_fa_cnt = cck_fa_cnt;
1033 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
1034 dm_info->total_fa_cnt = ofdm_fa_cnt;
1035 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
1038 dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
1039 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1041 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
1042 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1044 dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
1045 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1047 dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
1048 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1051 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16);
1052 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
1055 dm_info->cck_cca_cnt = cca32_cnt & 0xffff;
1056 dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
1109 /* enable PTA (3-wire function form BT side) */
1113 /* enable PTA (tx/rx signal form WiFi side) */
1115 /* wl tx signal to PTA not case EDCCA */
1124 struct rtw_coex *coex = &rtwdev->coex;
1125 struct rtw_coex_dm *coex_dm = &coex->dm;
1126 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1130 if (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status)
1133 coex_dm->cur_switch_status = (ctrl_type << 8) + pos_type;
1135 if (coex_rfe->ant_switch_diversity &&
1139 polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
1152 if (coex_rfe->rfe_module_type != 0x4 &&
1153 coex_rfe->rfe_module_type != 0x2)
1220 struct rtw_coex *coex = &rtwdev->coex;
1221 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1222 struct rtw_efuse *efuse = &rtwdev->efuse;
1225 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
1226 coex_rfe->ant_switch_polarity = 0;
1227 coex_rfe->ant_switch_diversity = false;
1228 if (coex_rfe->rfe_module_type == 0x12 ||
1229 coex_rfe->rfe_module_type == 0x15 ||
1230 coex_rfe->rfe_module_type == 0x16)
1231 coex_rfe->ant_switch_exist = false;
1233 coex_rfe->ant_switch_exist = true;
1235 if (coex_rfe->rfe_module_type == 2 ||
1236 coex_rfe->rfe_module_type == 4) {
1243 coex_rfe->wlg_at_btg = false;
1245 if (efuse->share_ant &&
1246 coex_rfe->ant_switch_exist && !is_ext_fem)
1247 coex_rfe->ant_switch_with_bt = true;
1249 coex_rfe->ant_switch_with_bt = false;
1268 struct rtw_coex *coex = &rtwdev->coex;
1269 struct rtw_coex_dm *coex_dm = &coex->dm;
1274 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
1277 coex_dm->cur_wl_pwr_lvl = wl_pwr;
1279 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power))
1280 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1;
1282 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl];
1290 struct rtw_coex *coex = &rtwdev->coex;
1291 struct rtw_coex_dm *coex_dm = &coex->dm;
1292 /* WL Rx Low gain on */
1305 /* WL Rx Low gain off */
1319 if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
1322 coex_dm->cur_wl_rx_low_gain_en = low_gain;
1324 if (coex_dm->cur_wl_rx_low_gain_en) {
1325 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n");
1335 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n");
1351 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1352 s8 delta_pwr_idx = dm_info->delta_power_index[path];
1353 u8 swing_upper_bound = dm_info->default_ofdm_index + 10;
1357 u8 swing_index = dm_info->default_ofdm_index;
1364 swing_index = dm_info->default_ofdm_index;
1367 swing_index = dm_info->default_ofdm_index +
1368 delta_pwr_idx - tx_pwr_idx_offset;
1372 if (dm_info->default_ofdm_index > abs(delta_pwr_idx))
1374 dm_info->default_ofdm_index + delta_pwr_idx;
1383 rtw_warn(rtwdev, "swing index overflow\n");
1384 swing_index = RTW_TXSCALE_SIZE - 1;
1416 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1418 u8 channel = rtwdev->hal.current_channel;
1419 u8 band_width = rtwdev->hal.current_band_width;
1421 u8 tx_rate = dm_info->tx_rate;
1422 u8 max_pwr_idx = rtwdev->chip->max_power_index;
1429 pwr_idx_offset = max_pwr_idx - tx_pwr_idx;
1438 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1445 power_idx_last = dm_info->delta_power_index[path];
1453 dm_info->delta_power_index[path] = power_idx_cur;
1459 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1465 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff)
1472 if (dm_info->pwr_trk_init_trigger)
1473 dm_info->pwr_trk_init_trigger = false;
1478 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
1488 struct rtw_efuse *efuse = &rtwdev->efuse;
1489 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1491 if (efuse->power_track_type != 0)
1494 if (!dm_info->pwr_trk_triggered) {
1497 dm_info->pwr_trk_triggered = true;
1502 dm_info->pwr_trk_triggered = false;
1528 if (bfee->role == RTW_BFEE_SU)
1530 else if (bfee->role == RTW_BFEE_MU)
1553 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1557 igi = dm_info->igi_history[0];
1558 if (dm_info->edcca_mode == RTW_EDCCA_NORMAL) {
1560 h2l = l2h - EDCCA_L2H_H2L_DIFF_NORMAL;
1562 l2h = min_t(s8, igi, dm_info->l2h_th_ini);
1563 h2l = l2h - EDCCA_L2H_H2L_DIFF;
2179 /* Shared-Antenna Coex Table */
2181 {0xffffffff, 0xffffffff}, /* case-0 */
2186 {0xfafafafa, 0xfafafafa}, /* case-5 */
2191 {0x66555555, 0x6a5a5a5a}, /* case-10 */
2196 {0x66555555, 0xaaaaaaaa}, /* case-15 */
2201 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
2206 {0xffffffff, 0x6a5a5aaa}, /* case-25 */
2211 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
2216 /* Non-Shared-Antenna Coex Table */
2218 {0xffffffff, 0xffffffff}, /* case-100 */
2223 {0xfafafafa, 0xfafafafa}, /* case-105 */
2228 {0x66555555, 0x6a5a5a5a}, /* case-110 */
2233 {0xffff55ff, 0xffff55ff}, /* case-115 */
2238 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
2244 /* Shared-Antenna TDMA */
2246 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
2251 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
2256 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
2261 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
2266 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
2271 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
2276 /* Non-Shared-Antenna TDMA */
2278 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
2279 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
2283 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
2288 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
2293 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
2298 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
2302 /* rssi in percentage % (dbm = % - 100) */
2309 {0, 16, false, 7}, /* for WL-CPT */
2318 {0, 16, false, 7}, /* for WL-CPT */
2567 .l2h_th_ini_ad = -14 + EDCCA_IGI_BASE,