Lines Matching +full:11 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
26 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8822be_efuse_parsing()
32 ether_addr_copy(efuse->addr, map->u.mac_addr); in rtw8822bu_efuse_parsing()
38 ether_addr_copy(efuse->addr, map->s.mac_addr); in rtw8822bs_efuse_parsing()
43 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8822b_read_efuse()
49 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(7)); in rtw8822b_read_efuse()
50 efuse->rfe_option = map->rfe_option; in rtw8822b_read_efuse()
51 efuse->rf_board_option = map->rf_board_option; in rtw8822b_read_efuse()
52 efuse->crystal_cap = map->xtal_k; in rtw8822b_read_efuse()
53 efuse->pa_type_2g = map->pa_type; in rtw8822b_read_efuse()
54 efuse->pa_type_5g = map->pa_type; in rtw8822b_read_efuse()
55 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8822b_read_efuse()
56 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8822b_read_efuse()
57 efuse->channel_plan = map->channel_plan; in rtw8822b_read_efuse()
58 efuse->country_code[0] = map->country_code[0]; in rtw8822b_read_efuse()
59 efuse->country_code[1] = map->country_code[1]; in rtw8822b_read_efuse()
60 efuse->bt_setting = map->rf_bt_setting; in rtw8822b_read_efuse()
61 efuse->regd = map->rf_board_option & 0x7; in rtw8822b_read_efuse()
62 efuse->thermal_meter[RF_PATH_A] = map->thermal_meter; in rtw8822b_read_efuse()
63 efuse->thermal_meter_k = map->thermal_meter; in rtw8822b_read_efuse()
66 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; in rtw8822b_read_efuse()
80 return -ENOTSUPP; in rtw8822b_read_efuse()
89 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3); in rtw8822b_phy_rfe_init()
90 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0); in rtw8822b_phy_rfe_init()
91 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1); in rtw8822b_phy_rfe_init()
95 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3); in rtw8822b_phy_rfe_init()
99 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3); in rtw8822b_phy_rfe_init()
127 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8822b_pwrtrack_init()
132 dm_info->default_ofdm_index = 24; in rtw8822b_pwrtrack_init()
134 dm_info->default_ofdm_index = swing_idx; in rtw8822b_pwrtrack_init()
136 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { in rtw8822b_pwrtrack_init()
137 ewma_thermal_init(&dm_info->avg_thermal[path]); in rtw8822b_pwrtrack_init()
138 dm_info->delta_power_index[path] = 0; in rtw8822b_pwrtrack_init()
140 dm_info->pwr_trk_triggered = false; in rtw8822b_pwrtrack_init()
141 dm_info->pwr_trk_init_trigger = true; in rtw8822b_pwrtrack_init()
142 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; in rtw8822b_pwrtrack_init()
154 struct rtw_hal *hal = &rtwdev->hal; in rtw8822b_phy_set_param()
170 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8822b_phy_set_param()
178 rtw8822b_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, in rtw8822b_phy_set_param()
268 /* Set beacon cotnrol - enable TSF and other related functions */ in rtw8822b_mac_init()
292 struct rtw_hal *hal = &rtwdev->hal; in rtw8822b_set_channel_rfe_efem()
297 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0); in rtw8822b_set_channel_rfe_efem()
301 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0); in rtw8822b_set_channel_rfe_efem()
304 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); in rtw8822b_set_channel_rfe_efem()
306 if (hal->antenna_rx == BB_PATH_AB || in rtw8822b_set_channel_rfe_efem()
307 hal->antenna_tx == BB_PATH_AB) { in rtw8822b_set_channel_rfe_efem()
310 } else if (hal->antenna_rx == hal->antenna_tx) { in rtw8822b_set_channel_rfe_efem()
321 struct rtw_hal *hal = &rtwdev->hal; in rtw8822b_set_channel_rfe_ifem()
333 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); in rtw8822b_set_channel_rfe_ifem()
336 if (hal->antenna_rx == BB_PATH_AB || in rtw8822b_set_channel_rfe_ifem()
337 hal->antenna_tx == BB_PATH_AB) { in rtw8822b_set_channel_rfe_ifem()
340 } else if (hal->antenna_rx == hal->antenna_tx) { in rtw8822b_set_channel_rfe_ifem()
387 *reg82c = cca_ccut->reg82c[col]; in rtw8822b_get_cca_val()
388 *reg830 = cca_ccut->reg830[col]; in rtw8822b_get_cca_val()
389 *reg838 = cca_ccut->reg838[col]; in rtw8822b_get_cca_val()
424 struct rtw_hal *hal = &rtwdev->hal; in rtw8822b_set_channel_cca()
425 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8822b_set_channel_cca()
432 cca_ccut = rfe_info->cca_ccut_2g; in rtw8822b_set_channel_cca()
434 if (hal->antenna_rx == BB_PATH_A || in rtw8822b_set_channel_cca()
435 hal->antenna_rx == BB_PATH_B) in rtw8822b_set_channel_cca()
440 cca_ccut = rfe_info->cca_ccut_5g; in rtw8822b_set_channel_cca()
442 if (hal->antenna_rx == BB_PATH_A || in rtw8822b_set_channel_cca()
443 hal->antenna_rx == BB_PATH_B) in rtw8822b_set_channel_cca()
451 switch (rfe_info->fem) { in rtw8822b_set_channel_cca()
455 if (rfe_info->ifem_ext) in rtw8822b_set_channel_cca()
470 if ((hal->cut_version == RTW_CHIP_VER_CUT_B && in rtw8822b_set_channel_cca()
475 (efuse->rfe_option == 5 && col == CCUT_IDX_2R_5G)) in rtw8822b_set_channel_cca()
483 if (is_efem_cca && !(hal->cut_version == RTW_CHIP_VER_CUT_B)) in rtw8822b_set_channel_cca()
500 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) in rtw8822b_set_channel_rf()
502 #define RF18_BAND_5G (BIT(16) | BIT(8)) in rtw8822b_set_channel_rf()
504 #define RF18_RFSI_MASK (BIT(18) | BIT(17)) in rtw8822b_set_channel_rf()
505 #define RF18_RFSI_GE_CH80 (BIT(17)) in rtw8822b_set_channel_rf()
506 #define RF18_RFSI_GT_CH144 (BIT(18)) in rtw8822b_set_channel_rf()
507 #define RF18_BW_MASK (BIT(11) | BIT(10)) in rtw8822b_set_channel_rf()
508 #define RF18_BW_20M (BIT(11) | BIT(10)) in rtw8822b_set_channel_rf()
509 #define RF18_BW_40M (BIT(11)) in rtw8822b_set_channel_rf()
510 #define RF18_BW_80M (BIT(10)) in rtw8822b_set_channel_rf()
511 #define RFBE_MASK (BIT(17) | BIT(16) | BIT(15)) in rtw8822b_set_channel_rf()
513 struct rtw_hal *hal = &rtwdev->hal; in rtw8822b_set_channel_rf()
546 rf_reg_be = low_band[(channel - 36) >> 1]; in rtw8822b_set_channel_rf()
548 rf_reg_be = middle_band[(channel - 100) >> 1]; in rtw8822b_set_channel_rf()
550 rf_reg_be = high_band[(channel - 149) >> 1]; in rtw8822b_set_channel_rf()
558 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1); in rtw8822b_set_channel_rf()
560 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0); in rtw8822b_set_channel_rf()
563 if (hal->rf_type > RF_1T1R) in rtw8822b_set_channel_rf()
566 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8822b_set_channel_rf()
567 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); in rtw8822b_set_channel_rf()
577 struct rtw_hal *hal = &rtwdev->hal; in rtw8822b_toggle_igi()
581 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2); in rtw8822b_toggle_igi()
583 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2); in rtw8822b_toggle_igi()
588 hal->antenna_rx | (hal->antenna_rx << 4)); in rtw8822b_toggle_igi()
595 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1); in rtw8822b_set_channel_rxdfir()
596 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0); in rtw8822b_set_channel_rxdfir()
597 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8822b_set_channel_rxdfir()
600 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8822b_set_channel_rxdfir()
601 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); in rtw8822b_set_channel_rxdfir()
602 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8822b_set_channel_rxdfir()
605 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8822b_set_channel_rxdfir()
606 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8822b_set_channel_rxdfir()
607 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); in rtw8822b_set_channel_rxdfir()
614 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8822b_set_channel_bb()
615 u8 rfe_option = efuse->rfe_option; in rtw8822b_set_channel_bb()
619 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8822b_set_channel_bb()
620 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); in rtw8822b_set_channel_bb()
621 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); in rtw8822b_set_channel_bb()
636 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); in rtw8822b_set_channel_bb()
637 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); in rtw8822b_set_channel_bb()
638 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8822b_set_channel_bb()
668 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8822b_set_channel_bb()
672 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); in rtw8822b_set_channel_bb()
674 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); in rtw8822b_set_channel_bb()
681 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8822b_set_channel_bb()
689 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8822b_set_channel_bb()
693 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1); in rtw8822b_set_channel_bb()
699 val32 |= ((BIT(6) | RTW_CHANNEL_WIDTH_20)); in rtw8822b_set_channel_bb()
702 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8822b_set_channel_bb()
703 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8822b_set_channel_bb()
708 val32 |= ((BIT(7) | RTW_CHANNEL_WIDTH_20)); in rtw8822b_set_channel_bb()
711 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8822b_set_channel_bb()
712 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8822b_set_channel_bb()
720 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8822b_set_channel()
723 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info), in rtw8822b_set_channel()
724 "rfe_option %d is out of boundary\n", efuse->rfe_option)) in rtw8822b_set_channel()
727 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option]; in rtw8822b_set_channel()
735 (*rfe_info->rtw_set_channel_rfe)(rtwdev, channel); in rtw8822b_set_channel()
741 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8822b_config_trx_mode()
743 u8 ch = rtwdev->hal.current_channel; in rtw8822b_config_trx_mode()
747 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info), in rtw8822b_config_trx_mode()
748 "rfe_option %d is out of boundary\n", efuse->rfe_option)) in rtw8822b_config_trx_mode()
751 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option]; in rtw8822b_config_trx_mode()
763 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3); in rtw8822b_config_trx_mode()
764 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1); in rtw8822b_config_trx_mode()
765 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1); in rtw8822b_config_trx_mode()
784 if (is_tx2_path || rtwdev->mp_mode) { in rtw8822b_config_trx_mode()
790 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0); in rtw8822b_config_trx_mode()
791 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0); in rtw8822b_config_trx_mode()
802 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0); in rtw8822b_config_trx_mode()
803 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0); in rtw8822b_config_trx_mode()
804 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0); in rtw8822b_config_trx_mode()
806 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1); in rtw8822b_config_trx_mode()
807 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1); in rtw8822b_config_trx_mode()
808 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1); in rtw8822b_config_trx_mode()
811 for (counter = 100; counter > 0; counter--) { in rtw8822b_config_trx_mode()
836 (*rfe_info->rtw_set_channel_rfe)(rtwdev, ch); in rtw8822b_config_trx_mode()
842 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in query_phy_status_page0()
843 s8 min_rx_power = -120; in query_phy_status_page0()
847 pkt_stat->rx_power[RF_PATH_A] = pwdb - 110; in query_phy_status_page0()
848 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); in query_phy_status_page0()
849 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; in query_phy_status_page0()
850 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], in query_phy_status_page0()
852 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; in query_phy_status_page0()
858 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in query_phy_status_page1()
860 s8 min_rx_power = -120; in query_phy_status_page1()
866 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) in query_phy_status_page1()
880 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; in query_phy_status_page1()
881 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; in query_phy_status_page1()
882 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); in query_phy_status_page1()
883 pkt_stat->bw = bw; in query_phy_status_page1()
884 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], in query_phy_status_page1()
885 pkt_stat->rx_power[RF_PATH_B], in query_phy_status_page1()
888 dm_info->curr_rx_rate = pkt_stat->rate; in query_phy_status_page1()
890 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); in query_phy_status_page1()
891 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status); in query_phy_status_page1()
893 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); in query_phy_status_page1()
894 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status); in query_phy_status_page1()
896 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); in query_phy_status_page1()
897 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status); in query_phy_status_page1()
899 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { in query_phy_status_page1()
900 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); in query_phy_status_page1()
901 dm_info->rssi[path] = rssi; in query_phy_status_page1()
902 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1; in query_phy_status_page1()
903 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1; in query_phy_status_page1()
905 rx_evm = pkt_stat->rx_evm[path]; in query_phy_status_page1()
911 evm_dbm = ((u8)-rx_evm >> 1); in query_phy_status_page1()
913 dm_info->rx_evm_dbm[path] = evm_dbm; in query_phy_status_page1()
941 struct rtw_hal *hal = &rtwdev->hal; in rtw8822b_set_tx_power_index_by_rate()
948 pwr_index = hal->tx_pwr_tbl[path][rate]; in rtw8822b_set_tx_power_index_by_rate()
962 struct rtw_hal *hal = &rtwdev->hal; in rtw8822b_set_tx_power_index()
966 for (path = 0; path < hal->rf_path_num; path++) { in rtw8822b_set_tx_power_index()
990 struct rtw_hal *hal = &rtwdev->hal; in rtw8822b_set_antenna()
997 return -EINVAL; in rtw8822b_set_antenna()
1002 return -EINVAL; in rtw8822b_set_antenna()
1005 hal->antenna_tx = antenna_tx; in rtw8822b_set_antenna()
1006 hal->antenna_rx = antenna_rx; in rtw8822b_set_antenna()
1024 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8822b_false_alarm_statistics()
1031 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28); in rtw8822b_false_alarm_statistics()
1035 dm_info->cck_fa_cnt = cck_fa_cnt; in rtw8822b_false_alarm_statistics()
1036 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; in rtw8822b_false_alarm_statistics()
1037 dm_info->total_fa_cnt = ofdm_fa_cnt; in rtw8822b_false_alarm_statistics()
1038 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; in rtw8822b_false_alarm_statistics()
1041 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1042 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1044 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1045 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1047 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1048 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1050 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1051 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1054 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); in rtw8822b_false_alarm_statistics()
1055 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; in rtw8822b_false_alarm_statistics()
1058 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1059 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; in rtw8822b_false_alarm_statistics()
1062 rtw_write32_set(rtwdev, 0x9a4, BIT(17)); in rtw8822b_false_alarm_statistics()
1063 rtw_write32_clr(rtwdev, 0x9a4, BIT(17)); in rtw8822b_false_alarm_statistics()
1064 rtw_write32_clr(rtwdev, 0xa2c, BIT(15)); in rtw8822b_false_alarm_statistics()
1065 rtw_write32_set(rtwdev, 0xa2c, BIT(15)); in rtw8822b_false_alarm_statistics()
1066 rtw_write32_set(rtwdev, 0xb58, BIT(0)); in rtw8822b_false_alarm_statistics()
1067 rtw_write32_clr(rtwdev, 0xb58, BIT(0)); in rtw8822b_false_alarm_statistics()
1088 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); in rtw8822b_do_iqk()
1112 /* enable PTA (3-wire function form BT side) */ in rtw8822b_coex_cfg_init()
1127 struct rtw_coex *coex = &rtwdev->coex; in rtw8822b_coex_cfg_ant_switch()
1128 struct rtw_coex_dm *coex_dm = &coex->dm; in rtw8822b_coex_cfg_ant_switch()
1129 struct rtw_coex_rfe *coex_rfe = &coex->rfe; in rtw8822b_coex_cfg_ant_switch()
1133 if (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status) in rtw8822b_coex_cfg_ant_switch()
1136 coex_dm->cur_switch_status = (ctrl_type << 8) + pos_type; in rtw8822b_coex_cfg_ant_switch()
1138 if (coex_rfe->ant_switch_diversity && in rtw8822b_coex_cfg_ant_switch()
1142 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); in rtw8822b_coex_cfg_ant_switch()
1155 if (coex_rfe->rfe_module_type != 0x4 && in rtw8822b_coex_cfg_ant_switch()
1156 coex_rfe->rfe_module_type != 0x2) in rtw8822b_coex_cfg_ant_switch()
1223 struct rtw_coex *coex = &rtwdev->coex; in rtw8822b_coex_cfg_rfe_type()
1224 struct rtw_coex_rfe *coex_rfe = &coex->rfe; in rtw8822b_coex_cfg_rfe_type()
1225 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8822b_coex_cfg_rfe_type()
1228 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; in rtw8822b_coex_cfg_rfe_type()
1229 coex_rfe->ant_switch_polarity = 0; in rtw8822b_coex_cfg_rfe_type()
1230 coex_rfe->ant_switch_diversity = false; in rtw8822b_coex_cfg_rfe_type()
1231 if (coex_rfe->rfe_module_type == 0x12 || in rtw8822b_coex_cfg_rfe_type()
1232 coex_rfe->rfe_module_type == 0x15 || in rtw8822b_coex_cfg_rfe_type()
1233 coex_rfe->rfe_module_type == 0x16) in rtw8822b_coex_cfg_rfe_type()
1234 coex_rfe->ant_switch_exist = false; in rtw8822b_coex_cfg_rfe_type()
1236 coex_rfe->ant_switch_exist = true; in rtw8822b_coex_cfg_rfe_type()
1238 if (coex_rfe->rfe_module_type == 2 || in rtw8822b_coex_cfg_rfe_type()
1239 coex_rfe->rfe_module_type == 4) { in rtw8822b_coex_cfg_rfe_type()
1246 coex_rfe->wlg_at_btg = false; in rtw8822b_coex_cfg_rfe_type()
1248 if (efuse->share_ant && in rtw8822b_coex_cfg_rfe_type()
1249 coex_rfe->ant_switch_exist && !is_ext_fem) in rtw8822b_coex_cfg_rfe_type()
1250 coex_rfe->ant_switch_with_bt = true; in rtw8822b_coex_cfg_rfe_type()
1252 coex_rfe->ant_switch_with_bt = false; in rtw8822b_coex_cfg_rfe_type()
1271 struct rtw_coex *coex = &rtwdev->coex; in rtw8822b_coex_cfg_wl_tx_power()
1272 struct rtw_coex_dm *coex_dm = &coex->dm; in rtw8822b_coex_cfg_wl_tx_power()
1277 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) in rtw8822b_coex_cfg_wl_tx_power()
1280 coex_dm->cur_wl_pwr_lvl = wl_pwr; in rtw8822b_coex_cfg_wl_tx_power()
1282 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power)) in rtw8822b_coex_cfg_wl_tx_power()
1283 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1; in rtw8822b_coex_cfg_wl_tx_power()
1285 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl]; in rtw8822b_coex_cfg_wl_tx_power()
1293 struct rtw_coex *coex = &rtwdev->coex; in rtw8822b_coex_cfg_wl_rx_gain()
1294 struct rtw_coex_dm *coex_dm = &coex->dm; in rtw8822b_coex_cfg_wl_rx_gain()
1322 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) in rtw8822b_coex_cfg_wl_rx_gain()
1325 coex_dm->cur_wl_rx_low_gain_en = low_gain; in rtw8822b_coex_cfg_wl_rx_gain()
1327 if (coex_dm->cur_wl_rx_low_gain_en) { in rtw8822b_coex_cfg_wl_rx_gain()
1328 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n"); in rtw8822b_coex_cfg_wl_rx_gain()
1338 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n"); in rtw8822b_coex_cfg_wl_rx_gain()
1354 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8822b_txagc_swing_offset()
1355 s8 delta_pwr_idx = dm_info->delta_power_index[path]; in rtw8822b_txagc_swing_offset()
1356 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; in rtw8822b_txagc_swing_offset()
1360 u8 swing_index = dm_info->default_ofdm_index; in rtw8822b_txagc_swing_offset()
1367 swing_index = dm_info->default_ofdm_index; in rtw8822b_txagc_swing_offset()
1370 swing_index = dm_info->default_ofdm_index + in rtw8822b_txagc_swing_offset()
1371 delta_pwr_idx - tx_pwr_idx_offset; in rtw8822b_txagc_swing_offset()
1375 if (dm_info->default_ofdm_index > abs(delta_pwr_idx)) in rtw8822b_txagc_swing_offset()
1377 dm_info->default_ofdm_index + delta_pwr_idx; in rtw8822b_txagc_swing_offset()
1387 swing_index = RTW_TXSCALE_SIZE - 1; in rtw8822b_txagc_swing_offset()
1419 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8822b_pwrtrack_set()
1421 u8 channel = rtwdev->hal.current_channel; in rtw8822b_pwrtrack_set()
1422 u8 band_width = rtwdev->hal.current_band_width; in rtw8822b_pwrtrack_set()
1424 u8 tx_rate = dm_info->tx_rate; in rtw8822b_pwrtrack_set()
1425 u8 max_pwr_idx = rtwdev->chip->max_power_index; in rtw8822b_pwrtrack_set()
1432 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; in rtw8822b_pwrtrack_set()
1441 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8822b_phy_pwrtrack_path()
1448 power_idx_last = dm_info->delta_power_index[path]; in rtw8822b_phy_pwrtrack_path()
1456 dm_info->delta_power_index[path] = power_idx_cur; in rtw8822b_phy_pwrtrack_path()
1462 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8822b_phy_pwrtrack()
1468 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff) in rtw8822b_phy_pwrtrack()
1475 if (dm_info->pwr_trk_init_trigger) in rtw8822b_phy_pwrtrack()
1476 dm_info->pwr_trk_init_trigger = false; in rtw8822b_phy_pwrtrack()
1481 for (path = 0; path < rtwdev->hal.rf_path_num; path++) in rtw8822b_phy_pwrtrack()
1491 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8822b_pwr_track()
1492 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8822b_pwr_track()
1494 if (efuse->power_track_type != 0) in rtw8822b_pwr_track()
1497 if (!dm_info->pwr_trk_triggered) { in rtw8822b_pwr_track()
1500 dm_info->pwr_trk_triggered = true; in rtw8822b_pwr_track()
1505 dm_info->pwr_trk_triggered = false; in rtw8822b_pwr_track()
1531 if (bfee->role == RTW_BFEE_SU) in rtw8822b_bf_config_bfee()
1533 else if (bfee->role == RTW_BFEE_MU) in rtw8822b_bf_config_bfee()
1556 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8822b_adaptivity()
1560 igi = dm_info->igi_history[0]; in rtw8822b_adaptivity()
1561 if (dm_info->edcca_mode == RTW_EDCCA_NORMAL) { in rtw8822b_adaptivity()
1563 h2l = l2h - EDCCA_L2H_H2L_DIFF_NORMAL; in rtw8822b_adaptivity()
1565 l2h = min_t(s8, igi, dm_info->l2h_th_ini); in rtw8822b_adaptivity()
1566 h2l = l2h - EDCCA_L2H_H2L_DIFF; in rtw8822b_adaptivity()
1604 RTW_PWR_CMD_WRITE, BIT(0), 0},
1609 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1614 RTW_PWR_CMD_WRITE, BIT(0), 0},
1619 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1642 RTW_PWR_CMD_WRITE, BIT(1), 0},
1647 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1652 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1662 RTW_PWR_CMD_WRITE, BIT(5), 0},
1667 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1672 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1677 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1682 RTW_PWR_CMD_WRITE, BIT(0), 0},
1692 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1697 RTW_PWR_CMD_WRITE, BIT(7), 0},
1702 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1707 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1712 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1717 RTW_PWR_CMD_POLLING, BIT(0), 0},
1722 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1742 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1752 RTW_PWR_CMD_WRITE, BIT(2), 0},
1757 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1762 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1775 RTW_PWR_CMD_WRITE, BIT(2), 0},
1780 RTW_PWR_CMD_WRITE, BIT(3), 0},
1800 RTW_PWR_CMD_WRITE, BIT(1), 0},
1805 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1810 RTW_PWR_CMD_WRITE, BIT(1), 0},
1815 RTW_PWR_CMD_WRITE, BIT(0), 0},
1820 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1825 RTW_PWR_CMD_POLLING, BIT(1), 0},
1830 RTW_PWR_CMD_WRITE, BIT(3), 0},
1835 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1848 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1858 RTW_PWR_CMD_WRITE, BIT(5), 0},
1863 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1868 RTW_PWR_CMD_WRITE, BIT(0), 0},
1873 RTW_PWR_CMD_WRITE, BIT(5), 0},
1878 RTW_PWR_CMD_WRITE, BIT(4), 0},
1883 RTW_PWR_CMD_WRITE, BIT(0), 0},
1888 RTW_PWR_CMD_WRITE, BIT(1), 0},
1893 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1898 RTW_PWR_CMD_WRITE, BIT(2), 0},
1903 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1908 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1913 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1918 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1923 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1928 RTW_PWR_CMD_POLLING, BIT(1), 0},
1933 RTW_PWR_CMD_WRITE, BIT(1), 0},
2184 /* Shared-Antenna Coex Table */
2186 {0xffffffff, 0xffffffff}, /* case-0 */
2191 {0xfafafafa, 0xfafafafa}, /* case-5 */
2196 {0x66555555, 0x6a5a5a5a}, /* case-10 */
2201 {0x66555555, 0xaaaaaaaa}, /* case-15 */
2206 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
2211 {0xffffffff, 0x6a5a5aaa}, /* case-25 */
2216 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
2221 /* Non-Shared-Antenna Coex Table */
2223 {0xffffffff, 0xffffffff}, /* case-100 */
2228 {0xfafafafa, 0xfafafafa}, /* case-105 */
2233 {0x66555555, 0x6a5a5a5a}, /* case-110 */
2238 {0xffff55ff, 0xffff55ff}, /* case-115 */
2243 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
2249 /* Shared-Antenna TDMA */
2251 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
2256 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
2261 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
2266 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
2271 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
2276 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
2281 /* Non-Shared-Antenna TDMA */
2283 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
2284 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
2288 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
2293 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
2298 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
2303 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
2307 /* rssi in percentage % (dbm = % - 100) */
2314 {0, 16, false, 7}, /* for WL-CPT */
2323 {0, 16, false, 7}, /* for WL-CPT */
2360 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2363 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2366 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2373 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2376 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2379 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2386 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2389 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2392 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2399 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2402 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2405 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2412 8, 9, 9, 9, 10, 10, 11, 11, 11, 12
2418 9, 10, 10, 11, 11, 12, 12, 12, 13, 13
2424 8, 9, 9, 9, 10, 10, 11, 11, 11, 12
2430 10, 11, 11, 12, 12, 13, 13, 14, 14, 15
2436 8, 9, 9, 9, 10, 10, 11, 11, 11, 12
2442 9, 10, 10, 11, 11, 12, 12, 12, 13, 13
2448 8, 9, 9, 9, 10, 10, 11, 11, 11, 12
2454 10, 11, 11, 12, 12, 13, 13, 14, 14, 15
2492 {0xcbd, BIT(0), RTW_REG_DOMAIN_MAC8},
2498 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2501 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
2502 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
2503 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2504 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2509 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2548 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),
2573 .l2h_th_ini_ad = -14 + EDCCA_IGI_BASE,