Lines Matching +full:0 +full:x186
54 efuse->lna_type_2g = map->lna_type_2g[0];
55 efuse->lna_type_5g = map->lna_type_5g[0];
57 efuse->country_code[0] = map->country_code[0];
60 efuse->regd = map->rf_board_option & 0x7;
64 for (i = 0; i < 4; i++)
82 return 0;
88 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3);
89 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0);
90 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1);
93 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30);
94 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3);
97 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f);
98 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3);
103 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
104 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
105 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
106 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
111 u8 i = 0;
114 swing = rtw_read32_mask(rtwdev, 0xc1c, 0xffe00000);
115 for (i = 0; i < RTW_TXSCALE_SIZE; i++) {
137 dm_info->delta_power_index[path] = 0;
148 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF);
169 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
170 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap);
171 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap);
187 #define WLAN_SLOT_TIME 0x09
188 #define WLAN_PIFS_TIME 0x19
189 #define WLAN_SIFS_CCK_CONT_TX 0xA
190 #define WLAN_SIFS_OFDM_CONT_TX 0xE
191 #define WLAN_SIFS_CCK_TRX 0x10
192 #define WLAN_SIFS_OFDM_TRX 0x10
193 #define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */
194 #define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */
195 #define WLAN_RDG_NAV 0x05
196 #define WLAN_TXOP_NAV 0x1B
197 #define WLAN_CCK_RX_TSF 0x30
198 #define WLAN_OFDM_RX_TSF 0x30
199 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
200 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
201 #define WLAN_DRV_EARLY_INT 0x04
202 #define WLAN_BCN_DMA_TIME 0x02
204 #define WLAN_RX_FILTER0 0x0FFFFFFF
205 #define WLAN_RX_FILTER2 0xFFFF
206 #define WLAN_RCR_CFG 0xE400220E
210 #define WLAN_AMPDU_MAX_TIME 0x70
211 #define WLAN_RTS_LEN_TH 0xFF
212 #define WLAN_RTS_TX_TIME_TH 0x08
213 #define WLAN_MAX_AGG_PKT_LIMIT 0x20
214 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
215 #define FAST_EDCA_VO_TH 0x06
216 #define FAST_EDCA_VI_TH 0x06
217 #define FAST_EDCA_BE_TH 0x06
218 #define FAST_EDCA_BK_TH 0x06
219 #define WLAN_BAR_RETRY_LIMIT 0x01
220 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
222 #define WLAN_TX_FUNC_CFG1 0x30
223 #define WLAN_TX_FUNC_CFG2 0x30
224 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
225 #define WLAN_MAC_OPT_LB_FUNC1 0x80
226 #define WLAN_MAC_OPT_FUNC2 0xb0810041
259 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
286 return 0;
294 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x705770);
295 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57);
296 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0);
298 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x177517);
299 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75);
300 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0);
303 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0);
308 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501);
311 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500);
314 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005);
324 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x745774);
325 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57);
328 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x477547);
329 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75);
332 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0);
338 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501);
341 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500);
344 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005);
347 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5);
366 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
367 {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
368 {0x87765541, 0x87746341, 0x87765541, 0x87746341}, /*Reg838*/
372 {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/
373 {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa}, /*Reg830*/
374 {0x87766451, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/
378 {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/
379 {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
380 {0x87765541, 0x86666341, 0x87765561, 0x86666361}, /*Reg838*/
475 reg830 = 0x79a0ea28;
483 rtw_write32_mask(rtwdev, REG_L1WT, MASKDWORD, 0x9194b2b9);
486 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4);
489 static const u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6,
490 0x5, 0x0, 0x0, 0x7, 0x6, 0x6};
491 static const u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0,
492 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6,
493 0x6, 0x5, 0x0, 0x0, 0x7};
494 static const u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0,
495 0x7, 0x7, 0x6, 0x5, 0x5, 0x0};
500 #define RF18_BAND_2G (0)
515 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
543 rf_reg_be = 0x0;
555 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */
557 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1);
559 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0);
561 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);
563 rtw_write_rf(rtwdev, RF_PATH_B, 0x18, RFREG_MASK, rf_reg18);
565 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
579 igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f);
580 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2);
581 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi);
582 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2);
583 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi);
585 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0);
594 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1);
595 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0);
596 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
599 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
600 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
601 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
604 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
605 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
606 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
618 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
619 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
620 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
621 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
623 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x0);
624 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);
626 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x00006577);
627 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
629 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x384f6577);
630 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525);
633 rtw_write32_mask(rtwdev, REG_RFEINV, 0x300, 0x2);
635 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
636 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
637 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
638 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 34);
641 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x1);
643 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x2);
645 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x3);
648 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);
650 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);
652 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);
654 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);
656 rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1);
663 val32 &= 0xFFCFFC00;
667 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
676 val32 &= 0xFF3FF300;
677 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_40);
680 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
684 val32 &= 0xFCEFCF00;
685 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_80);
688 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
691 rtw_write32_mask(rtwdev, REG_L1PKWT, 0x0000f000, 0x6);
692 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1);
697 val32 &= 0xEFEEFE00;
701 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
702 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
706 val32 &= 0xEFFEFF00;
710 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
711 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
753 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231);
755 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111);
758 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231);
760 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111);
762 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3);
763 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1);
764 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1);
767 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x001);
768 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x8);
770 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x002);
771 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x4);
775 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x01);
777 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x43);
784 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x043);
785 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0xc);
789 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0);
790 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0);
793 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x0);
795 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x5);
801 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0);
802 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0);
803 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0);
805 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1);
806 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1);
807 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1);
810 for (counter = 100; counter > 0; counter--) {
813 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000);
814 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001);
817 rf_reg33 = rtw_read_rf(rtwdev, RF_PATH_A, 0x33, RFREG_MASK);
819 if (rf_reg33 == 0x00001)
823 if (WARN(counter <= 0, "write RF mode table fail\n"))
826 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000);
827 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001);
828 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x00034);
829 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x4080c);
830 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000);
831 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000);
861 u8 evm_dbm = 0;
898 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
906 if (rx_evm < 0) {
908 evm_dbm = 0;
921 page = *phy_status & 0xf;
924 case 0:
944 memset(pkt_stat, 0, sizeof(*pkt_stat));
981 static const u32 offset_txagc[2] = {0x1d00, 0x1d80};
986 for (j = 0; j < rtw_rate_size[rs]; j++) {
989 shift = rate & 0x3;
991 if (shift == 0x3) {
992 rate_idx = rate & 0xfc;
995 phy_pwr_idx = 0;
1005 for (path = 0; path < hal->rf_path_num; path++) {
1006 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
1029 rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n",
1033 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx);
1038 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx);
1047 return 0;
1068 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28);
1069 cck_fa_cnt = rtw_read16(rtwdev, 0xa5c);
1070 ofdm_fa_cnt = rtw_read16(rtwdev, 0xf48);
1075 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
1077 crc32_cnt = rtw_read32(rtwdev, 0xf04);
1078 dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
1079 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1080 crc32_cnt = rtw_read32(rtwdev, 0xf14);
1081 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
1082 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1083 crc32_cnt = rtw_read32(rtwdev, 0xf10);
1084 dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
1085 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1086 crc32_cnt = rtw_read32(rtwdev, 0xf0c);
1087 dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
1088 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1090 cca32_cnt = rtw_read32(rtwdev, 0xf08);
1091 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16);
1094 cca32_cnt = rtw_read32(rtwdev, 0xfcc);
1095 dm_info->cck_cca_cnt = cca32_cnt & 0xffff;
1099 rtw_write32_set(rtwdev, 0x9a4, BIT(17));
1100 rtw_write32_clr(rtwdev, 0x9a4, BIT(17));
1101 rtw_write32_clr(rtwdev, 0xa2c, BIT(15));
1102 rtw_write32_set(rtwdev, 0xa2c, BIT(15));
1103 rtw_write32_set(rtwdev, 0xb58, BIT(0));
1104 rtw_write32_clr(rtwdev, 0xb58, BIT(0));
1110 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0};
1117 for (counter = 0; counter < 300; counter++) {
1119 if (rf_reg == 0xabcde)
1123 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);
1126 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
1128 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n",
1143 /* 0x790[5:0]=0x5 */
1144 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
1147 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
1168 u8 regval = 0;
1184 /* 0x4c[23] = 0 */
1185 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1186 /* 0x4c[24] = 1 */
1187 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1189 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77);
1192 if (coex_rfe->rfe_module_type != 0x4 &&
1193 coex_rfe->rfe_module_type != 0x2)
1194 regval = 0x3;
1196 regval = (!polarity_inverse ? 0x2 : 0x1);
1198 regval = (!polarity_inverse ? 0x2 : 0x1);
1200 regval = (!polarity_inverse ? 0x1 : 0x2);
1206 /* 0x4c[23] = 0 */
1207 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1208 /* 0x4c[24] = 1 */
1209 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1211 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66);
1213 regval = (!polarity_inverse ? 0x2 : 0x1);
1217 /* 0x4c[23] = 0 */
1218 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1219 /* 0x4c[24] = 1 */
1220 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1221 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88);
1224 /* 0x4c[23] = 1 */
1225 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1);
1227 regval = (!polarity_inverse ? 0x0 : 0x1);
1231 /* 0x4c[23] = 0 */
1232 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1233 /* 0x4c[24] = 1 */
1234 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1237 /* 0x4c[23] = 0 */
1238 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1239 /* 0x4c[24] = 0 */
1240 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0);
1251 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0);
1252 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0);
1253 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0);
1254 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0);
1255 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0);
1266 coex_rfe->ant_switch_polarity = 0;
1268 if (coex_rfe->rfe_module_type == 0x12 ||
1269 coex_rfe->rfe_module_type == 0x15 ||
1270 coex_rfe->rfe_module_type == 0x16)
1292 rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff);
1293 rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0);
1294 rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0);
1297 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0);
1300 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
1303 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
1310 static const u16 reg_addr[] = {0xc58, 0xe58};
1311 static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8};
1324 for (i = 0; i < ARRAY_SIZE(reg_addr); i++)
1325 rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr);
1334 0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003,
1335 0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003,
1336 0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003,
1337 0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003,
1338 0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003,
1339 0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003,
1340 0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003,
1341 0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003,
1342 0x007e0403
1347 0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003,
1348 0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003,
1349 0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003,
1350 0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003,
1351 0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003,
1352 0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003,
1353 0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003,
1354 0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003,
1355 0x007e0403
1366 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++)
1370 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1);
1371 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f);
1372 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1);
1373 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f);
1376 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++)
1377 rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]);
1380 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4);
1381 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0);
1382 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4);
1383 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0);
1394 u8 swing_lower_bound = 0;
1395 u8 max_tx_pwr_idx_offset = 0xf;
1396 s8 agc_index = 0;
1401 if (delta_pwr_idx >= 0) {
1419 agc_index = 0;
1438 reg1 = 0xc94;
1439 reg2 = 0xc1c;
1441 reg1 = 0xe94;
1442 reg2 = 0xe1c;
1505 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff)
1508 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1518 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
1531 if (efuse->power_track_type != 0)
1536 GENMASK(17, 16), 0x03);
1585 rtw_write32_mask(rtwdev, REG_EDCCA_POW_MA, BIT_MA_LEVEL, 0);
1597 igi = dm_info->igi_history[0];
1619 {0x0086,
1623 RTW_PWR_CMD_WRITE, BIT(0), 0},
1624 {0x0086,
1629 {0x004A,
1633 RTW_PWR_CMD_WRITE, BIT(0), 0},
1634 {0x0005,
1638 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1639 {0x0300,
1643 RTW_PWR_CMD_WRITE, 0xFF, 0},
1644 {0x0301,
1648 RTW_PWR_CMD_WRITE, 0xFF, 0},
1649 {0xFFFF,
1652 0,
1653 RTW_PWR_CMD_END, 0, 0},
1657 {0x0012,
1661 RTW_PWR_CMD_WRITE, BIT(1), 0},
1662 {0x0012,
1666 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1667 {0x0020,
1671 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1672 {0x0001,
1677 {0x0000,
1681 RTW_PWR_CMD_WRITE, BIT(5), 0},
1682 {0x0005,
1686 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1687 {0x0075,
1691 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1692 {0x0006,
1697 {0x0075,
1701 RTW_PWR_CMD_WRITE, BIT(0), 0},
1702 {0xFF1A,
1706 RTW_PWR_CMD_WRITE, 0xFF, 0},
1707 {0x0006,
1711 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1712 {0x0005,
1716 RTW_PWR_CMD_WRITE, BIT(7), 0},
1717 {0x0005,
1721 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1722 {0x10C3,
1726 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1727 {0x0005,
1731 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1732 {0x0005,
1736 RTW_PWR_CMD_POLLING, BIT(0), 0},
1737 {0x0020,
1742 {0x10A8,
1746 RTW_PWR_CMD_WRITE, 0xFF, 0},
1747 {0x10A9,
1751 RTW_PWR_CMD_WRITE, 0xFF, 0xef},
1752 {0x10AA,
1756 RTW_PWR_CMD_WRITE, 0xFF, 0x0c},
1757 {0x0068,
1762 {0x0029,
1766 RTW_PWR_CMD_WRITE, 0xFF, 0xF9},
1767 {0x0024,
1771 RTW_PWR_CMD_WRITE, BIT(2), 0},
1772 {0x0074,
1777 {0x00AF,
1782 {0xFFFF,
1785 0,
1786 RTW_PWR_CMD_END, 0, 0},
1790 {0x0003,
1794 RTW_PWR_CMD_WRITE, BIT(2), 0},
1795 {0x0093,
1799 RTW_PWR_CMD_WRITE, BIT(3), 0},
1800 {0x001F,
1804 RTW_PWR_CMD_WRITE, 0xFF, 0},
1805 {0x00EF,
1809 RTW_PWR_CMD_WRITE, 0xFF, 0},
1810 {0xFF1A,
1814 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
1815 {0x0049,
1819 RTW_PWR_CMD_WRITE, BIT(1), 0},
1820 {0x0006,
1824 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1825 {0x0002,
1829 RTW_PWR_CMD_WRITE, BIT(1), 0},
1830 {0x10C3,
1834 RTW_PWR_CMD_WRITE, BIT(0), 0},
1835 {0x0005,
1840 {0x0005,
1844 RTW_PWR_CMD_POLLING, BIT(1), 0},
1845 {0x0020,
1849 RTW_PWR_CMD_WRITE, BIT(3), 0},
1850 {0x0000,
1855 {0xFFFF,
1858 0,
1859 RTW_PWR_CMD_END, 0, 0},
1863 {0x0005,
1868 {0x0007,
1872 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1873 {0x0067,
1877 RTW_PWR_CMD_WRITE, BIT(5), 0},
1878 {0x0005,
1883 {0x004A,
1887 RTW_PWR_CMD_WRITE, BIT(0), 0},
1888 {0x0067,
1892 RTW_PWR_CMD_WRITE, BIT(5), 0},
1893 {0x0067,
1897 RTW_PWR_CMD_WRITE, BIT(4), 0},
1898 {0x004F,
1902 RTW_PWR_CMD_WRITE, BIT(0), 0},
1903 {0x0067,
1907 RTW_PWR_CMD_WRITE, BIT(1), 0},
1908 {0x0046,
1913 {0x0067,
1917 RTW_PWR_CMD_WRITE, BIT(2), 0},
1918 {0x0046,
1923 {0x0062,
1928 {0x0081,
1932 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1933 {0x0005,
1938 {0x0086,
1942 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1943 {0x0086,
1947 RTW_PWR_CMD_POLLING, BIT(1), 0},
1948 {0x0090,
1952 RTW_PWR_CMD_WRITE, BIT(1), 0},
1953 {0x0044,
1957 RTW_PWR_CMD_WRITE, 0xFF, 0},
1958 {0x0040,
1962 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1963 {0x0041,
1967 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1968 {0x0042,
1972 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1973 {0xFFFF,
1976 0,
1977 RTW_PWR_CMD_END, 0, 0},
1993 {0xFFFF, 0x00,
2000 {0x0001, 0xA841,
2004 {0xFFFF, 0x0000,
2011 {0x0001, 0xA841,
2015 {0x0002, 0x60C6,
2019 {0x0008, 0x3596,
2023 {0x0009, 0x321C,
2027 {0x000A, 0x9623,
2031 {0x0020, 0x94FF,
2035 {0x0021, 0xFFCF,
2039 {0x0026, 0xC006,
2043 {0x0029, 0xFF0E,
2047 {0x002A, 0x1840,
2051 {0xFFFF, 0x0000,
2058 {0x0001, 0xA841,
2062 {0x0002, 0x60C6,
2066 {0x0008, 0x3597,
2070 {0x0009, 0x321C,
2074 {0x000A, 0x9623,
2078 {0x0020, 0x94FF,
2082 {0x0021, 0xFFCF,
2086 {0x0026, 0xC006,
2090 {0x0029, 0xFF0E,
2094 {0x002A, 0x3040,
2098 {0xFFFF, 0x0000,
2117 [3] = RTW_DEF_RFE(8822b, 3, 0),
2122 [0] = { .addr = 0xc50, .mask = 0x7f },
2123 [1] = { .addr = 0xe50, .mask = 0x7f },
2135 {64, 64, 0, 0, 1},
2136 {64, 64, 64, 0, 1},
2206 {0xffffffff, 0xffffffff}, /* case-0 */
2207 {0x55555555, 0x55555555},
2208 {0x66555555, 0x66555555},
2209 {0xaaaaaaaa, 0xaaaaaaaa},
2210 {0x5a5a5a5a, 0x5a5a5a5a},
2211 {0xfafafafa, 0xfafafafa}, /* case-5 */
2212 {0x6a5a5555, 0xaaaaaaaa},
2213 {0x6a5a56aa, 0x6a5a56aa},
2214 {0x6a5a5a5a, 0x6a5a5a5a},
2215 {0x66555555, 0x5a5a5a5a},
2216 {0x66555555, 0x6a5a5a5a}, /* case-10 */
2217 {0x66555555, 0xfafafafa},
2218 {0x66555555, 0x5a5a5aaa},
2219 {0x66555555, 0x6aaa5aaa},
2220 {0x66555555, 0xaaaa5aaa},
2221 {0x66555555, 0xaaaaaaaa}, /* case-15 */
2222 {0xffff55ff, 0xfafafafa},
2223 {0xffff55ff, 0x6afa5afa},
2224 {0xaaffffaa, 0xfafafafa},
2225 {0xaa5555aa, 0x5a5a5a5a},
2226 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
2227 {0xaa5555aa, 0xaaaaaaaa},
2228 {0xffffffff, 0x5a5a5a5a},
2229 {0xffffffff, 0x5a5a5a5a},
2230 {0xffffffff, 0x55555555},
2231 {0xffffffff, 0x6a5a5aaa}, /* case-25 */
2232 {0x55555555, 0x5a5a5a5a},
2233 {0x55555555, 0xaaaaaaaa},
2234 {0x55555555, 0x6a5a6a5a},
2235 {0x66556655, 0x66556655},
2236 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
2237 {0xffffffff, 0x5aaa5aaa},
2238 {0x56555555, 0x5a5a5aaa},
2243 {0xffffffff, 0xffffffff}, /* case-100 */
2244 {0x55555555, 0x55555555},
2245 {0x66555555, 0x66555555},
2246 {0xaaaaaaaa, 0xaaaaaaaa},
2247 {0x5a5a5a5a, 0x5a5a5a5a},
2248 {0xfafafafa, 0xfafafafa}, /* case-105 */
2249 {0x5afa5afa, 0x5afa5afa},
2250 {0x55555555, 0xfafafafa},
2251 {0x66555555, 0xfafafafa},
2252 {0x66555555, 0x5a5a5a5a},
2253 {0x66555555, 0x6a5a5a5a}, /* case-110 */
2254 {0x66555555, 0xaaaaaaaa},
2255 {0xffff55ff, 0xfafafafa},
2256 {0xffff55ff, 0x5afa5afa},
2257 {0xffff55ff, 0xaaaaaaaa},
2258 {0xffff55ff, 0xffff55ff}, /* case-115 */
2259 {0xaaffffaa, 0x5afa5afa},
2260 {0xaaffffaa, 0xaaaaaaaa},
2261 {0xffffffff, 0xfafafafa},
2262 {0xffffffff, 0x5afa5afa},
2263 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
2264 {0x55ff55ff, 0x5afa5afa},
2265 {0x55ff55ff, 0xaaaaaaaa},
2266 {0x55ff55ff, 0x55ff55ff}
2271 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
2272 { {0x61, 0x45, 0x03, 0x11, 0x11} },
2273 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2274 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2275 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2276 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
2277 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2278 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2279 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2280 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2281 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
2282 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2283 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2284 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2285 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2286 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
2287 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2288 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2289 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2290 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2291 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
2292 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
2293 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
2294 { {0x55, 0x08, 0x03, 0x10, 0x54} },
2295 { {0x65, 0x10, 0x03, 0x11, 0x10} },
2296 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
2297 { {0x51, 0x08, 0x03, 0x10, 0x50} },
2298 { {0x61, 0x08, 0x03, 0x11, 0x11} }
2303 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
2304 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
2305 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2306 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2307 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2308 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
2309 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2310 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2311 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2312 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2313 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
2314 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2315 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2316 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2317 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2318 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
2319 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2320 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2321 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2322 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2323 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
2324 { {0x51, 0x08, 0x03, 0x10, 0x50} }
2333 {0, 0, false, 7}, /* for normal */
2334 {0, 16, false, 7}, /* for WL-CPT */
2335 {4, 0, true, 1},
2342 {0, 0, false, 7}, /* for normal */
2343 {0, 16, false, 7}, /* for WL-CPT */
2344 {4, 0, true, 1},
2379 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2382 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2385 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2392 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2395 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2398 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2405 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2408 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2411 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2418 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2421 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2424 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2430 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2436 0, 0, 1, 1, 2, 2, 3, 3, 4, 4,
2442 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2448 0, 1, 1, 2, 2, 3, 3, 4, 4, 5,
2454 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2460 0, 0, 1, 1, 2, 2, 3, 3, 4, 4,
2466 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2472 0, 1, 1, 2, 2, 3, 3, 4, 4, 5,
2501 {0xcb0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2502 {0xcb4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2503 {0xcba, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2504 {0xcbd, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2505 {0xc58, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2506 {0xcbd, BIT(0), RTW_REG_DOMAIN_MAC8},
2507 {0, 0, RTW_REG_DOMAIN_NL},
2508 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2509 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2510 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2511 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2512 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2513 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2514 {0, 0, RTW_REG_DOMAIN_NL},
2515 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
2516 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
2517 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2518 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2519 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B},
2520 {0, 0, RTW_REG_DOMAIN_NL},
2521 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2522 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2523 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2524 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2528 [EDCCA_TH_L2H_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE0}, .offset = 0},
2529 [EDCCA_TH_H2L_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE1}, .offset = 0},
2550 .max_power_index = 0x3f,
2551 .csi_buf_pg_num = 0,
2554 .dig_min = 0x1c,
2559 .sys_func_en = 0xDC,
2568 .rf_base_addr = {0x2800, 0x2c00},
2569 .rf_sipi_addr = {0xc90, 0xe90},
2588 .coex_para_ver = 0x20070206,
2589 .bt_desired_ver = 0x6,
2611 .bt_afh_span_bw20 = 0x24,
2612 .bt_afh_span_bw40 = 0x36,
2619 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680},