Lines Matching +full:0 +full:xc00
13 u8 res4[4]; /* 0xd0 */
15 u8 res5[0x1e];
17 u8 serial[0x0b]; /* 0xf5 */
18 u8 vid; /* 0x100 */
22 u8 mac_addr[ETH_ALEN]; /* 0x107 */
24 u8 vendor_name[0x07];
26 u8 device_name[0x14];
27 u8 res11[0xcf];
28 u8 package_type; /* 0x1fb */
29 u8 res12[0x4];
33 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
41 u8 ltr_cap; /* 0xe3 */
46 u8 res0:2; /* 0xf4 */
69 u8 res4[0x4a]; /* 0xd0 */
70 u8 mac_addr[ETH_ALEN]; /* 0x11a */
75 u8 res0[0x0e];
80 u8 channel_plan; /* 0xb8 */
84 u8 pa_type; /* 0xbc */
85 u8 lna_type_2g[2]; /* 0xbd */
95 u8 rf_antenna_option; /* 0xc9 */
109 /* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */
111 rtw_write32_mask(rtwdev, addr + 0x200, mask, data);
118 BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00); \
121 } while (0)
124 #define WLAN_SLOT_TIME 0x09
125 #define WLAN_PIFS_TIME 0x19
126 #define WLAN_SIFS_CCK_CONT_TX 0xA
127 #define WLAN_SIFS_OFDM_CONT_TX 0xE
128 #define WLAN_SIFS_CCK_TRX 0x10
129 #define WLAN_SIFS_OFDM_TRX 0x10
130 #define WLAN_VO_TXOP_LIMIT 0x186
131 #define WLAN_VI_TXOP_LIMIT 0x3BC
132 #define WLAN_RDG_NAV 0x05
133 #define WLAN_TXOP_NAV 0x1B
134 #define WLAN_CCK_RX_TSF 0x30
135 #define WLAN_OFDM_RX_TSF 0x30
136 #define WLAN_TBTT_PROHIBIT 0x04
137 #define WLAN_TBTT_HOLD_TIME 0x064
138 #define WLAN_DRV_EARLY_INT 0x04
139 #define WLAN_BCN_DMA_TIME 0x02
141 #define WLAN_RX_FILTER0 0x0FFFFFFF
142 #define WLAN_RX_FILTER2 0xFFFF
143 #define WLAN_RCR_CFG 0xE400220E
147 #define WLAN_AMPDU_MAX_TIME 0x70
148 #define WLAN_RTS_LEN_TH 0xFF
149 #define WLAN_RTS_TX_TIME_TH 0x08
150 #define WLAN_MAX_AGG_PKT_LIMIT 0x20
151 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
152 #define FAST_EDCA_VO_TH 0x06
153 #define FAST_EDCA_VI_TH 0x06
154 #define FAST_EDCA_BE_TH 0x06
155 #define FAST_EDCA_BK_TH 0x06
156 #define WLAN_BAR_RETRY_LIMIT 0x01
157 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
159 #define WLAN_TX_FUNC_CFG1 0x30
160 #define WLAN_TX_FUNC_CFG2 0x30
161 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
162 #define WLAN_MAC_OPT_LB_FUNC1 0x80
163 #define WLAN_MAC_OPT_FUNC2 0xb0810041
175 #define WLAN_PRE_TXCNT_TIME_TH 0x1E4
179 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
181 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(12, 8))
183 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(15, 13))
185 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), BIT(23))
187 #define BIT_LNA_L_MASK GENMASK(2, 0)
191 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
193 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
195 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
197 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
199 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
201 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
203 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
205 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
207 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
209 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
211 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
213 #define REG_SYS_CTRL 0x000
215 #define REG_INIRTS_RATE_SEL 0x0480
216 #define REG_HTSTFWT 0x800
217 #define REG_RXPSEL 0x808
219 #define REG_TXPSEL 0x80c
220 #define REG_RXCCAMSK 0x814
221 #define REG_CCASEL 0x82c
222 #define REG_PDMFTH 0x830
223 #define REG_CCA2ND 0x838
224 #define REG_L1WT 0x83c
225 #define REG_L1PKWT 0x840
226 #define REG_MRC 0x850
227 #define REG_CLKTRK 0x860
228 #define REG_ADCCLK 0x8ac
229 #define REG_ADC160 0x8c4
230 #define REG_ADC40 0x8c8
231 #define REG_CHFIR 0x8f0
232 #define REG_CDDTXP 0x93c
233 #define REG_TXPSEL1 0x940
234 #define REG_ACBB0 0x948
235 #define REG_ACBBRXFIR 0x94c
236 #define REG_ACGG2TBL 0x958
237 #define REG_FAS 0x9a4
238 #define REG_RXSB 0xa00
239 #define REG_ADCINI 0xa04
240 #define REG_PWRTH 0xa08
241 #define REG_CCA_FLTR 0xa20
242 #define REG_TXSF2 0xa24
243 #define REG_TXSF6 0xa28
244 #define REG_FA_CCK 0xa5c
245 #define REG_RXDESC 0xa2c
246 #define REG_ENTXCCK 0xa80
247 #define BTG_LNA 0xfc84
248 #define WLG_LNA 0x7532
249 #define REG_ENRXCCA 0xa84
250 #define BTG_CCA 0x0e
251 #define WLG_CCA 0x12
252 #define REG_PWRTH2 0xaa8
253 #define REG_CSRATIO 0xaaa
254 #define REG_TXFILTER 0xaac
255 #define REG_CNTRST 0xb58
256 #define REG_AGCTR_A 0xc08
257 #define REG_TXSCALE_A 0xc1c
258 #define REG_TXDFIR 0xc20
259 #define REG_RXIGI_A 0xc50
260 #define REG_TXAGCIDX 0xc94
261 #define REG_TRSW 0xca0
262 #define REG_RFESEL0 0xcb0
263 #define REG_RFESEL8 0xcb4
264 #define REG_RFECTL 0xcb8
270 #define REG_RFEINV 0xcbc
271 #define REG_AGCTR_B 0xe08
272 #define REG_RXIGI_B 0xe50
273 #define REG_CRC_CCK 0xf04
274 #define REG_CRC_OFDM 0xf14
275 #define REG_CRC_HT 0xf10
276 #define REG_CRC_VHT 0xf0c
277 #define REG_CCA_OFDM 0xf08
278 #define REG_FA_OFDM 0xf48
279 #define REG_CCA_CCK 0xfcc
280 #define REG_DMEM_CTRL 0x1080
282 #define REG_ANTWT 0x1904
283 #define REG_IQKFAILMSK 0x1bf0
286 #define BT_CNT_ENABLE 0x1
288 #define BCN_PRI_EN 0x1
289 #define PTA_CTRL_PIN 0x66
290 #define DPDT_CTRL_PIN 0x77
291 #define ANTDIC_CTRL_PIN 0x88
292 #define REG_CTRL_TYPE 0x67
298 #define RF18_BAND_2G (0)