Lines Matching +full:channel +full:- +full:11
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
21 -20, -24, -28, -31, -34, -37, -40, -44};
26 ether_addr_copy(efuse->addr, map->e.mac_addr);
32 ether_addr_copy(efuse->addr, map->u.mac_addr);
38 ether_addr_copy(efuse->addr, map->s.mac_addr);
50 struct rtw_hal *hal = &rtwdev->hal;
51 struct rtw_efuse *efuse = &rtwdev->efuse;
57 efuse->rfe_option = map->rfe_option & 0x1f;
58 efuse->rf_board_option = map->rf_board_option;
59 efuse->crystal_cap = map->xtal_k;
60 efuse->pa_type_2g = map->pa_type;
61 efuse->pa_type_5g = map->pa_type;
62 efuse->lna_type_2g = map->lna_type_2g[0];
63 efuse->lna_type_5g = map->lna_type_5g[0];
64 efuse->channel_plan = map->channel_plan;
65 efuse->country_code[0] = map->country_code[0];
66 efuse->country_code[1] = map->country_code[1];
67 efuse->bt_setting = map->rf_bt_setting;
68 efuse->regd = map->rf_board_option & 0x7;
69 efuse->thermal_meter[0] = map->thermal_meter;
70 efuse->thermal_meter_k = map->thermal_meter;
71 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;
72 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;
74 hal->pkg_type = map->rfe_option & BIT(5) ? 1 : 0;
76 switch (efuse->rfe_option) {
83 hal->rfe_btg = true;
88 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
90 if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4)
91 efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g;
105 return -ENOTSUPP;
135 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
139 dm_info->default_ofdm_index = 24;
141 dm_info->default_ofdm_index = swing_idx;
143 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]);
144 dm_info->delta_power_index[RF_PATH_A] = 0;
145 dm_info->delta_power_index_last[RF_PATH_A] = 0;
146 dm_info->pwr_trk_triggered = false;
147 dm_info->pwr_trk_init_trigger = true;
148 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
160 struct rtw_hal *hal = &rtwdev->hal;
178 usleep_range(10, 11);
181 usleep_range(10, 11);
188 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
195 hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD);
196 hal->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD);
197 hal->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD);
200 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
241 /* Set beacon cotnrol - enable TSF and other related functions */
310 static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
312 struct rtw_hal *hal = &rtwdev->hal;
320 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G);
321 rf_reg18 |= (channel & RF18_CHANNEL_MASK);
323 if (channel >= 100 && channel <= 140)
325 else if (channel > 140)
343 if (channel <= 14) {
344 if (hal->rfe_btg)
384 static void rtw8821c_cck_tx_filter_srrc(struct rtw_dev *rtwdev, u8 channel, u8 bw)
386 struct rtw_hal *hal = &rtwdev->hal;
388 if (channel == 14) {
404 } else if (channel == 13 ||
405 (channel == 11 && bw == RTW_CHANNEL_WIDTH_40)) {
424 hal->ch_param[0]);
426 hal->ch_param[1] & MASKLWORD);
428 hal->ch_param[2]);
443 static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
446 struct rtw_hal *hal = &rtwdev->hal;
449 if (channel <= 14) {
459 rtw8821c_cck_tx_filter_srrc(rtwdev, channel, bw);
464 if (channel == 14) {
470 hal->ch_param[0]);
472 hal->ch_param[1] & MASKLWORD);
474 hal->ch_param[2]);
476 } else if (channel > 35) {
482 if (channel >= 36 && channel <= 64)
484 else if (channel >= 100 && channel <= 144)
486 else if (channel >= 149)
489 if (channel >= 36 && channel <= 48)
491 else if (channel >= 52 && channel <= 64)
493 else if (channel >= 100 && channel <= 116)
495 else if (channel >= 118 && channel <= 177)
554 static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel)
556 struct rtw_efuse efuse = rtwdev->efuse;
560 tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g :
568 static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel,
572 rtw8821c_get_bb_swing(rtwdev, channel));
576 static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
579 rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
580 rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx);
581 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
582 rtw8821c_set_channel_rf(rtwdev, channel, bw);
588 struct rtw_efuse *efuse = &rtwdev->efuse;
594 if (efuse->rfe_option == 0) {
604 return -120;
608 rx_pwr_all = lna_gain - 2 * vga_idx;
616 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
626 pkt_stat->rx_power[RF_PATH_A] = rx_power;
627 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
628 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
629 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
630 pkt_stat->signal_power = rx_power;
636 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
638 s8 min_rx_power = -120;
640 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
654 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
655 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
656 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
657 pkt_stat->bw = bw;
658 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
685 struct rtw_hal *hal = &rtwdev->hal;
693 pwr_index = hal->tx_pwr_tbl[path][rate];
707 struct rtw_hal *hal = &rtwdev->hal;
710 for (path = 0; path < hal->rf_path_num; path++) {
722 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
733 dm_info->cck_fa_cnt = cck_fa_cnt;
734 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
735 dm_info->total_fa_cnt = ofdm_fa_cnt;
737 dm_info->total_fa_cnt += cck_fa_cnt;
740 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
741 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
744 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
745 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
748 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
749 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
752 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
753 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
756 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt);
757 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
760 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt);
761 dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
817 /* enable PTA (3-wire function form BT side) */
828 /* beacon queue always hi-pri */
836 struct rtw_coex *coex = &rtwdev->coex;
837 struct rtw_coex_dm *coex_dm = &coex->dm;
838 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
843 if (switch_status == coex_dm->cur_switch_status)
846 if (coex_rfe->wlg_at_btg) {
849 if (coex_rfe->ant_switch_polarity)
855 coex_dm->cur_switch_status = switch_status;
857 if (coex_rfe->ant_switch_diversity &&
861 polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
873 if (coex_rfe->rfe_module_type != 0x4 &&
874 coex_rfe->rfe_module_type != 0x2)
945 struct rtw_coex *coex = &rtwdev->coex;
946 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
947 struct rtw_efuse *efuse = &rtwdev->efuse;
949 coex_rfe->rfe_module_type = efuse->rfe_option;
950 coex_rfe->ant_switch_polarity = 0;
951 coex_rfe->ant_switch_exist = true;
952 coex_rfe->wlg_at_btg = false;
954 switch (coex_rfe->rfe_module_type) {
958 case 9: /* 1-Ant, Main, WLG */
959 default: /* 2-Ant, DPDT, WLG */
962 case 10: /* 1-Ant, Main, BTG */
964 case 15: /* 2-Ant, DPDT, BTG */
965 coex_rfe->wlg_at_btg = true;
968 case 11: /* 1-Ant, Aux, WLG */
969 coex_rfe->ant_switch_polarity = 1;
972 case 12: /* 1-Ant, Aux, BTG */
973 coex_rfe->wlg_at_btg = true;
974 coex_rfe->ant_switch_polarity = 1;
977 case 13: /* 2-Ant, no switch, WLG */
979 case 14: /* 2-Ant, no antenna switch, WLG */
980 coex_rfe->ant_switch_exist = false;
987 struct rtw_coex *coex = &rtwdev->coex;
988 struct rtw_coex_dm *coex_dm = &coex->dm;
989 struct rtw_efuse *efuse = &rtwdev->efuse;
990 bool share_ant = efuse->share_ant;
995 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
998 coex_dm->cur_wl_pwr_lvl = wl_pwr;
1009 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1010 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A];
1011 u8 swing_upper_bound = dm_info->default_ofdm_index + 10;
1015 u8 swing_index = dm_info->default_ofdm_index;
1018 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15);
1023 swing_index = dm_info->default_ofdm_index;
1026 swing_index = dm_info->default_ofdm_index +
1027 delta_pwr_idx - pwr_idx_offset;
1033 swing_index = dm_info->default_ofdm_index;
1035 if (dm_info->default_ofdm_index >
1036 (pwr_idx_offset_lower - delta_pwr_idx))
1037 swing_index = dm_info->default_ofdm_index +
1038 delta_pwr_idx - pwr_idx_offset_lower;
1048 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1;
1070 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1073 u8 channel = rtwdev->hal.current_channel;
1074 u8 band_width = rtwdev->hal.current_band_width;
1076 u8 tx_rate = dm_info->tx_rate;
1077 u8 max_pwr_idx = rtwdev->chip->max_power_index;
1080 band_width, channel, regd);
1084 pwr_idx_offset = max_pwr_idx - tx_pwr_idx;
1085 pwr_idx_offset_lower = 0 - tx_pwr_idx;
1092 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1098 if (rtwdev->efuse.thermal_meter[0] == 0xff)
1105 if (dm_info->pwr_trk_init_trigger)
1106 dm_info->pwr_trk_init_trigger = false;
1113 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1);
1115 dm_info->delta_power_index[RF_PATH_A] =
1118 if (dm_info->delta_power_index[RF_PATH_A] ==
1119 dm_info->delta_power_index_last[RF_PATH_A])
1122 dm_info->delta_power_index_last[RF_PATH_A] =
1123 dm_info->delta_power_index[RF_PATH_A];
1133 struct rtw_efuse *efuse = &rtwdev->efuse;
1134 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1136 if (efuse->power_track_type != 0)
1139 if (!dm_info->pwr_trk_triggered) {
1142 dm_info->pwr_trk_triggered = true;
1147 dm_info->pwr_trk_triggered = false;
1173 if (bfee->role == RTW_BFEE_SU)
1175 else if (bfee->role == RTW_BFEE_MU)
1183 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1187 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n",
1188 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl);
1190 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)
1198 dm_info->cck_pd_default + new_lvl * 2,
1199 pd[new_lvl], dm_info->cck_fa_avg);
1201 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
1203 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
1206 dm_info->cck_pd_default + new_lvl * 2);
1688 /* rssi in percentage % (dbm = % - 100) */
1692 /* Shared-Antenna Coex Table */
1694 {0x55555555, 0x55555555}, /* case-0 */
1699 {0xfafafafa, 0xfafafafa}, /* case-5 */
1704 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1709 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1714 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1719 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1724 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1729 /* Non-Shared-Antenna Coex Table */
1731 {0xffffffff, 0xffffffff}, /* case-100 */
1736 {0xffffffff, 0xffffffff}, /* case-105 */
1741 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1746 {0xffff55ff, 0xffff55ff}, /* case-115 */
1751 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1757 /* Shared-Antenna TDMA */
1759 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1760 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1764 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1769 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1774 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1779 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1784 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1789 /* Non-Shared-Antenna TDMA */
1791 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1796 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1801 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1806 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1811 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1820 {0, 20, false, 7}, /* for WL-CPT */
1829 {0, 20, false, 7}, /* for WL-CPT */
1844 11, 11, 12, 12, 12, 12, 12},
1845 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1846 11, 12, 12, 12, 12, 12, 12, 12},
1847 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1848 11, 12, 12, 12, 12, 12, 12},
1852 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1854 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1856 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1857 11, 12, 12, 12, 12, 12, 12, 12},
1862 11, 11, 12, 12, 12, 12, 12},
1863 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1864 11, 12, 12, 12, 12, 12, 12, 12},
1865 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1866 11, 12, 12, 12, 12, 12, 12},
1870 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1872 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1874 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1875 11, 12, 12, 12, 12, 12, 12, 12},