Lines Matching +full:0 +full:x18000060
19 #define WLAN_SLOT_TIME 0x09
20 #define WLAN_RL_VAL 0x3030
21 #define WLAN_BAR_VAL 0x0201ffff
22 #define BIT_MASK_TBTT_HOLD 0x00000fff
24 #define BIT_MASK_TBTT_SETUP 0x000000ff
25 #define BIT_SHIFT_TBTT_SETUP 0
30 #define WLAN_TBTT_TIME_NORMAL TBTT_TIME(0x04, 0x80)
31 #define WLAN_TBTT_TIME_STOP_BCN TBTT_TIME(0x04, 0x64)
32 #define WLAN_PIFS_VAL 0
33 #define WLAN_AGG_BRK_TIME 0x16
34 #define WLAN_NAV_PROT_LEN 0x0040
35 #define WLAN_SPEC_SIFS 0x100a
36 #define WLAN_RX_PKT_LIMIT 0x17
37 #define WLAN_MAX_AGG_NR 0x0A
38 #define WLAN_AMPDU_MAX_TIME 0x1C
39 #define WLAN_ANT_SEL 0x82
40 #define WLAN_LTR_IDLE_LAT 0x90039003
41 #define WLAN_LTR_ACT_LAT 0x883c883c
42 #define WLAN_LTR_CTRL1 0xCB004010
43 #define WLAN_LTR_CTRL2 0x01233425
46 0x0b40002d, 0x0c000030, 0x0cc00033, 0x0d800036, 0x0e400039, 0x0f00003c,
47 0x10000040, 0x11000044, 0x12000048, 0x1300004c, 0x14400051, 0x15800056,
48 0x16c0005b, 0x18000060, 0x19800066, 0x1b00006c, 0x1c800072, 0x1e400079,
49 0x20000080, 0x22000088, 0x24000090, 0x26000098, 0x288000a2, 0x2ac000ab,
50 0x2d4000b5, 0x300000c0, 0x32c000cb, 0x35c000d7, 0x390000e4, 0x3c8000f2,
51 0x40000100, 0x43c0010f, 0x47c0011f, 0x4c000130, 0x50800142, 0x55400155,
52 0x5a400169, 0x5fc0017f, 0x65400195, 0x6b8001ae, 0x71c001c7, 0x788001e2,
53 0x7f8001fe,
57 0x0CD, 0x0D9, 0x0E6, 0x0F3, 0x102, 0x111, 0x121, 0x132, 0x144, 0x158,
58 0x16C, 0x182, 0x198, 0x1B1, 0x1CA, 0x1E5, 0x202, 0x221, 0x241, 0x263,
59 0x287, 0x2AE, 0x2D6, 0x301, 0x32F, 0x35F, 0x392, 0x3C9, 0x402, 0x43F,
60 0x47F, 0x4C3, 0x50C, 0x558, 0x5A9, 0x5FF, 0x65A, 0x6BA, 0x720, 0x78C,
61 0x7FF,
76 dm_info->delta_power_index[path] = 0;
81 dm_info->txagc_remnant_cck = 0;
82 dm_info->txagc_remnant_ofdm[RF_PATH_A] = 0;
95 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80);
104 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F;
119 rtw_write8(rtwdev, REG_ATIMWND, 0x2);
144 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
150 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);
151 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);
184 if (GET_PHY_STAT_P1_RF_MODE(phy_status) == 0)
205 rx_evm = clamp_t(s8, -pkt_stat->rx_evm[RF_PATH_A] >> 1, 0, 64);
206 rx_evm &= 0x3F; /* 64->0: second path of 1SS rate is 64 */
215 page = *phy_status & 0xf;
218 case 0:
260 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f);
261 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
262 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
263 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
264 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
265 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
266 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
272 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb);
273 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
274 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x04000000);
275 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
276 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
277 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
278 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
281 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5);
282 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
283 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
284 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
285 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
286 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00080000);
287 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
290 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
291 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
340 [0] = {
341 { .len = 4, .reg = 0xA24, .val = 0x64B80C1C },
342 { .len = 4, .reg = 0xA28, .val = 0x00008810 },
343 { .len = 4, .reg = 0xAAC, .val = 0x01235667 },
346 { .len = 4, .reg = 0xA24, .val = 0x0000B81C },
347 { .len = 4, .reg = 0xA28, .val = 0x00000000 },
348 { .len = 4, .reg = 0xAAC, .val = 0x00003667 },
358 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1];
360 for (i = 0; i < CCK_DFIR_NR; i++, cck_dfir++)
365 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0);
366 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0);
368 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_MASK_RXBB_DFIR, 0xa);
371 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1);
372 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1);
373 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 0);
375 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0));
411 .val_bb_sel_btg = 0x99000000,
413 .val_txiqk_pi = 0x8214019f,
417 .val_wlint = 0xe0d,
418 .val_wlsel = 0x60d,
419 .val_iqkpts = 0xfa000000,
423 .val_bb_sel_btg = 0x99000280,
425 .val_txiqk_pi = 0x8214018a,
429 .val_wlint = 0xe6d,
430 .val_wlsel = 0x66d,
431 .val_iqkpts = 0xf9000000,
441 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n",
443 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n",
447 "[IQK] 0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
448 rtw_read32(rtwdev, 0xe90),
449 rtw_read32(rtwdev, 0xe98));
461 return 0;
470 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n",
475 "[IQK] 0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n",
476 rtw_read32(rtwdev, 0xea0),
477 rtw_read32(rtwdev, 0xea8));
491 return 0;
494 #define IQK_LTE_WRITE_VAL_8723D 0x0000ff00
499 u32 pts = (tx ? iqk_cfg->val_iqkpts : 0xf9000000);
505 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0054);
507 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] GNT_BT @%s %sIQK1 = 0x%x\n",
510 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x948 @%s %sIQK1 = 0x%x\n",
516 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000);
533 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x0);
534 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, BIT(0), 0x0);
535 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, BIT(0), 0x0);
545 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s TXIQK = 0x%x\n",
552 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000);
553 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00004);
554 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005d);
555 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xBFFE0);
556 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);
559 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x08008c0c);
560 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);
562 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160200);
563 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
564 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
567 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911);
570 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1);
571 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0);
572 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x1E0, 0x3);
573 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXIQGEN, 0x1F, 0xf);
576 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x10, 0x1);
577 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_bspad, 0x1, 0x1);
582 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s TXIQK = 0x%x\n",
585 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s TXIQK = 0x%x\n",
606 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK1 = 0x%x\n",
614 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
615 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
618 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c);
619 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);
620 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);
621 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);
622 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82160000);
623 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160000);
626 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911);
629 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000);
630 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00006);
631 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f);
632 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xa7ffb);
633 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);
635 /* PA/PAD=0 */
636 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1);
637 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0);
641 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1@ path %s RXIQK1 = 0x%x\n",
644 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2@ path %s RXIQK1 = 0x%x\n",
659 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n",
665 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK2 = 0x%x\n",
669 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
670 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c);
671 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c);
672 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);
673 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);
674 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82170000);
675 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28171400);
678 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1);
683 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x80000, 0x1);
684 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00007);
685 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f);
686 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xb3fdb);
687 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);
689 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s RXIQK2 = 0x%x\n",
692 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s RXIQK2 = 0x%x\n",
713 if (result[IQK_S1_TX_X] == 0)
736 "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n",
739 "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c);
741 if (result[IQK_S1_RX_X] == 0)
760 if (result[IQK_S0_TX_X] == 0)
777 if (result[IQK_S0_RX_X] == 0)
788 rtw_write8(rtwdev, REG_TXPAUSE, 0xff);
799 rtw_write_rf(rtwdev, path, RF_MODE, RFREG_MASK, 0x10000);
803 #define ADDA_ON_VAL_8723D 0x03c00016
814 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
815 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
835 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf);
836 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05611);
837 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4);
838 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204200);
841 for (i = 0; i < PATH_IQK_RETRY; i++) {
854 result[t][IQK_S1_TX_X] = 0x100;
855 result[t][IQK_S1_TX_Y] = 0x0;
858 for (i = 0; i < PATH_IQK_RETRY; i++) {
871 result[t][IQK_S1_RX_X] = 0x100;
872 result[t][IQK_S1_RX_Y] = 0x0;
875 if (s1_ok == 0x0)
880 for (i = 0; i < PATH_IQK_RETRY; i++) {
893 result[t][IQK_S0_TX_X] = 0x100;
894 result[t][IQK_S0_TX_Y] = 0x0;
897 for (i = 0; i < PATH_IQK_RETRY; i++) {
911 result[t][IQK_S0_RX_X] = 0x100;
912 result[t][IQK_S0_RX_Y] = 0x0;
915 if (s0_ok == 0x0)
936 memset(result, 0, sizeof(result));
967 s32 reg_tmp = 0;
969 for (i = 0; i < IQK_NR; i++)
972 if (reg_tmp != 0) {
1000 result[i][0], result[i][1], result[i][2], result[i][3],
1005 "[IQK]0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n",
1011 "[IQK]0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n",
1034 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n",
1042 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);
1043 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,
1054 rtw_write8_mask(rtwdev, REG_LEDCFG2, BIT(6), 0);
1055 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(0), 0);
1056 rtw_write8_mask(rtwdev, REG_GPIO_INTM + 2, BIT(4), 0);
1057 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT(1), 0);
1058 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(1), 0);
1059 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT(7), 0);
1060 rtw_write8_mask(rtwdev, REG_SYS_CLKR + 1, BIT(1), 0);
1061 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT(3), 0);
1072 coex_rfe->ant_switch_polarity = 0;
1081 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x80);
1083 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x200);
1086 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x280);
1088 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x0);
1092 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);
1093 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
1094 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
1101 static const u8 wl_tx_power[] = {0xb2, 0x90};
1123 0xec120101, 0xeb130101, 0xce140101, 0xcd150101, 0xcc160101,
1124 0xcb170101, 0xca180101, 0x8d190101, 0x8c1a0101, 0x8b1b0101,
1125 0x4f1c0101, 0x4e1d0101, 0x4d1e0101, 0x4c1f0101, 0x0e200101,
1126 0x0d210101, 0x0c220101, 0x0b230101, 0xcf240001, 0xce250001,
1127 0xcd260001, 0xcc270001, 0x8f280001
1131 0xec120101, 0xeb130101, 0xea140101, 0xe9150101, 0xe8160101,
1132 0xe7170101, 0xe6180101, 0xe5190101, 0xe41a0101, 0xe31b0101,
1133 0xe21c0101, 0xe11d0101, 0xe01e0101, 0x861f0101, 0x85200101,
1134 0x84210101, 0x83220101, 0x82230101, 0x81240101, 0x80250101,
1135 0x44260101, 0x43270101, 0x42280101
1145 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++)
1148 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++)
1188 /* write new elements A, C, D, and element B is always 0 */
1201 /* write new elements A, C, D, and element B is always 0 */
1225 else if (ofdm_index < 0)
1226 ofdm_index = 0;
1240 0x00);
1256 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 0x0);
1257 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 0x0);
1258 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 0x0);
1281 rtw_write32_mask(rtwdev, 0xab4, 0x000007FF,
1304 else if (final_ofdm_swing_index < 0)
1305 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, 0,
1308 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0);
1313 else if (final_cck_swing_index < 0)
1314 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, 0,
1317 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0);
1331 if (rtwdev->efuse.thermal_meter[0] == 0xff)
1334 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1353 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1378 if (efuse->power_track_type != 0)
1383 GENMASK(17, 16), 0x03);
1427 {0xffffffff, 0xffffffff}, /* case-0 */
1428 {0x55555555, 0x55555555},
1429 {0x66555555, 0x66555555},
1430 {0xaaaaaaaa, 0xaaaaaaaa},
1431 {0x5a5a5a5a, 0x5a5a5a5a},
1432 {0xfafafafa, 0xfafafafa}, /* case-5 */
1433 {0x6a5a5555, 0xaaaaaaaa},
1434 {0x6a5a56aa, 0x6a5a56aa},
1435 {0x6a5a5a5a, 0x6a5a5a5a},
1436 {0x66555555, 0x5a5a5a5a},
1437 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1438 {0x66555555, 0x6a5a5aaa},
1439 {0x66555555, 0x5a5a5aaa},
1440 {0x66555555, 0x6aaa5aaa},
1441 {0x66555555, 0xaaaa5aaa},
1442 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1443 {0xffff55ff, 0xfafafafa},
1444 {0xffff55ff, 0x6afa5afa},
1445 {0xaaffffaa, 0xfafafafa},
1446 {0xaa5555aa, 0x5a5a5a5a},
1447 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1448 {0xaa5555aa, 0xaaaaaaaa},
1449 {0xffffffff, 0x5a5a5a5a},
1450 {0xffffffff, 0x5a5a5a5a},
1451 {0xffffffff, 0x55555555},
1452 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1453 {0x55555555, 0x5a5a5a5a},
1454 {0x55555555, 0xaaaaaaaa},
1455 {0x55555555, 0x6a5a6a5a},
1456 {0x66556655, 0x66556655},
1457 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1458 {0xffffffff, 0x5aaa5aaa},
1459 {0x56555555, 0x5a5a5aaa},
1464 {0xffffffff, 0xffffffff}, /* case-100 */
1465 {0x55555555, 0x55555555},
1466 {0x66555555, 0x66555555},
1467 {0xaaaaaaaa, 0xaaaaaaaa},
1468 {0x5a5a5a5a, 0x5a5a5a5a},
1469 {0xfafafafa, 0xfafafafa}, /* case-105 */
1470 {0x5afa5afa, 0x5afa5afa},
1471 {0x55555555, 0xfafafafa},
1472 {0x66555555, 0xfafafafa},
1473 {0x66555555, 0x5a5a5a5a},
1474 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1475 {0x66555555, 0xaaaaaaaa},
1476 {0xffff55ff, 0xfafafafa},
1477 {0xffff55ff, 0x5afa5afa},
1478 {0xffff55ff, 0xaaaaaaaa},
1479 {0xffff55ff, 0xffff55ff}, /* case-115 */
1480 {0xaaffffaa, 0x5afa5afa},
1481 {0xaaffffaa, 0xaaaaaaaa},
1482 {0xffffffff, 0xfafafafa},
1483 {0xffffffff, 0x5afa5afa},
1484 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1485 {0x55ff55ff, 0x5afa5afa},
1486 {0x55ff55ff, 0xaaaaaaaa},
1487 {0x55ff55ff, 0x55ff55ff}
1492 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1493 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1494 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1495 { {0x61, 0x30, 0x03, 0x11, 0x11} },
1496 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1497 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
1498 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1499 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
1500 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1501 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1502 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1503 { {0x61, 0x08, 0x03, 0x11, 0x14} },
1504 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1505 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1506 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1507 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1508 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1509 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1510 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1511 { {0x51, 0x20, 0x03, 0x10, 0x50} },
1512 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1513 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
1514 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
1515 { {0x55, 0x08, 0x03, 0x10, 0x54} },
1516 { {0x65, 0x10, 0x03, 0x11, 0x10} },
1517 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1518 { {0x51, 0x08, 0x03, 0x10, 0x50} },
1519 { {0x61, 0x08, 0x03, 0x11, 0x11} }
1524 { {0x00, 0x00, 0x00, 0x00, 0x01} }, /* case-100 */
1525 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
1526 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1527 { {0x61, 0x30, 0x03, 0x11, 0x11} },
1528 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1529 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1530 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1531 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
1532 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1533 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1534 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1535 { {0x61, 0x08, 0x03, 0x11, 0x14} },
1536 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1537 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1538 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1539 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1540 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1541 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1542 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1543 { {0x51, 0x20, 0x03, 0x10, 0x50} },
1544 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
1545 { {0x51, 0x08, 0x03, 0x10, 0x50} }
1551 static const struct coex_5g_afh_map afh_5g_8723d[] = { {0, 0, 0} };
1559 {0, 0, false, 7}, /* for normal */
1560 {0, 10, false, 7}, /* for WL-CPT */
1561 {1, 0, true, 4},
1568 {0, 0, false, 7}, /* for normal */
1569 {0, 10, false, 7}, /* for WL-CPT */
1570 {1, 0, true, 5},
1577 {0x0005,
1581 RTW_PWR_CMD_WRITE, BIT(3) | BIT(7), 0},
1582 {0x0086,
1586 RTW_PWR_CMD_WRITE, BIT(0), 0},
1587 {0x0086,
1592 {0x004A,
1596 RTW_PWR_CMD_WRITE, BIT(0), 0},
1597 {0x0005,
1601 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
1602 {0x0023,
1606 RTW_PWR_CMD_WRITE, BIT(4), 0},
1607 {0x0301,
1611 RTW_PWR_CMD_WRITE, 0xFF, 0},
1612 {0xFFFF,
1615 0,
1616 RTW_PWR_CMD_END, 0, 0},
1620 {0x0020,
1624 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1625 {0x0001,
1630 {0x0000,
1634 RTW_PWR_CMD_WRITE, BIT(5), 0},
1635 {0x0005,
1639 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1640 {0x0075,
1644 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1645 {0x0006,
1650 {0x0075,
1654 RTW_PWR_CMD_WRITE, BIT(0), 0},
1655 {0x0006,
1659 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1660 {0x0005,
1664 RTW_PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0},
1665 {0x0005,
1669 RTW_PWR_CMD_WRITE, BIT(7), 0},
1670 {0x0005,
1674 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1675 {0x0005,
1679 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1680 {0x0005,
1684 RTW_PWR_CMD_POLLING, BIT(0), 0},
1685 {0x0010,
1690 {0x0049,
1695 {0x0063,
1700 {0x0062,
1704 RTW_PWR_CMD_WRITE, BIT(1), 0},
1705 {0x0058,
1709 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1710 {0x005A,
1715 {0x0068,
1720 {0x0069,
1725 {0x001f,
1729 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1730 {0x0077,
1734 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1735 {0x001f,
1739 RTW_PWR_CMD_WRITE, 0xFF, 0x07},
1740 {0x0077,
1744 RTW_PWR_CMD_WRITE, 0xFF, 0x07},
1745 {0xFFFF,
1748 0,
1749 RTW_PWR_CMD_END, 0, 0},
1759 {0x0301,
1763 RTW_PWR_CMD_WRITE, 0xFF, 0xFF},
1764 {0x0522,
1768 RTW_PWR_CMD_WRITE, 0xFF, 0xFF},
1769 {0x05F8,
1773 RTW_PWR_CMD_POLLING, 0xFF, 0},
1774 {0x05F9,
1778 RTW_PWR_CMD_POLLING, 0xFF, 0},
1779 {0x05FA,
1783 RTW_PWR_CMD_POLLING, 0xFF, 0},
1784 {0x05FB,
1788 RTW_PWR_CMD_POLLING, 0xFF, 0},
1789 {0x0002,
1793 RTW_PWR_CMD_WRITE, BIT(0), 0},
1794 {0x0002,
1798 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US},
1799 {0x0002,
1803 RTW_PWR_CMD_WRITE, BIT(1), 0},
1804 {0x0100,
1808 RTW_PWR_CMD_WRITE, 0xFF, 0x03},
1809 {0x0101,
1813 RTW_PWR_CMD_WRITE, BIT(1), 0},
1814 {0x0093,
1818 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1819 {0x0553,
1824 {0xFFFF,
1827 0,
1828 RTW_PWR_CMD_END, 0, 0},
1832 {0x0003,
1836 RTW_PWR_CMD_WRITE, BIT(2), 0},
1837 {0x0080,
1841 RTW_PWR_CMD_WRITE, 0xFF, 0},
1842 {0xFFFF,
1845 0,
1846 RTW_PWR_CMD_END, 0, 0},
1850 {0x0002,
1854 RTW_PWR_CMD_WRITE, BIT(0), 0},
1855 {0x0049,
1859 RTW_PWR_CMD_WRITE, BIT(1), 0},
1860 {0x0006,
1864 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1865 {0x0005,
1870 {0x0005,
1874 RTW_PWR_CMD_POLLING, BIT(1), 0},
1875 {0x0010,
1879 RTW_PWR_CMD_WRITE, BIT(6), 0},
1880 {0x0000,
1885 {0x0020,
1889 RTW_PWR_CMD_WRITE, BIT(0), 0},
1890 {0xFFFF,
1893 0,
1894 RTW_PWR_CMD_END, 0, 0},
1898 {0x0007,
1902 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1903 {0x0005,
1908 {0x0005,
1913 {0x0005,
1918 {0x004A,
1922 RTW_PWR_CMD_WRITE, BIT(0), 1},
1923 {0x0023,
1928 {0x0086,
1932 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1933 {0x0086,
1937 RTW_PWR_CMD_POLLING, BIT(1), 0},
1938 {0xFFFF,
1941 0,
1942 RTW_PWR_CMD_END, 0, 0},
1946 {0x001D,
1950 RTW_PWR_CMD_WRITE, BIT(0), 0},
1951 {0x001D,
1955 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1956 {0x001C,
1960 RTW_PWR_CMD_WRITE, 0xFF, 0x0E},
1961 {0xFFFF,
1964 0,
1965 RTW_PWR_CMD_END, 0, 0},
1978 {12, 2, 2, 0, 1},
1979 {12, 2, 2, 0, 1},
1980 {12, 2, 2, 0, 1},
1981 {12, 2, 2, 0, 1},
1982 {12, 2, 2, 0, 1},
2004 {0x0008, 0x4a22,
2008 {0x0009, 0x1000,
2012 {0xFFFF, 0x0000,
2024 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5,
2029 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7,
2034 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5,
2039 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7,
2044 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6,
2049 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7,
2054 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6,
2059 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7,
2064 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2065 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
2069 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2070 0, -10, -12, -14, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16
2087 [0] = { .phy_pg_tbl = &rtw8723d_bb_pg_tbl,
2093 {0x948, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2094 {0x67, BIT(7), RTW_REG_DOMAIN_MAC8},
2095 {0, 0, RTW_REG_DOMAIN_NL},
2096 {0x964, BIT(1), RTW_REG_DOMAIN_MAC8},
2097 {0x864, BIT(0), RTW_REG_DOMAIN_MAC8},
2098 {0xab7, BIT(5), RTW_REG_DOMAIN_MAC8},
2099 {0xa01, BIT(7), RTW_REG_DOMAIN_MAC8},
2100 {0, 0, RTW_REG_DOMAIN_NL},
2101 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2102 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2103 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2104 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2105 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2106 {0, 0, RTW_REG_DOMAIN_NL},
2107 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2108 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2109 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2110 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2111 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2131 .max_power_index = 0x3f,
2132 .csi_buf_pg_num = 0,
2135 .dig_min = 0x20,
2142 .lps_deep_mode_supported = 0,
2143 .sys_func_en = 0xFD,
2152 .rf_sipi_addr = {0x840, 0x844},
2167 .coex_para_ver = 0x2007022f,
2168 .bt_desired_ver = 0x2f,
2190 .bt_afh_span_bw20 = 0x20,
2191 .bt_afh_span_bw40 = 0x30,