Lines Matching +full:0 +full:x3ffff
8 #define REG_SYS_FUNC_EN 0x0002
14 #define BIT_FEN_BB_RSTB BIT(0)
17 #define REG_SYS_PW_CTRL 0x0004
20 #define REG_APS_FSMCO 0x0004
24 #define REG_SYS_CLK_CTRL 0x0008
27 #define REG_SYS_CLKR 0x0008
32 #define REG_RSV_CTRL 0x001C
33 #define DISABLE_PI 0x3
34 #define ENABLE_PI 0x2
36 #define BIT_WLMCU_IOIF BIT(0)
37 #define REG_RF_CTRL 0x001F
40 #define BIT_RF_EN BIT(0)
42 #define REG_AFE_CTRL1 0x0024
44 #define REG_EFUSE_CTRL 0x0030
47 #define BIT_MASK_EF_ADDR 0x3ff
48 #define BIT_MASK_EF_DATA 0xff
50 #define BITS_PLL 0xf0
52 #define REG_AFE_XTAL_CTRL 0x24
53 #define REG_AFE_PLL_CTRL 0x28
54 #define REG_AFE_CTRL3 0x2c
55 #define BIT_MASK_XTAL 0x00FFF000
58 #define REG_LDO_EFUSE_CTRL 0x0034
61 #define BIT_LDO25_VOLTAGE_V25 0x03
66 #define REG_ACLK_MON 0x3e
68 #define REG_GPIO_MUXCFG 0x0040
76 #define REG_LED_CFG 0x004C
87 #define BIT_LED0_CM GENMASK(2, 0)
88 #define BIT_LED_MODE_SW_CTRL 0
92 #define REG_LEDCFG2 0x004E
93 #define REG_GPIO_PIN_CTRL_2 0x0060
94 #define REG_PAD_CTRL1 0x0064
101 #define BIT_SW_DPDT_SEL_DATA BIT(0)
102 #define REG_WL_BT_PWR_CTRL 0x0068
105 #define REG_SYS_SDIO_CTRL 0x0070
108 #define REG_HCI_OPT_CTRL 0x0074
112 #define REG_RF_B_CTRL 0x76
114 #define REG_AFE_CTRL_4 0x0078
118 #define REG_LDO_SWR_CTRL 0x007C
119 #define LDO_SEL 0xC3
120 #define SPS_SEL 0x83
124 #define REG_MCUFW_CTRL 0x0080
143 #define BIT_MCUFWDL_EN BIT(0)
150 #define FW_READY_MASK 0xffff
152 #define REG_MCU_TST_CFG 0x84
153 #define VAL_FW_TRIGGER 0x1
155 #define REG_PMC_DBG_CTRL1 0xa8
158 #define REG_HIMR0 0xb0
159 #define REG_HISR0 0xb4
160 #define REG_HIMR1 0xb8
161 #define REG_HISR1 0xbc
163 #define REG_PAD_CTRL2 0x00C4
171 #define REG_EFUSE_ACCESS 0x00CF
172 #define EFUSE_ACCESS_ON 0x69
173 #define EFUSE_ACCESS_OFF 0x00
175 #define REG_WLRF1 0x00EC
176 #define REG_WIFI_BT_INFO 0x00AA
178 #define REG_SYS_CFG1 0x00F0
183 #define BIT_MASK_VENDOR_ID 0xf
189 #define BIT_MASK_CHIP_VER 0xf
194 #define REG_SYS_STATUS1 0x00F4
195 #define REG_SYS_STATUS2 0x00F8
196 #define REG_SYS_CFG2 0x00FC
197 #define REG_WLRF1 0x00EC
199 #define REG_CR 0x0100
210 #define BIT_HCI_TXDMA_EN BIT(0)
214 #define REG_PBP 0x104
215 #define PBP_RX_MASK 0x0f
216 #define PBP_TX_MASK 0xf0
217 #define PBP_64 0x0
218 #define PBP_128 0x1
219 #define PBP_256 0x2
220 #define PBP_512 0x3
221 #define PBP_1024 0x4
224 #define BIT_MASK_TXDMA_VOQ_MAP 0x3
228 #define BIT_MASK_TXDMA_VIQ_MAP 0x3
231 #define REG_TXDMA_PQ_MAP 0x010C
232 #define BIT_RXDMA_ARBBW_EN BIT(0)
237 #define BIT_MASK_TXDMA_BEQ_MAP 0x3
241 #define BIT_MASK_TXDMA_BKQ_MAP 0x3
245 #define BIT_MASK_TXDMA_MGQ_MAP 0x3
249 #define BIT_MASK_TXDMA_HIQ_MAP 0x3
253 #define BIT_MASK_TXSC_40M 0xf
256 #define BIT_SHIFT_TXSC_20M 0
257 #define BIT_MASK_TXSC_20M 0xf
261 #define MAC_CLK_HW_DEF_80M 0
266 #define REG_CR 0x0100
267 #define REG_TRXFF_BNDY 0x0114
268 #define REG_RXFF_BNDY 0x011C
269 #define REG_FE1IMR 0x0120
271 #define REG_CPWM 0x012C
272 #define REG_FWIMR 0x0130
275 #define REG_FWISR 0x0134
278 #define REG_PKTBUF_DBG_CTRL 0x0140
279 #define REG_C2HEVT 0x01A0
280 #define REG_MCUTST_1 0x01C0
281 #define REG_MCUTST_II 0x01C4
282 #define REG_WOWLAN_WAKE_REASON 0x01C7
283 #define REG_HMETFR 0x01CC
284 #define BIT_INT_BOX0 BIT(0)
290 #define REG_HMEBOX0 0x01D0
291 #define REG_HMEBOX1 0x01D4
292 #define REG_HMEBOX2 0x01D8
293 #define REG_HMEBOX3 0x01DC
294 #define REG_LLT_INIT 0x01E0
296 #define REG_HMEBOX0_EX 0x01F0
297 #define REG_HMEBOX1_EX 0x01F4
298 #define REG_HMEBOX2_EX 0x01F8
299 #define REG_HMEBOX3_EX 0x01FC
301 #define REG_RQPN 0x0200
302 #define BIT_MASK_HPQ 0xff
303 #define BIT_SHIFT_HPQ 0
305 #define BIT_MASK_LPQ 0xff
308 #define BIT_MASK_PUBQ 0xff
314 #define REG_FIFOPAGE_CTRL_2 0x0204
316 #define BIT_MASK_BCN_HEAD_1_V1 0xfff
317 #define REG_AUTO_LLT_V1 0x0208
318 #define BIT_AUTO_INIT_LLT_V1 BIT(0)
320 #define REG_DWBCN0_CTRL 0x0208
322 #define REG_TXDMA_OFFSET_CHK 0x020C
324 #define REG_TXDMA_STATUS 0x0210
327 #define REG_RQPN_NPQ 0x0214
328 #define BIT_MASK_NPQ 0xff
329 #define BIT_SHIFT_NPQ 0
330 #define BIT_MASK_EPQ 0xff
336 #define REG_AUTO_LLT 0x0224
338 #define REG_DWBCN1_CTRL 0x0228
339 #define REG_RQPN_CTRL_1 0x0228
340 #define REG_RQPN_CTRL_2 0x022C
342 #define REG_FIFOPAGE_INFO_1 0x0230
343 #define REG_FIFOPAGE_INFO_2 0x0234
344 #define REG_FIFOPAGE_INFO_3 0x0238
345 #define REG_FIFOPAGE_INFO_4 0x023C
346 #define REG_FIFOPAGE_INFO_5 0x0240
347 #define REG_H2C_HEAD 0x0244
348 #define REG_H2C_TAIL 0x0248
349 #define REG_H2C_READ_ADDR 0x024C
350 #define REG_H2C_INFO 0x0254
351 #define REG_RXDMA_AGG_PG_TH 0x0280
352 #define BIT_RXDMA_AGG_PG_TH GENMASK(7, 0)
355 #define REG_RXPKT_NUM 0x0284
359 #define REG_RXDMA_STATUS 0x0288
360 #define REG_RXDMA_DPR 0x028C
361 #define REG_RXDMA_MODE 0x0290
367 #define BIT_DMA_BURST_SIZE_1024 0
369 #define REG_RXPKTNUM 0x02B0
370 #define REG_EARLY_MODE_CONTROL 0x02BC
372 #define REG_INT_MIG 0x0304
373 #define REG_HCI_MIX_CFG 0x03FC
376 #define REG_BCNQ_INFO 0x0418
378 #define REG_TXPKT_EMPTY 0x041A
379 #define REG_FWHW_TXQ_CTRL 0x0420
382 #define REG_HWSEQ_CTRL 0x0423
384 #define REG_BCNQ_BDNY_V1 0x0424
385 #define REG_BCNQ_BDNY 0x0424
386 #define REG_MGQ_BDNY 0x0425
387 #define REG_LIFETIME_EN 0x0426
389 #define REG_SPEC_SIFS 0x0428
390 #define REG_RETRY_LIMIT 0x042a
391 #define REG_DARFRC 0x0430
392 #define REG_DARFRCH 0x0434
393 #define REG_RARFRCH 0x043C
394 #define REG_RRSR 0x0440
396 #define REG_ARFR0 0x0444
397 #define REG_ARFRH0 0x0448
398 #define REG_ARFR1_V1 0x044C
399 #define REG_ARFRH1_V1 0x0450
400 #define REG_CCK_CHECK 0x0454
402 #define REG_AMPDU_MAX_TIME_V1 0x0455
403 #define REG_BCNQ1_BDNY_V1 0x0456
404 #define REG_AMPDU_MAX_TIME 0x0456
405 #define REG_AMPDU_MAX_LENGTH 0x0458
406 #define REG_WMAC_LBK_BF_HD 0x045D
407 #define REG_TX_HANG_CTRL 0x045E
410 #define REG_FAST_EDCA_CTRL 0x0460
411 #define REG_DATA_SC 0x0483
412 #define REG_ARFR2_V1 0x048C
413 #define REG_ARFRH2_V1 0x0490
414 #define REG_ARFR3_V1 0x0494
416 #define REG_ARFRH3_V1 0x0498
417 #define REG_ARFR4 0x049C
418 #define BIT_WL_RFK BIT(0)
419 #define REG_ARFRH4 0x04A0
420 #define REG_ARFR5 0x04A4
421 #define REG_ARFRH5 0x04A8
422 #define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC
424 #define REG_QUEUE_CTRL 0x04C6
427 #define REG_SINGLE_AMPDU_CTRL 0x04C7
429 #define REG_PROT_MODE_CTRL 0x04C8
430 #define REG_MAX_AGGR_NUM 0x04CA
431 #define REG_BAR_MODE_CTRL 0x04CC
432 #define REG_PRECNT_CTRL 0x04E5
433 #define BIT_BTCCA_CTRL (BIT(0) | BIT(1))
435 #define REG_TX_RPT_CTRL 0x04EC
436 #define REG_TX_RPT_TIME 0x04F0
437 #define REG_DUMMY_PAGE4_V1 0x04FC
439 #define REG_EDCA_VO_PARAM 0x0500
440 #define REG_EDCA_VI_PARAM 0x0504
441 #define REG_EDCA_BE_PARAM 0x0508
442 #define REG_EDCA_BK_PARAM 0x050C
446 #define BIT_MASK_AIFS GENMASK(7, 0)
447 #define REG_BCNTCFG 0x0510
448 #define REG_PIFS 0x0512
449 #define REG_SIFS 0x0514
453 #define REG_AGGR_BREAK_TIME 0x051A
454 #define REG_SLOT 0x051B
455 #define REG_TX_PTCL_CTRL 0x0520
458 #define REG_TXPAUSE 0x0522
459 #define BIT_AC_QUEUE GENMASK(7, 0)
461 #define REG_RD_CTRL 0x0524
466 #define REG_TBTT_PROHIBIT 0x0540
468 #define REG_RD_NAV_NXT 0x0544
469 #define REG_NAV_PROT_LEN 0x0546
470 #define REG_BCN_CTRL 0x0550
474 #define REG_BCN_CTRL_CLINT0 0x0551
475 #define REG_DRVERLYINT 0x0558
476 #define REG_BCNDMATIM 0x0559
477 #define REG_ATIMWND 0x055A
478 #define REG_USTIME_TSF 0x055C
479 #define REG_BCN_MAX_ERR 0x055D
480 #define REG_RXTSF_OFFSET_CCK 0x055E
481 #define REG_MISC_CTRL 0x0577
483 #define BIT_DIS_SECOND_CCA (BIT(0) | BIT(1))
484 #define REG_HIQ_NO_LMT_EN 0x5A7
485 #define REG_DTIM_COUNTER_ROOT 0x5A8
486 #define BIT_HIQ_NO_LMT_EN_ROOT BIT(0)
487 #define REG_TIMER0_SRC_SEL 0x05B4
490 #define REG_TCR 0x0604
494 #define REG_RCR 0x0608
526 #define BIT_AAP BIT(0)
527 #define REG_RX_PKT_LIMIT 0x060C
528 #define REG_RX_DRVINFO_SZ 0x060F
530 #define REG_MAR 0x0620
531 #define REG_USTIME_EDCA 0x0638
532 #define REG_ACKTO_CCK 0x0639
533 #define REG_MAC_SPEC_SIFS 0x063A
534 #define REG_RESP_SIFS_CCK 0x063C
535 #define REG_RESP_SIFS_OFDM 0x063E
536 #define REG_ACKTO 0x0640
537 #define REG_EIFS 0x0642
538 #define REG_NAV_CTRL 0x0650
539 #define REG_WMAC_TRXPTCL_CTL 0x0668
543 #define REG_WMAC_TRXPTCL_CTL_H 0x066C
544 #define REG_WKFMCAM_CMD 0x0698
549 #define BIT_MASK_WKFCAM_ADDR_V2 0xff
552 #define REG_WKFMCAM_RWD 0x069C
558 #define REG_RXFLTMAP0 0x06A0
559 #define REG_RXFLTMAP1 0x06A2
560 #define REG_RXFLTMAP2 0x06A4
561 #define REG_RXFLTMAP4 0x068A
562 #define REG_BT_COEX_TABLE0 0x06C0
563 #define REG_BT_COEX_TABLE1 0x06C4
564 #define REG_BT_COEX_BRK_TABLE 0x06C8
565 #define REG_BT_COEX_TABLE_H 0x06CC
566 #define REG_BT_COEX_TABLE_H1 0x06CD
567 #define REG_BT_COEX_TABLE_H2 0x06CE
568 #define REG_BT_COEX_TABLE_H3 0x06CF
569 #define REG_BBPSF_CTRL 0x06DC
571 #define REG_BT_COEX_V2 0x0762
574 #define REG_GNT_BT 0x0765
576 #define REG_BT_COEX_ENH_INTR_CTRL 0x76E
579 #define REG_BT_ACT_STATISTICS 0x0770
580 #define REG_BT_ACT_STATISTICS_1 0x0774
581 #define REG_BT_STAT_CTRL 0x0778
582 #define REG_BT_TDMA_TIME 0x0790
583 #define BIT_MASK_SAMPLE_RATE GENMASK(5, 0)
584 #define REG_LTR_IDLE_LATENCY 0x0798
585 #define REG_LTR_ACTIVE_LATENCY 0x079C
586 #define REG_LTR_CTRL_BASIC 0x07A4
587 #define REG_WMAC_OPTION_FUNCTION 0x07D0
588 #define REG_WMAC_OPTION_FUNCTION_1 0x07D4
590 #define REG_FPGA0_RFMOD 0x0800
593 #define REG_CCK_RPT_FORMAT 0x0804
595 #define REG_RXPSEL 0x0808
597 #define REG_TXPSEL 0x080C
598 #define REG_RX_GAIN_EN 0x081c
599 #define REG_CCASEL 0x082C
600 #define REG_PDMFTH 0x0830
601 #define REG_BWINDICATION 0x0834
602 #define REG_CCA2ND 0x0838
603 #define REG_L1PKTH 0x0848
604 #define REG_CLKTRK 0x0860
605 #define REG_ADCCLK 0x08AC
606 #define REG_HSSI_READ 0x08B0
607 #define REG_FPGA0_XCD_RF_PARA 0x08B4
608 #define REG_RX_MCS_LIMIT 0x08BC
609 #define REG_ADC160 0x08C4
610 #define REG_ANTSEL_SW 0x0900
611 #define REG_DAC_RSTB 0x090c
612 #define REG_SINGLE_TONE_CONT_TX 0x0914
614 #define REG_RFE_CTRL_E 0x0974
615 #define REG_2ND_CCA_CTRL 0x0976
616 #define REG_IQK_COM00 0x0978
617 #define REG_IQK_COM32 0x097c
618 #define REG_IQK_COM64 0x0980
619 #define REG_IQK_COM96 0x0984
621 #define REG_FAS 0x09a4
622 #define REG_RXSB 0x0a00
623 #define REG_CCK_RX 0x0a04
624 #define REG_CCK_PD_TH 0x0a0a
626 #define REG_CCK0_FAREPORT 0xa2c
629 #define REG_FA_CCK 0x0a5c
631 #define REG_DIS_DPD 0x0a70
632 #define DIS_DPD_MASK GENMASK(9, 0)
633 #define DIS_DPD_RATE6M BIT(0)
643 #define DIS_DPD_RATEALL GENMASK(9, 0)
645 #define REG_CNTRST 0x0b58
647 #define REG_3WIRE_SWA 0x0c00
648 #define REG_RX_IQC_AB_A 0x0c10
649 #define REG_TXSCALE_A 0x0c1c
651 #define REG_TX_AGC_A_CCK_11_CCK_1 0xc20
652 #define REG_TX_AGC_A_OFDM18_OFDM6 0xc24
653 #define REG_TX_AGC_A_OFDM54_OFDM24 0xc28
654 #define REG_TX_AGC_A_MCS3_MCS0 0xc2c
655 #define REG_TX_AGC_A_MCS7_MCS4 0xc30
656 #define REG_TX_AGC_A_MCS11_MCS8 0xc34
657 #define REG_TX_AGC_A_MCS15_MCS12 0xc38
658 #define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0 0xc3c
659 #define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4 0xc40
660 #define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8 0xc44
661 #define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2 0xc48
662 #define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6 0xc4c
663 #define REG_RXIGI_A 0x0c50
664 #define REG_TX_PWR_TRAINING_A 0x0c54
665 #define REG_CK_MONHA 0x0c5c
666 #define REG_AFE_PWR1_A 0x0c60
667 #define REG_AFE_PWR2_A 0x0c64
668 #define REG_RX_WAIT_CCA_TX_CCK_RFON_A 0x0c68
669 #define REG_OFDM0_XA_TX_IQ_IMBALANCE 0x0c80
670 #define REG_OFDM0_A_TX_AFE 0x0c84
671 #define REG_OFDM0_XB_TX_IQ_IMBALANCE 0x0c88
672 #define REG_TSSI_TRK_SW 0x0c8c
673 #define REG_LSSI_WRITE_A 0x0c90
674 #define REG_PREDISTA 0x0c90
675 #define REG_TXAGCIDX 0x0c94
677 #define REG_RFE_PINMUX_A 0x0cb0
678 #define REG_RFE_INV_A 0x0cb4
679 #define REG_RFE_CTRL8 0x0cb4
680 #define BIT_MASK_RFE_SEL89 GENMASK(7, 0)
681 #define PTA_CTRL_PIN 0x66
682 #define DPDT_CTRL_PIN 0x77
683 #define RFE_INV_MASK 0x3ff00000
684 #define REG_RFECTL_A 0x0cb8
685 #define REG_RFE_INV8 0x0cbd
686 #define BIT_MASK_RFE_INV89 GENMASK(1, 0)
687 #define REG_RFE_INV16 0x0cbe
690 #define REG_IQK_DPD_CFG 0x0cc4
691 #define REG_CFG_PMPD 0x0cc8
692 #define REG_IQC_Y 0x0ccc
693 #define REG_IQC_X 0x0cd4
694 #define REG_INTPO_SETA 0x0ce8
696 #define REG_IQKA_END 0x0d00
697 #define REG_PI_READ_A 0x0d04
698 #define REG_SI_READ_A 0x0d08
699 #define REG_IQKB_END 0x0d40
700 #define REG_PI_READ_B 0x0d44
701 #define REG_SI_READ_B 0x0d48
703 #define REG_3WIRE_SWB 0x0e00
704 #define REG_RX_IQC_AB_B 0x0e10
705 #define REG_TXSCALE_B 0x0e1c
706 #define REG_TX_AGC_B_CCK_11_CCK_1 0xe20
707 #define REG_TX_AGC_B_OFDM18_OFDM6 0xe24
708 #define REG_TX_AGC_B_OFDM54_OFDM24 0xe28
709 #define REG_TX_AGC_B_MCS3_MCS0 0xe2c
710 #define REG_TX_AGC_B_MCS7_MCS4 0xe30
711 #define REG_TX_AGC_B_MCS11_MCS8 0xe34
712 #define REG_TX_AGC_B_MCS15_MCS12 0xe38
713 #define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0 0xe3c
714 #define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4 0xe40
715 #define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8 0xe44
716 #define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2 0xe48
717 #define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6 0xe4c
718 #define REG_RXIGI_B 0x0e50
719 #define REG_TX_PWR_TRAINING_B 0x0e54
720 #define REG_CK_MONHB 0x0e5c
721 #define REG_AFE_PWR1_B 0x0e60
722 #define REG_AFE_PWR2_B 0x0e64
723 #define REG_RX_WAIT_CCA_TX_CCK_RFON_B 0x0e68
724 #define REG_TXTONEB 0x0e80
725 #define REG_RXTONEB 0x0e84
726 #define REG_TXPITMB 0x0e88
727 #define REG_RXPITMB 0x0e8c
728 #define REG_LSSI_WRITE_B 0x0e90
729 #define REG_PREDISTB 0x0e90
730 #define REG_INIDLYB 0x0e94
731 #define REG_RFE_PINMUX_B 0x0eb0
732 #define REG_RFE_INV_B 0x0eb4
733 #define REG_RFECTL_B 0x0eb8
734 #define REG_BPBDB 0x0ec4
735 #define REG_PHYTXONB 0x0ec8
736 #define REG_IQKYB 0x0ecc
737 #define REG_IQKXB 0x0ed4
738 #define REG_INTPO_SETB 0x0ee8
740 #define REG_CRC_CCK 0x0f04
741 #define REG_CCA_OFDM 0x0f08
742 #define REG_CRC_VHT 0x0f0c
743 #define REG_CRC_HT 0x0f10
744 #define REG_CRC_OFDM 0x0f14
745 #define REG_FA_OFDM 0x0f48
746 #define REG_CCA_CCK 0x0fcc
748 #define REG_ANAPARSW_MAC_0 0x1010
751 #define REG_ANAPAR_XTAL_0 0x1040
753 #define REG_CPU_DMEM_CON 0x1080
758 #define REG_SW_MDIO 0x10C0
760 #define REG_H2C_PKT_READADDR 0x10D0
761 #define REG_H2C_PKT_WRITEADDR 0x10D4
762 #define REG_FW_DBG6 0x10F8
763 #define REG_FW_DBG7 0x10FC
764 #define FW_KEY_MASK 0xffffff00
766 #define REG_CR_EXT 0x1100
768 #define REG_FT1IMR 0x1138
770 #define REG_FT1ISR 0x113c
772 #define REG_DDMA_CH0SA 0x1200
773 #define REG_DDMA_CH0DA 0x1204
774 #define REG_DDMA_CH0CTRL 0x1208
781 #define BIT_MASK_DDMACH0_DLEN 0x3ffff
783 #define REG_H2CQ_CSR 0x1330
785 #define REG_FAST_EDCA_VOVI_SETTING 0x1448
786 #define REG_FAST_EDCA_BEBK_SETTING 0x144C
788 #define REG_RXPSF_CTRL 0x1610
792 #define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3
799 #define BIT_MASK_RXGCK_HT_FIFOTHR 0x3
806 #define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3
813 #define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3
822 #define BIT_MASK_RXPSF_PKTLENTHR 0x7
842 #define BIT_SHIFT_RXPSF_ERRTHR 0
843 #define BIT_MASK_RXPSF_ERRTHR 0x7
853 #define REG_RXPSF_TYPE_CTRL 0x1614
854 #define REG_GENERAL_OPTION 0x1664
857 #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700
858 #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704
859 #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708
865 #define REG_IGN_GNT_BT1 0x1860
867 #define REG_RFESEL_CTRL 0x1990
869 #define REG_NOMASK_TXBT 0x1ca7
870 #define REG_ANAPAR 0x1c30
872 #define REG_RSTB_SEL 0x1c38
877 #define REG_HRCV_MSG 0x1cf
879 #define REG_EDCCA_REPORT 0x2d38
882 #define REG_IGN_GNTBT4 0x4160
884 #define REG_USB_MOD 0xf008
885 #define REG_USB3_RXITV 0xf050
886 #define REG_USB2_PHY_ADR 0xfe40
887 #define REG_USB2_PHY_DAT 0xfe41
888 #define REG_USB2_PHY_CMD 0xfe42
889 #define BIT_USB2_PHY_CMD_TRG 0x81
890 #define REG_USB_HRPWM 0xfe58
891 #define REG_USB3_PHY_ADR 0xff0c
892 #define REG_USB3_PHY_DAT_L 0xff0d
893 #define REG_USB3_PHY_DAT_H 0xff0e
896 #define BIT_USB3_PHY_ADR_MASK GENMASK(5, 0)
898 #define RF_MODE 0x00
899 #define RF_MODOPT 0x01
900 #define RF_WLINT 0x01
901 #define RF_WLSEL 0x02
902 #define RF_DTXLOK 0x08
903 #define RF_CFGCH 0x18
908 #define RF_RCK 0x1d
909 #define RF_MODE_TABLE_ADDR 0x30
910 #define RF_MODE_TABLE_DATA0 0x31
911 #define RF_MODE_TABLE_DATA1 0x32
912 #define RF_LUTWA 0x33
913 #define RF_LUTWD1 0x3e
914 #define RF_LUTWD0 0x3f
916 #define BIT_DATA_L GENMASK(11, 0)
917 #define RF_T_METER 0x42
918 #define RF_BSPAD 0x54
919 #define RF_GAINTX 0x56
920 #define RF_TXMOD 0x58
921 #define RF_TXATANK 0x64
922 #define RF_TXA_PREPAD 0x65
923 #define RF_TRXIQ 0x66
924 #define RF_RXIQGEN 0x8d
925 #define RF_RXBB2 0x8f
926 #define RF_SYN_PFD 0xb0
927 #define RF_LCK 0xb4
928 #define RF_XTALX2 0xb8
929 #define RF_SYN_CTRL 0xbb
930 #define RF_MALSEL 0xbe
931 #define RF_SYN_AAC 0xc9
932 #define RF_AAC_CTRL 0xca
933 #define RF_FAST_LCK 0xcc
934 #define RF_RCKD 0xde
935 #define RF_TXADBG 0xde
936 #define RF_LUTDBG 0xdf
938 #define RF_LUTWE2 0xee
939 #define RF_LUTWE 0xef
941 #define LTE_COEX_CTRL 0x38
942 #define LTE_WL_TRX_CTRL 0xa0
943 #define LTE_BT_TRX_CTRL 0xa4