Lines Matching +full:0 +full:x024c
8 #define REG_SYS_FUNC_EN 0x0002
15 #define BIT_FEN_BB_RSTB BIT(0)
18 #define REG_SYS_PW_CTRL 0x0004
21 #define REG_APS_FSMCO 0x0004
25 #define REG_SYS_CLK_CTRL 0x0008
28 #define REG_SYS_CLKR 0x0008
33 #define REG_RSV_CTRL 0x001C
34 #define DISABLE_PI 0x3
35 #define ENABLE_PI 0x2
37 #define BIT_WLMCU_IOIF BIT(0)
38 #define REG_RF_CTRL 0x001F
41 #define BIT_RF_EN BIT(0)
43 #define REG_RF_CTRL1 0x0020
44 #define REG_RF_CTRL2 0x0021
46 #define REG_AFE_CTRL1 0x0024
48 #define REG_EFUSE_CTRL 0x0030
51 #define BIT_MASK_EF_ADDR 0x3ff
52 #define BIT_MASK_EF_DATA 0xff
54 #define BITS_PLL 0xf0
56 #define REG_AFE_XTAL_CTRL 0x24
57 #define REG_AFE_PLL_CTRL 0x28
58 #define REG_AFE_CTRL3 0x2c
59 #define BIT_MASK_XTAL 0x00FFF000
62 #define REG_LDO_EFUSE_CTRL 0x0034
65 #define BIT_LDO25_VOLTAGE_V25 0x03
70 #define REG_ACLK_MON 0x3e
72 #define REG_GPIO_MUXCFG 0x0040
80 #define REG_GPIO_PIN_CTRL 0x0044
82 #define REG_LED_CFG 0x004C
93 #define BIT_LED0_CM GENMASK(2, 0)
94 #define BIT_LED_MODE_SW_CTRL 0
98 #define REG_LEDCFG2 0x004E
99 #define REG_GPIO_PIN_CTRL_2 0x0060
100 #define REG_PAD_CTRL1 0x0064
107 #define BIT_SW_DPDT_SEL_DATA BIT(0)
108 #define REG_WL_BT_PWR_CTRL 0x0068
111 #define REG_SYS_SDIO_CTRL 0x0070
114 #define REG_HCI_OPT_CTRL 0x0074
118 #define REG_RF_B_CTRL 0x76
119 #define REG_RF_CTRL3 0x0076
121 #define REG_AFE_CTRL_4 0x0078
125 #define REG_LDO_SWR_CTRL 0x007C
126 #define LDO_SEL 0xC3
127 #define SPS_SEL 0x83
131 #define REG_MCUFW_CTRL 0x0080
151 #define BIT_MCUFWDL_EN BIT(0)
158 #define FW_READY_MASK (0xffff & ~BIT_CPU_CLK_SEL)
160 #define REG_MCU_TST_CFG 0x84
161 #define VAL_FW_TRIGGER 0x1
163 #define REG_PMC_DBG_CTRL1 0xa8
166 #define REG_HIMR0 0xb0
167 #define REG_HISR0 0xb4
168 #define REG_HIMR1 0xb8
169 #define REG_HISR1 0xbc
171 #define REG_PAD_CTRL2 0x00C4
179 #define REG_EFUSE_ACCESS 0x00CF
180 #define EFUSE_ACCESS_ON 0x69
181 #define EFUSE_ACCESS_OFF 0x00
183 #define REG_WLRF1 0x00EC
184 #define REG_WIFI_BT_INFO 0x00AA
186 #define REG_SYS_CFG1 0x00F0
191 #define BIT_MASK_VENDOR_ID 0xf
197 #define BIT_MASK_CHIP_VER 0xf
202 #define REG_SYS_STATUS1 0x00F4
203 #define REG_SYS_STATUS2 0x00F8
204 #define REG_SYS_CFG2 0x00FC
205 #define REG_WLRF1 0x00EC
207 #define REG_CR 0x0100
218 #define BIT_HCI_TXDMA_EN BIT(0)
222 #define REG_PBP 0x104
223 #define PBP_RX_MASK 0x0f
224 #define PBP_TX_MASK 0xf0
225 #define PBP_64 0x0
226 #define PBP_128 0x1
227 #define PBP_256 0x2
228 #define PBP_512 0x3
229 #define PBP_1024 0x4
232 #define BIT_MASK_TXDMA_VOQ_MAP 0x3
236 #define BIT_MASK_TXDMA_VIQ_MAP 0x3
239 #define REG_TXDMA_PQ_MAP 0x010C
240 #define BIT_RXDMA_ARBBW_EN BIT(0)
245 #define BIT_MASK_TXDMA_BEQ_MAP 0x3
249 #define BIT_MASK_TXDMA_BKQ_MAP 0x3
253 #define BIT_MASK_TXDMA_MGQ_MAP 0x3
257 #define BIT_MASK_TXDMA_HIQ_MAP 0x3
261 #define BIT_MASK_TXSC_40M 0xf
264 #define BIT_SHIFT_TXSC_20M 0
265 #define BIT_MASK_TXSC_20M 0xf
269 #define MAC_CLK_HW_DEF_80M 0
274 #define REG_CR 0x0100
275 #define REG_TRXFF_BNDY 0x0114
276 #define REG_RXFF_BNDY 0x011C
277 #define REG_FE1IMR 0x0120
279 #define REG_CPWM 0x012C
280 #define REG_FWIMR 0x0130
283 #define REG_FWISR 0x0134
286 #define REG_PKTBUF_DBG_CTRL 0x0140
287 #define REG_C2HEVT 0x01A0
288 #define REG_MCUTST_1 0x01C0
289 #define REG_MCUTST_II 0x01C4
290 #define REG_WOWLAN_WAKE_REASON 0x01C7
291 #define REG_HMETFR 0x01CC
292 #define BIT_INT_BOX0 BIT(0)
298 #define REG_HMEBOX0 0x01D0
299 #define REG_HMEBOX1 0x01D4
300 #define REG_HMEBOX2 0x01D8
301 #define REG_HMEBOX3 0x01DC
302 #define REG_LLT_INIT 0x01E0
304 #define REG_HMEBOX0_EX 0x01F0
305 #define REG_HMEBOX1_EX 0x01F4
306 #define REG_HMEBOX2_EX 0x01F8
307 #define REG_HMEBOX3_EX 0x01FC
309 #define REG_RQPN 0x0200
310 #define BIT_MASK_HPQ 0xff
311 #define BIT_SHIFT_HPQ 0
313 #define BIT_MASK_LPQ 0xff
316 #define BIT_MASK_PUBQ 0xff
322 #define REG_FIFOPAGE_CTRL_2 0x0204
324 #define BIT_MASK_BCN_HEAD_1_V1 0xfff
325 #define REG_AUTO_LLT_V1 0x0208
326 #define BIT_AUTO_INIT_LLT_V1 BIT(0)
328 #define REG_DWBCN0_CTRL 0x0208
330 #define REG_TXDMA_OFFSET_CHK 0x020C
332 #define REG_TXDMA_STATUS 0x0210
335 #define REG_RQPN_NPQ 0x0214
336 #define BIT_MASK_NPQ 0xff
337 #define BIT_SHIFT_NPQ 0
338 #define BIT_MASK_EPQ 0xff
344 #define REG_AUTO_LLT 0x0224
346 #define REG_DWBCN1_CTRL 0x0228
347 #define REG_RQPN_CTRL_1 0x0228
348 #define REG_RQPN_CTRL_2 0x022C
350 #define REG_FIFOPAGE_INFO_1 0x0230
351 #define REG_FIFOPAGE_INFO_2 0x0234
352 #define REG_FIFOPAGE_INFO_3 0x0238
353 #define REG_FIFOPAGE_INFO_4 0x023C
354 #define REG_FIFOPAGE_INFO_5 0x0240
355 #define REG_H2C_HEAD 0x0244
356 #define REG_H2C_TAIL 0x0248
357 #define REG_H2C_READ_ADDR 0x024C
358 #define REG_H2C_INFO 0x0254
359 #define REG_RXDMA_AGG_PG_TH 0x0280
360 #define BIT_RXDMA_AGG_PG_TH GENMASK(7, 0)
363 #define REG_RXPKT_NUM 0x0284
367 #define REG_RXDMA_STATUS 0x0288
368 #define REG_RXDMA_DPR 0x028C
369 #define REG_RXDMA_MODE 0x0290
375 #define BIT_DMA_BURST_SIZE_1024 0
377 #define REG_RXPKTNUM 0x02B0
378 #define REG_EARLY_MODE_CONTROL 0x02BC
380 #define REG_INT_MIG 0x0304
381 #define REG_HCI_MIX_CFG 0x03FC
384 #define REG_BCNQ_INFO 0x0418
386 #define REG_TXPKT_EMPTY 0x041A
387 #define REG_FWHW_TXQ_CTRL 0x0420
390 #define REG_HWSEQ_CTRL 0x0423
392 #define REG_BCNQ_BDNY_V1 0x0424
393 #define REG_BCNQ_BDNY 0x0424
394 #define REG_MGQ_BDNY 0x0425
395 #define REG_LIFETIME_EN 0x0426
397 #define REG_SPEC_SIFS 0x0428
398 #define REG_RETRY_LIMIT 0x042a
399 #define REG_DARFRC 0x0430
400 #define REG_DARFRCH 0x0434
401 #define REG_RARFRCH 0x043C
402 #define REG_RRSR 0x0440
404 #define REG_ARFR0 0x0444
405 #define REG_ARFRH0 0x0448
406 #define REG_ARFR1_V1 0x044C
407 #define REG_ARFRH1_V1 0x0450
408 #define REG_CCK_CHECK 0x0454
410 #define REG_AMPDU_MAX_TIME_V1 0x0455
411 #define REG_BCNQ1_BDNY_V1 0x0456
412 #define REG_AMPDU_MAX_TIME 0x0456
413 #define REG_AMPDU_MAX_LENGTH 0x0458
414 #define REG_WMAC_LBK_BF_HD 0x045D
415 #define REG_TX_HANG_CTRL 0x045E
418 #define REG_FAST_EDCA_CTRL 0x0460
419 #define REG_DATA_SC 0x0483
420 #define REG_ARFR2_V1 0x048C
421 #define REG_ARFRH2_V1 0x0490
422 #define REG_ARFR3_V1 0x0494
424 #define REG_ARFRH3_V1 0x0498
425 #define REG_ARFR4 0x049C
426 #define BIT_WL_RFK BIT(0)
427 #define REG_ARFRH4 0x04A0
428 #define REG_ARFR5 0x04A4
429 #define REG_ARFRH5 0x04A8
430 #define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC
432 #define REG_QUEUE_CTRL 0x04C6
435 #define REG_SINGLE_AMPDU_CTRL 0x04C7
437 #define REG_PROT_MODE_CTRL 0x04C8
438 #define REG_MAX_AGGR_NUM 0x04CA
439 #define REG_BAR_MODE_CTRL 0x04CC
440 #define REG_PRECNT_CTRL 0x04E5
441 #define BIT_BTCCA_CTRL (BIT(0) | BIT(1))
443 #define REG_TX_RPT_CTRL 0x04EC
444 #define REG_TX_RPT_TIME 0x04F0
445 #define REG_DUMMY_PAGE4_V1 0x04FC
447 #define REG_EDCA_VO_PARAM 0x0500
448 #define REG_EDCA_VI_PARAM 0x0504
449 #define REG_EDCA_BE_PARAM 0x0508
450 #define REG_EDCA_BK_PARAM 0x050C
454 #define BIT_MASK_AIFS GENMASK(7, 0)
455 #define REG_BCNTCFG 0x0510
456 #define REG_PIFS 0x0512
457 #define REG_SIFS 0x0514
461 #define REG_AGGR_BREAK_TIME 0x051A
462 #define REG_SLOT 0x051B
463 #define REG_TX_PTCL_CTRL 0x0520
466 #define REG_TXPAUSE 0x0522
467 #define BIT_AC_QUEUE GENMASK(7, 0)
469 #define REG_RD_CTRL 0x0524
474 #define REG_TBTT_PROHIBIT 0x0540
476 #define REG_RD_NAV_NXT 0x0544
477 #define REG_NAV_PROT_LEN 0x0546
478 #define REG_BCN_CTRL 0x0550
482 #define REG_BCN_CTRL_CLINT0 0x0551
483 #define REG_DRVERLYINT 0x0558
484 #define REG_BCNDMATIM 0x0559
485 #define REG_ATIMWND 0x055A
486 #define REG_USTIME_TSF 0x055C
487 #define REG_BCN_MAX_ERR 0x055D
488 #define REG_RXTSF_OFFSET_CCK 0x055E
489 #define REG_MISC_CTRL 0x0577
491 #define BIT_DIS_SECOND_CCA (BIT(0) | BIT(1))
492 #define REG_HIQ_NO_LMT_EN 0x5A7
493 #define REG_DTIM_COUNTER_ROOT 0x5A8
494 #define BIT_HIQ_NO_LMT_EN_ROOT BIT(0)
495 #define REG_TIMER0_SRC_SEL 0x05B4
498 #define REG_TCR 0x0604
502 #define REG_RCR 0x0608
534 #define BIT_AAP BIT(0)
535 #define REG_RX_PKT_LIMIT 0x060C
536 #define REG_RX_DRVINFO_SZ 0x060F
538 #define REG_MAR 0x0620
539 #define REG_USTIME_EDCA 0x0638
540 #define REG_ACKTO_CCK 0x0639
541 #define REG_MAC_SPEC_SIFS 0x063A
542 #define REG_RESP_SIFS_CCK 0x063C
543 #define REG_RESP_SIFS_OFDM 0x063E
544 #define REG_ACKTO 0x0640
545 #define REG_EIFS 0x0642
546 #define REG_NAV_CTRL 0x0650
547 #define REG_WMAC_TRXPTCL_CTL 0x0668
551 #define REG_WMAC_TRXPTCL_CTL_H 0x066C
552 #define REG_WKFMCAM_CMD 0x0698
557 #define BIT_MASK_WKFCAM_ADDR_V2 0xff
560 #define REG_WKFMCAM_RWD 0x069C
566 #define REG_RXFLTMAP0 0x06A0
567 #define REG_RXFLTMAP1 0x06A2
568 #define REG_RXFLTMAP2 0x06A4
569 #define REG_RXFLTMAP4 0x068A
570 #define REG_BT_COEX_TABLE0 0x06C0
571 #define REG_BT_COEX_TABLE1 0x06C4
572 #define REG_BT_COEX_BRK_TABLE 0x06C8
573 #define REG_BT_COEX_TABLE_H 0x06CC
574 #define REG_BT_COEX_TABLE_H1 0x06CD
575 #define REG_BT_COEX_TABLE_H2 0x06CE
576 #define REG_BT_COEX_TABLE_H3 0x06CF
577 #define REG_BBPSF_CTRL 0x06DC
579 #define REG_BT_COEX_V2 0x0762
582 #define REG_GNT_BT 0x0765
584 #define REG_BT_COEX_ENH_INTR_CTRL 0x76E
587 #define REG_BT_ACT_STATISTICS 0x0770
588 #define REG_BT_ACT_STATISTICS_1 0x0774
589 #define REG_BT_STAT_CTRL 0x0778
590 #define REG_BT_TDMA_TIME 0x0790
591 #define BIT_MASK_SAMPLE_RATE GENMASK(5, 0)
592 #define REG_LTR_IDLE_LATENCY 0x0798
593 #define REG_LTR_ACTIVE_LATENCY 0x079C
594 #define REG_LTR_CTRL_BASIC 0x07A4
595 #define REG_WMAC_OPTION_FUNCTION 0x07D0
596 #define REG_WMAC_OPTION_FUNCTION_1 0x07D4
598 #define REG_FPGA0_RFMOD 0x0800
601 #define REG_CCK_RPT_FORMAT 0x0804
603 #define REG_RXPSEL 0x0808
605 #define REG_TXPSEL 0x080C
606 #define REG_RX_GAIN_EN 0x081c
607 #define REG_CCASEL 0x082C
608 #define REG_PDMFTH 0x0830
609 #define REG_BWINDICATION 0x0834
610 #define REG_CCA2ND 0x0838
611 #define REG_L1PKTH 0x0848
612 #define REG_CLKTRK 0x0860
613 #define REG_CSI_MASK_SETTING1 0x0874
614 #define REG_NBI_SETTING 0x087c
616 #define REG_CSI_FIX_MASK0 0x0880
617 #define REG_CSI_FIX_MASK1 0x0884
618 #define REG_CSI_FIX_MASK6 0x0898
619 #define REG_CSI_FIX_MASK7 0x089c
620 #define REG_ADCCLK 0x08AC
621 #define REG_HSSI_READ 0x08B0
622 #define REG_FPGA0_XCD_RF_PARA 0x08B4
623 #define REG_RX_MCS_LIMIT 0x08BC
624 #define REG_ADC160 0x08C4
625 #define REG_DBGSEL 0x08fc
626 #define REG_ANTSEL_SW 0x0900
627 #define REG_DAC_RSTB 0x090c
628 #define REG_PSD 0x0910
630 #define REG_SINGLE_TONE_CONT_TX 0x0914
631 #define REG_AGC_TABLE 0x0958
632 #define REG_RFE_CTRL_E 0x0974
633 #define REG_2ND_CCA_CTRL 0x0976
634 #define REG_IQK_COM00 0x0978
635 #define REG_IQK_COM32 0x097c
636 #define REG_IQK_COM64 0x0980
637 #define REG_IQK_COM96 0x0984
639 #define REG_FAS 0x09a4
640 #define REG_RXSB 0x0a00
642 #define REG_CCK_RX 0x0a04
643 #define REG_CCK_PD_TH 0x0a0a
644 #define REG_PRECTRL 0x0a14
647 #define REG_CCA_MF 0x0a20
649 #define REG_CCK0_TX_FILTER1 0x0a20
650 #define REG_CCK0_TX_FILTER2 0x0a24
651 #define REG_CCK0_DEBUG_PORT 0x0a28
652 #define REG_CCK0_FAREPORT 0x0a2c
655 #define REG_FA_CCK 0x0a5c
657 #define REG_DIS_DPD 0x0a70
658 #define DIS_DPD_MASK GENMASK(9, 0)
659 #define DIS_DPD_RATE6M BIT(0)
669 #define DIS_DPD_RATEALL GENMASK(9, 0)
671 #define REG_CCA 0x0a70
673 #define REG_ANTSEL 0x0a74
675 #define REG_CCKTX 0x0a84
678 #define REG_CNTRST 0x0b58
680 #define REG_3WIRE_SWA 0x0c00
681 #define REG_RX_IQC_AB_A 0x0c10
682 #define REG_RX_IQC_CD_A 0x0c14
683 #define REG_TXSCALE_A 0x0c1c
685 #define REG_TX_AGC_A_CCK_11_CCK_1 0xc20
686 #define REG_TX_AGC_A_OFDM18_OFDM6 0xc24
687 #define REG_TX_AGC_A_OFDM54_OFDM24 0xc28
688 #define REG_TX_AGC_A_MCS3_MCS0 0xc2c
689 #define REG_TX_AGC_A_MCS7_MCS4 0xc30
690 #define REG_TX_AGC_A_MCS11_MCS8 0xc34
691 #define REG_TX_AGC_A_MCS15_MCS12 0xc38
692 #define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0 0xc3c
693 #define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4 0xc40
694 #define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8 0xc44
695 #define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2 0xc48
696 #define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6 0xc4c
697 #define REG_RXIGI_A 0x0c50
698 #define REG_TX_PWR_TRAINING_A 0x0c54
699 #define REG_CK_MONHA 0x0c5c
700 #define REG_AFE_PWR1_A 0x0c60
701 #define REG_AFE_PWR2_A 0x0c64
702 #define REG_RX_WAIT_CCA_TX_CCK_RFON_A 0x0c68
703 #define REG_OFDM0_XA_TX_IQ_IMBALANCE 0x0c80
704 #define REG_OFDM0_A_TX_AFE 0x0c84
705 #define REG_OFDM0_XB_TX_IQ_IMBALANCE 0x0c88
706 #define REG_TSSI_TRK_SW 0x0c8c
707 #define REG_LSSI_WRITE_A 0x0c90
708 #define REG_PREDISTA 0x0c90
709 #define REG_TXAGCIDX 0x0c94
710 #define REG_TX_AGC_A 0x0c94
711 #define REG_RFE_PINMUX_A 0x0cb0
712 #define REG_RFE_INV_A 0x0cb4
713 #define REG_RFE_CTRL8 0x0cb4
714 #define BIT_MASK_RFE_SEL89 GENMASK(7, 0)
715 #define PTA_CTRL_PIN 0x66
716 #define DPDT_CTRL_PIN 0x77
717 #define RFE_INV_MASK 0x3ff00000
718 #define REG_RFECTL_A 0x0cb8
719 #define REG_RFE_INV0 0x0cbc
720 #define REG_RFE_INV8 0x0cbd
721 #define BIT_MASK_RFE_INV89 GENMASK(1, 0)
722 #define REG_RFE_INV16 0x0cbe
725 #define REG_IQK_DPD_CFG 0x0cc4
726 #define REG_CFG_PMPD 0x0cc8
727 #define REG_IQC_Y 0x0ccc
728 #define REG_IQC_X 0x0cd4
729 #define REG_INTPO_SETA 0x0ce8
731 #define REG_IQKA_END 0x0d00
732 #define REG_PI_READ_A 0x0d04
733 #define REG_SI_READ_A 0x0d08
734 #define REG_IQKB_END 0x0d40
735 #define REG_PI_READ_B 0x0d44
736 #define REG_SI_READ_B 0x0d48
738 #define REG_3WIRE_SWB 0x0e00
739 #define REG_RX_IQC_AB_B 0x0e10
740 #define REG_RX_IQC_CD_B 0x0e14
741 #define REG_TXSCALE_B 0x0e1c
742 #define REG_TX_AGC_B_CCK_11_CCK_1 0xe20
743 #define REG_TX_AGC_B_OFDM18_OFDM6 0xe24
744 #define REG_TX_AGC_B_OFDM54_OFDM24 0xe28
745 #define REG_TX_AGC_B_MCS3_MCS0 0xe2c
746 #define REG_TX_AGC_B_MCS7_MCS4 0xe30
747 #define REG_TX_AGC_B_MCS11_MCS8 0xe34
748 #define REG_TX_AGC_B_MCS15_MCS12 0xe38
749 #define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0 0xe3c
750 #define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4 0xe40
751 #define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8 0xe44
752 #define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2 0xe48
753 #define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6 0xe4c
754 #define REG_RXIGI_B 0x0e50
755 #define REG_TX_PWR_TRAINING_B 0x0e54
756 #define REG_CK_MONHB 0x0e5c
757 #define REG_AFE_PWR1_B 0x0e60
758 #define REG_AFE_PWR2_B 0x0e64
759 #define REG_RX_WAIT_CCA_TX_CCK_RFON_B 0x0e68
760 #define REG_TXTONEB 0x0e80
761 #define REG_RXTONEB 0x0e84
762 #define REG_TXPITMB 0x0e88
763 #define REG_RXPITMB 0x0e8c
764 #define REG_LSSI_WRITE_B 0x0e90
765 #define REG_PREDISTB 0x0e90
766 #define REG_INIDLYB 0x0e94
767 #define REG_TX_AGC_B 0x0e94
768 #define REG_RFE_PINMUX_B 0x0eb0
769 #define REG_RFE_INV_B 0x0eb4
770 #define REG_RFECTL_B 0x0eb8
771 #define REG_BPBDB 0x0ec4
772 #define REG_PHYTXONB 0x0ec8
773 #define REG_IQKYB 0x0ecc
774 #define REG_IQKXB 0x0ed4
775 #define REG_INTPO_SETB 0x0ee8
777 #define REG_CRC_CCK 0x0f04
778 #define REG_CCA_OFDM 0x0f08
779 #define REG_CRC_VHT 0x0f0c
780 #define REG_CRC_HT 0x0f10
781 #define REG_CRC_OFDM 0x0f14
782 #define REG_FA_OFDM 0x0f48
783 #define REG_DBGRPT 0x0fa0
784 #define REG_CCA_CCK 0x0fcc
786 #define REG_SYS_CFG3_8814A 0x1000
788 #define REG_ANAPARSW_MAC_0 0x1010
791 #define REG_ANAPAR_XTAL_0 0x1040
793 #define REG_CPU_DMEM_CON 0x1080
798 #define REG_SW_MDIO 0x10C0
800 #define REG_H2C_PKT_READADDR 0x10D0
801 #define REG_H2C_PKT_WRITEADDR 0x10D4
802 #define REG_FW_DBG6 0x10F8
803 #define REG_FW_DBG7 0x10FC
804 #define FW_KEY_MASK 0xffffff00
806 #define REG_CR_EXT 0x1100
808 #define REG_FT1IMR 0x1138
810 #define REG_FT1ISR 0x113c
812 #define REG_DDMA_CH0SA 0x1200
813 #define REG_DDMA_CH0DA 0x1204
814 #define REG_DDMA_CH0CTRL 0x1208
821 #define BIT_MASK_DDMACH0_DLEN 0x3ffff
823 #define REG_H2CQ_CSR 0x1330
825 #define REG_FAST_EDCA_VOVI_SETTING 0x1448
826 #define REG_FAST_EDCA_BEBK_SETTING 0x144C
828 #define REG_RXPSF_CTRL 0x1610
832 #define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3
839 #define BIT_MASK_RXGCK_HT_FIFOTHR 0x3
846 #define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3
853 #define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3
862 #define BIT_MASK_RXPSF_PKTLENTHR 0x7
882 #define BIT_SHIFT_RXPSF_ERRTHR 0
883 #define BIT_MASK_RXPSF_ERRTHR 0x7
893 #define REG_RXPSF_TYPE_CTRL 0x1614
894 #define REG_GENERAL_OPTION 0x1664
897 #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700
898 #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704
899 #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708
905 #define REG_RX_IQC_AB_C 0x1810
906 #define REG_RX_IQC_CD_C 0x1814
907 #define REG_TXSCALE_C 0x181c
908 #define REG_CK_MONHC 0x185c
909 #define REG_AFE_PWR1_C 0x1860
910 #define REG_IGN_GNT_BT1 0x1860
911 #define REG_TX_AGC_C 0x1894
912 #define REG_RFE_PINMUX_C 0x18b4
914 #define REG_RFESEL_CTRL 0x1990
915 #define REG_AGC_TBL 0x1998
917 #define REG_RX_IQC_AB_D 0x1a10
918 #define REG_RX_IQC_CD_D 0x1a14
919 #define REG_TXSCALE_D 0x1a1c
920 #define REG_CK_MONHD 0x1a5c
921 #define REG_AFE_PWR1_D 0x1a60
922 #define REG_TX_AGC_D 0x1a94
923 #define REG_RFE_PINMUX_D 0x1ab4
924 #define REG_RFE_INVSEL_D 0x1abc
927 #define REG_NOMASK_TXBT 0x1ca7
928 #define REG_ANAPAR 0x1c30
930 #define REG_RSTB_SEL 0x1c38
935 #define REG_HRCV_MSG 0x1cf
937 #define REG_EDCCA_REPORT 0x2d38
940 #define REG_IGN_GNTBT4 0x4160
942 #define REG_USB_MOD 0xf008
943 #define REG_USB3_RXITV 0xf050
944 #define REG_USB2_PHY_ADR 0xfe40
945 #define REG_USB2_PHY_DAT 0xfe41
946 #define REG_USB2_PHY_CMD 0xfe42
947 #define BIT_USB2_PHY_CMD_TRG 0x81
948 #define REG_USB_HRPWM 0xfe58
949 #define REG_USB3_PHY_ADR 0xff0c
950 #define REG_USB3_PHY_DAT_L 0xff0d
951 #define REG_USB3_PHY_DAT_H 0xff0e
954 #define BIT_USB3_PHY_ADR_MASK GENMASK(5, 0)
956 #define RF_MODE 0x00
957 #define RF_MODOPT 0x01
958 #define RF_WLINT 0x01
959 #define RF_WLSEL 0x02
960 #define RF_DTXLOK 0x08
961 #define RF_CFGCH 0x18
966 #define RF_RCK1_V1 0x1c
967 #define RF_RCK 0x1d
968 #define RF_MODE_TABLE_ADDR 0x30
969 #define RF_MODE_TABLE_DATA0 0x31
970 #define RF_MODE_TABLE_DATA1 0x32
971 #define RF_LUTWA 0x33
972 #define RF_LUTWD1 0x3e
973 #define RF_LUTWD0 0x3f
975 #define BIT_DATA_L GENMASK(11, 0)
976 #define RF_T_METER 0x42
977 #define RF_BSPAD 0x54
978 #define RF_GAINTX 0x56
979 #define RF_TXMOD 0x58
980 #define RF_TXATANK 0x64
981 #define RF_TXA_PREPAD 0x65
982 #define RF_TRXIQ 0x66
983 #define RF_RXIQGEN 0x8d
984 #define RF_RXBB2 0x8f
985 #define RF_SYN_PFD 0xb0
986 #define RF_LCK 0xb4
987 #define RF_XTALX2 0xb8
988 #define RF_SYN_CTRL 0xbb
989 #define RF_MALSEL 0xbe
990 #define RF_SYN_AAC 0xc9
991 #define RF_AAC_CTRL 0xca
992 #define RF_FAST_LCK 0xcc
993 #define RF_RCKD 0xde
994 #define RF_TXADBG 0xde
995 #define RF_LUTDBG 0xdf
997 #define RF_LUTWE2 0xee
998 #define RF_LUTWE 0xef
1000 #define LTE_COEX_CTRL 0x38
1001 #define LTE_WL_TRX_CTRL 0xa0
1002 #define LTE_BT_TRX_CTRL 0xa4