Lines Matching refs:regd
12 #include "regd.h"
154 switch (rtwdev->regd.dfs_region) {
1580 static void rtw_phy_set_tx_power_limit(struct rtw_dev *rtwdev, u8 regd, u8 band,
1592 if (regd >= RTW_REGD_MAX || bw >= RTW_CHANNEL_WIDTH_MAX ||
1595 "wrong txpwr_lmt regd=%u, band=%u bw=%u, rs=%u, ch_idx=%u, pwr_limit=%d\n",
1596 regd, band, bw, rs, ch_idx, pwr_limit);
1601 hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit;
1606 hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit;
1615 rtw_xref_5g_txpwr_lmt(struct rtw_dev *rtwdev, u8 regd,
1620 s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx];
1621 s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx];
1627 hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht;
1630 hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht;
1635 rtw_xref_txpwr_lmt_by_rs(struct rtw_dev *rtwdev, u8 regd, u8 bw, u8 ch_idx)
1645 rtw_xref_5g_txpwr_lmt(rtwdev, regd, bw, ch_idx, rs_ht, rs_vht);
1651 rtw_xref_5g_txpwr_lmt_by_ch(struct rtw_dev *rtwdev, u8 regd, u8 bw)
1656 rtw_xref_txpwr_lmt_by_rs(rtwdev, regd, bw, ch_idx);
1661 rtw_xref_txpwr_lmt_by_bw(struct rtw_dev *rtwdev, u8 regd)
1666 rtw_xref_5g_txpwr_lmt_by_ch(rtwdev, regd, bw);
1672 u8 regd;
1674 for (regd = 0; regd < RTW_REGD_MAX; regd++)
1675 rtw_xref_txpwr_lmt_by_bw(rtwdev, regd);
1679 __cfg_txpwr_lmt_by_alt(struct rtw_hal *hal, u8 regd, u8 regd_alt, u8 bw, u8 rs)
1684 hal->tx_pwr_limit_2g[regd][bw][rs][ch] =
1688 hal->tx_pwr_limit_5g[regd][bw][rs][ch] =
1693 rtw_cfg_txpwr_lmt_by_alt(struct rtw_dev *rtwdev, u8 regd, u8 regd_alt)
1699 __cfg_txpwr_lmt_by_alt(&rtwdev->hal, regd, regd_alt,
1713 regd_cfg_flag |= BIT(p->regd);
1714 rtw_phy_set_tx_power_limit(rtwdev, p->regd, p->band,
1726 "txpwr regd %d does not be configured\n", i);
1731 "cfg txpwr regd %d by regd %d as alternative\n",
1738 rtw_dbg(rtwdev, RTW_DBG_REGD, "cfg txpwr regd %d by WW\n", i);
2078 u8 rate, u8 channel, u8 regd)
2088 if (regd > RTW_REGD_WW)
2111 hal->tx_pwr_limit_2g[regd][cur_bw][rs][ch_idx] :
2112 hal->tx_pwr_limit_5g[regd][cur_bw][rs][ch_idx];
2147 u8 ch, u8 regd, struct rtw_power_params *pwr_param)
2178 rate, ch, regd);
2186 enum rtw_bandwidth bandwidth, u8 channel, u8 regd)
2193 channel, regd, &pwr_param);
2216 u8 regd = rtw_regd_get(rtwdev);
2233 bw, ch, regd);
2325 __rtw_phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs)
2332 hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base;
2337 hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base;
2343 u8 regd, bw, rs;
2348 for (regd = 0; regd < RTW_REGD_MAX; regd++)
2351 __rtw_phy_tx_power_limit_config(hal, regd, bw, rs);
2355 u8 regd, u8 bw, u8 rs)
2363 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index;
2367 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index;
2373 u8 regd, path, rate, rs, bw;
2384 for (regd = 0; regd < RTW_REGD_MAX; regd++)
2387 rtw_phy_init_tx_power_limit(rtwdev, regd, bw,