Lines Matching refs:hal
233 struct rtw_hal *hal = &rtwdev->hal;
242 for (path = 0; path < hal->rf_path_num; path++) {
643 for (i = 0; i < rtwdev->hal.rf_path_num; i++) {
738 if (rtwdev->hal.current_band_type != RTW_BAND_2G)
907 struct rtw_hal *hal = &rtwdev->hal;
912 if (rf_path >= hal->rf_phy_num) {
930 struct rtw_hal *hal = &rtwdev->hal;
939 if (rf_path >= hal->rf_phy_num) {
979 struct rtw_hal *hal = &rtwdev->hal;
986 if (rf_path >= hal->rf_phy_num) {
1019 struct rtw_hal *hal = &rtwdev->hal;
1024 if (rf_path >= hal->rf_phy_num) {
1052 struct rtw_hal *hal = &rtwdev->hal;
1057 cond.cut = hal->cut_version ? hal->cut_version : 15;
1090 hal->phy_cond = cond;
1091 hal->phy_cond2 = cond2;
1094 *((u32 *)&hal->phy_cond), *((u32 *)&hal->phy_cond2));
1100 struct rtw_hal *hal = &rtwdev->hal;
1101 struct rtw_phy_cond drv_cond = hal->phy_cond;
1102 struct rtw_phy_cond2 drv_cond2 = hal->phy_cond2;
1505 struct rtw_hal *hal = &rtwdev->hal;
1525 hal->tx_pwr_by_rate_offset_2g[rfpath][rate] = offset;
1527 hal->tx_pwr_by_rate_offset_5g[rfpath][rate] = offset;
1583 struct rtw_hal *hal = &rtwdev->hal;
1601 hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit;
1602 ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx];
1604 hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1606 hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit;
1607 ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx];
1609 hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1618 struct rtw_hal *hal = &rtwdev->hal;
1620 s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx];
1621 s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx];
1627 hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht;
1630 hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht;
1679 __cfg_txpwr_lmt_by_alt(struct rtw_hal *hal, u8 regd, u8 regd_alt, u8 bw, u8 rs)
1684 hal->tx_pwr_limit_2g[regd][bw][rs][ch] =
1685 hal->tx_pwr_limit_2g[regd_alt][bw][rs][ch];
1688 hal->tx_pwr_limit_5g[regd][bw][rs][ch] =
1689 hal->tx_pwr_limit_5g[regd_alt][bw][rs][ch];
1699 __cfg_txpwr_lmt_by_alt(&rtwdev->hal, regd, regd_alt,
1826 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) {
2080 struct rtw_hal *hal = &rtwdev->hal;
2081 u8 *cch_by_bw = hal->cch_by_bw;
2111 hal->tx_pwr_limit_2g[regd][cur_bw][rs][ch_idx] :
2112 hal->tx_pwr_limit_5g[regd][cur_bw][rs][ch_idx];
2149 struct rtw_hal *hal = &rtwdev->hal;
2168 *offset = hal->tx_pwr_by_rate_offset_2g[path][rate];
2174 *offset = hal->tx_pwr_by_rate_offset_5g[path][rate];
2181 *sar = rtw_phy_get_tx_power_sar(rtwdev, hal->sar_band, path, rate);
2215 struct rtw_hal *hal = &rtwdev->hal;
2229 bw = hal->current_band_width;
2234 hal->tx_pwr_tbl[path][rate] = pwr_idx;
2246 struct rtw_hal *hal = &rtwdev->hal;
2250 if (hal->current_band_type == RTW_BAND_2G)
2262 struct rtw_hal *hal = &rtwdev->hal;
2265 mutex_lock(&hal->tx_power_mutex);
2267 for (path = 0; path < hal->rf_path_num; path++)
2271 mutex_unlock(&hal->tx_power_mutex);
2276 rtw_phy_tx_power_by_rate_config_by_path(struct rtw_hal *hal, u8 path,
2287 base_2g = hal->tx_pwr_by_rate_offset_2g[path][base_idx];
2288 base_5g = hal->tx_pwr_by_rate_offset_5g[path][base_idx];
2289 hal->tx_pwr_by_rate_base_2g[path][rs] = base_2g;
2290 hal->tx_pwr_by_rate_base_5g[path][rs] = base_5g;
2293 hal->tx_pwr_by_rate_offset_2g[path][rate_idx] -= base_2g;
2294 hal->tx_pwr_by_rate_offset_5g[path][rate_idx] -= base_5g;
2298 void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal)
2303 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2306 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2309 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2312 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2315 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2318 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2325 __rtw_phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs)
2331 base = hal->tx_pwr_by_rate_base_2g[0][rs];
2332 hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base;
2336 base = hal->tx_pwr_by_rate_base_5g[0][rs];
2337 hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base;
2341 void rtw_phy_tx_power_limit_config(struct rtw_hal *hal)
2346 hal->cch_by_bw[RTW_CHANNEL_WIDTH_20] = 1;
2351 __rtw_phy_tx_power_limit_config(hal, regd, bw, rs);
2357 struct rtw_hal *hal = &rtwdev->hal;
2363 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index;
2367 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index;
2372 struct rtw_hal *hal = &rtwdev->hal;
2378 hal->tx_pwr_by_rate_offset_2g[path][rate] = 0;
2379 hal->tx_pwr_by_rate_offset_5g[path][rate] = 0;
2396 u8 channel = rtwdev->hal.current_channel;
2545 chip->ops->config_tx_path(rtwdev, rtwdev->hal.antenna_tx,
2576 if (rtwdev->hal.antenna_rx != BB_PATH_AB) {
2579 rtwdev->hal.antenna_tx, rtwdev->hal.antenna_rx);