Lines Matching +full:sar +full:- +full:threshold
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
13 #include "sar.h"
149 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_cck_pd_init()
154 dm_info->cck_pd_lv[i][j] = CCK_PD_LV0; in rtw_phy_cck_pd_init()
157 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; in rtw_phy_cck_pd_init()
162 const struct rtw_hw_reg_offset *edcca_th = rtwdev->chip->edcca_th; in rtw_phy_set_edcca_th()
177 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_adaptivity_set_mode()
178 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_adaptivity_set_mode()
182 dm_info->edcca_mode = RTW_EDCCA_NORMAL; in rtw_phy_adaptivity_set_mode()
187 switch (rtwdev->regd.dfs_region) { in rtw_phy_adaptivity_set_mode()
189 dm_info->edcca_mode = RTW_EDCCA_ADAPTIVITY; in rtw_phy_adaptivity_set_mode()
190 dm_info->l2h_th_ini = chip->l2h_th_ini_ad; in rtw_phy_adaptivity_set_mode()
193 dm_info->edcca_mode = RTW_EDCCA_ADAPTIVITY; in rtw_phy_adaptivity_set_mode()
194 dm_info->l2h_th_ini = chip->l2h_th_ini_cs; in rtw_phy_adaptivity_set_mode()
197 dm_info->edcca_mode = RTW_EDCCA_NORMAL; in rtw_phy_adaptivity_set_mode()
204 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_adaptivity_init()
207 if (chip->ops->adaptivity_init) in rtw_phy_adaptivity_init()
208 chip->ops->adaptivity_init(rtwdev); in rtw_phy_adaptivity_init()
213 if (rtwdev->chip->ops->adaptivity) in rtw_phy_adaptivity()
214 rtwdev->chip->ops->adaptivity(rtwdev); in rtw_phy_adaptivity()
219 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_cfo_init()
221 if (chip->ops->cfo_init) in rtw_phy_cfo_init()
222 chip->ops->cfo_init(rtwdev); in rtw_phy_cfo_init()
227 struct rtw_path_div *path_div = &rtwdev->dm_path_div; in rtw_phy_tx_path_div_init()
229 path_div->current_tx_path = rtwdev->chip->default_1ss_tx_path; in rtw_phy_tx_path_div_init()
230 path_div->path_a_cnt = 0; in rtw_phy_tx_path_div_init()
231 path_div->path_a_sum = 0; in rtw_phy_tx_path_div_init()
232 path_div->path_b_cnt = 0; in rtw_phy_tx_path_div_init()
233 path_div->path_b_sum = 0; in rtw_phy_tx_path_div_init()
238 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_init()
239 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_init()
242 dm_info->fa_history[3] = 0; in rtw_phy_init()
243 dm_info->fa_history[2] = 0; in rtw_phy_init()
244 dm_info->fa_history[1] = 0; in rtw_phy_init()
245 dm_info->fa_history[0] = 0; in rtw_phy_init()
246 dm_info->igi_bitmap = 0; in rtw_phy_init()
247 dm_info->igi_history[3] = 0; in rtw_phy_init()
248 dm_info->igi_history[2] = 0; in rtw_phy_init()
249 dm_info->igi_history[1] = 0; in rtw_phy_init()
251 addr = chip->dig[0].addr; in rtw_phy_init()
252 mask = chip->dig[0].mask; in rtw_phy_init()
253 dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask); in rtw_phy_init()
256 dm_info->iqk.done = false; in rtw_phy_init()
265 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_dig_write()
266 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_dig_write()
270 if (chip->dig_cck) { in rtw_phy_dig_write()
271 const struct rtw_hw_reg *dig_cck = &chip->dig_cck[0]; in rtw_phy_dig_write()
272 rtw_write32_mask(rtwdev, dig_cck->addr, dig_cck->mask, igi >> 1); in rtw_phy_dig_write()
275 for (path = 0; path < hal->rf_path_num; path++) { in rtw_phy_dig_write()
276 addr = chip->dig[path].addr; in rtw_phy_dig_write()
277 mask = chip->dig[path].mask; in rtw_phy_dig_write()
284 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_stat_false_alarm()
286 chip->ops->false_alarm_statistics(rtwdev); in rtw_phy_stat_false_alarm()
320 struct rtw_dev *rtwdev = iter_data->rtwdev; in rtw_phy_stat_rssi_iter()
321 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; in rtw_phy_stat_rssi_iter()
324 rssi = ewma_rssi_read(&si->avg_rssi); in rtw_phy_stat_rssi_iter()
325 si->rssi_level = rtw_phy_get_rssi_level(si->rssi_level, rssi); in rtw_phy_stat_rssi_iter()
329 iter_data->min_rssi = min_t(u8, rssi, iter_data->min_rssi); in rtw_phy_stat_rssi_iter()
334 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_stat_rssi()
341 dm_info->pre_min_rssi = dm_info->min_rssi; in rtw_phy_stat_rssi()
342 dm_info->min_rssi = data.min_rssi; in rtw_phy_stat_rssi()
347 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_stat_rate_cnt()
349 dm_info->last_pkt_count = dm_info->cur_pkt_count; in rtw_phy_stat_rate_cnt()
350 memset(&dm_info->cur_pkt_count, 0, sizeof(dm_info->cur_pkt_count)); in rtw_phy_stat_rate_cnt()
386 min_rssi = dm_info->min_rssi; in rtw_phy_dig_check_damping()
387 if (dm_info->damping) { in rtw_phy_dig_check_damping()
388 damping_rssi = dm_info->damping_rssi; in rtw_phy_dig_check_damping()
389 diff = min_rssi > damping_rssi ? min_rssi - damping_rssi : in rtw_phy_dig_check_damping()
390 damping_rssi - min_rssi; in rtw_phy_dig_check_damping()
391 if (diff > 3 || dm_info->damping_cnt++ > 20) { in rtw_phy_dig_check_damping()
392 dm_info->damping = false; in rtw_phy_dig_check_damping()
399 igi_history = dm_info->igi_history; in rtw_phy_dig_check_damping()
400 fa_history = dm_info->fa_history; in rtw_phy_dig_check_damping()
401 igi_bitmap = dm_info->igi_bitmap & 0xf; in rtw_phy_dig_check_damping()
404 /* down -> up -> down -> up */ in rtw_phy_dig_check_damping()
407 igi_history[0] - igi_history[1] >= 2 && in rtw_phy_dig_check_damping()
408 igi_history[2] - igi_history[3] >= 2 && in rtw_phy_dig_check_damping()
414 /* up -> down -> down -> up */ in rtw_phy_dig_check_damping()
417 igi_history[0] - igi_history[1] >= 4 && in rtw_phy_dig_check_damping()
418 igi_history[3] - igi_history[2] >= 2 && in rtw_phy_dig_check_damping()
428 dm_info->damping = true; in rtw_phy_dig_check_damping()
429 dm_info->damping_cnt = 0; in rtw_phy_dig_check_damping()
430 dm_info->damping_rssi = min_rssi; in rtw_phy_dig_check_damping()
446 dig_min = rtwdev->chip->dig_min; in rtw_phy_dig_get_boundary()
447 min_rssi = max_t(u8, dm_info->min_rssi, dig_min); in rtw_phy_dig_get_boundary()
467 min_rssi = dm_info->min_rssi; in rtw_phy_dig_get_threshold()
468 pre_min_rssi = dm_info->pre_min_rssi; in rtw_phy_dig_get_threshold()
496 igi_bitmap = dm_info->igi_bitmap << 1 & 0xfe; in rtw_phy_dig_recorder()
497 igi_history = dm_info->igi_history; in rtw_phy_dig_recorder()
498 fa_history = dm_info->fa_history; in rtw_phy_dig_recorder()
513 dm_info->igi_bitmap = igi_bitmap; in rtw_phy_dig_recorder()
518 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_dig()
526 if (test_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags)) in rtw_phy_dig()
532 linked = !!rtwdev->sta_cnt; in rtw_phy_dig()
534 fa_cnt = dm_info->total_fa_cnt; in rtw_phy_dig()
535 pre_igi = dm_info->igi_history[0]; in rtw_phy_dig()
539 /* test the false alarm count from the highest threshold level first, in rtw_phy_dig()
542 * note that the step size is offset by -2, compensate it afterall in rtw_phy_dig()
551 cur_igi -= 2; in rtw_phy_dig()
569 if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A && rtwdev->beacon_loss && in rtw_phy_dig()
570 linked && dm_info->total_fa_cnt < DIG_PERF_FA_TH_EXTRA_HIGH) in rtw_phy_dig()
580 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; in rtw_phy_ra_info_update_iter()
587 if (rtwdev->watch_dog_cnt & 0x3) in rtw_phy_ra_info_update()
600 rate_order -= DESC_RATEVHT4SS_MCS0; in rtw_phy_get_rrsr_mask()
602 rate_order -= DESC_RATEVHT3SS_MCS0; in rtw_phy_get_rrsr_mask()
604 rate_order -= DESC_RATEVHT2SS_MCS0; in rtw_phy_get_rrsr_mask()
606 rate_order -= DESC_RATEVHT1SS_MCS0; in rtw_phy_get_rrsr_mask()
608 rate_order -= DESC_RATEMCS24; in rtw_phy_get_rrsr_mask()
610 rate_order -= DESC_RATEMCS16; in rtw_phy_get_rrsr_mask()
612 rate_order -= DESC_RATEMCS8; in rtw_phy_get_rrsr_mask()
614 rate_order -= DESC_RATEMCS0; in rtw_phy_get_rrsr_mask()
616 rate_order -= DESC_RATE6M; in rtw_phy_get_rrsr_mask()
618 rate_order -= DESC_RATE1M; in rtw_phy_get_rrsr_mask()
623 return GENMASK(rate_order + RRSR_RATE_ORDER_CCK_LEN - 1, 0); in rtw_phy_get_rrsr_mask()
629 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; in rtw_phy_rrsr_mask_min_iter()
630 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_rrsr_mask_min_iter()
633 mask = rtw_phy_get_rrsr_mask(rtwdev, si->ra_report.desc_rate); in rtw_phy_rrsr_mask_min_iter()
634 if (mask < dm_info->rrsr_mask_min) in rtw_phy_rrsr_mask_min_iter()
635 dm_info->rrsr_mask_min = mask; in rtw_phy_rrsr_mask_min_iter()
640 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_rrsr_update()
642 dm_info->rrsr_mask_min = RRSR_RATE_ORDER_MAX; in rtw_phy_rrsr_update()
644 rtw_write32(rtwdev, REG_RRSR, dm_info->rrsr_val_init & dm_info->rrsr_mask_min); in rtw_phy_rrsr_update()
649 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_dpk_track()
651 if (chip->ops->dpk_track) in rtw_phy_dpk_track()
652 chip->ops->dpk_track(rtwdev); in rtw_phy_dpk_track()
666 struct rtw_dev *rtwdev = iter_data->rtwdev; in rtw_phy_parsing_cfo_iter()
667 struct rtw_rx_pkt_stat *pkt_stat = iter_data->pkt_stat; in rtw_phy_parsing_cfo_iter()
668 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_parsing_cfo_iter()
669 struct rtw_cfo_track *cfo = &dm_info->cfo_track; in rtw_phy_parsing_cfo_iter()
670 u8 *bssid = iter_data->bssid; in rtw_phy_parsing_cfo_iter()
673 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) in rtw_phy_parsing_cfo_iter()
676 for (i = 0; i < rtwdev->hal.rf_path_num; i++) { in rtw_phy_parsing_cfo_iter()
677 cfo->cfo_tail[i] += pkt_stat->cfo_tail[i]; in rtw_phy_parsing_cfo_iter()
678 cfo->cfo_cnt[i]++; in rtw_phy_parsing_cfo_iter()
681 cfo->packet_count++; in rtw_phy_parsing_cfo_iter()
687 struct ieee80211_hdr *hdr = pkt_stat->hdr; in rtw_phy_parsing_cfo()
690 if (pkt_stat->crc_err || pkt_stat->icv_err || !pkt_stat->phy_status || in rtw_phy_parsing_cfo()
691 ieee80211_is_ctl(hdr->frame_control)) in rtw_phy_parsing_cfo()
705 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_cfo_track()
707 if (chip->ops->cfo_track) in rtw_phy_cfo_track()
708 chip->ops->cfo_track(rtwdev); in rtw_phy_cfo_track()
716 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_cck_pd_lv_unlink()
717 u32 cck_fa_avg = dm_info->cck_fa_avg; in rtw_phy_cck_pd_lv_unlink()
737 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_cck_pd_lv_link()
738 u8 igi = dm_info->igi_history[0]; in rtw_phy_cck_pd_lv_link()
739 u8 rssi = dm_info->min_rssi; in rtw_phy_cck_pd_lv_link()
740 u32 cck_fa_avg = dm_info->cck_fa_avg; in rtw_phy_cck_pd_lv_link()
766 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_cck_pd()
767 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_cck_pd()
768 u32 cck_fa = dm_info->cck_fa_cnt; in rtw_phy_cck_pd()
771 if (rtwdev->hal.current_band_type != RTW_BAND_2G) in rtw_phy_cck_pd()
774 if (dm_info->cck_fa_avg == CCK_FA_AVG_RESET) in rtw_phy_cck_pd()
775 dm_info->cck_fa_avg = cck_fa; in rtw_phy_cck_pd()
777 dm_info->cck_fa_avg = (dm_info->cck_fa_avg * 3 + cck_fa) >> 2; in rtw_phy_cck_pd()
780 dm_info->igi_history[0], dm_info->min_rssi, in rtw_phy_cck_pd()
781 dm_info->fa_history[0]); in rtw_phy_cck_pd()
783 dm_info->cck_fa_avg, dm_info->cck_pd_default); in rtw_phy_cck_pd()
790 if (chip->ops->cck_pd_set) in rtw_phy_cck_pd()
791 chip->ops->cck_pd_set(rtwdev, level); in rtw_phy_cck_pd()
796 rtwdev->chip->ops->pwr_track(rtwdev); in rtw_phy_pwr_track()
818 if (rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_ADAPTIVITY)) in rtw_phy_dynamic_mechanism()
828 if (power <= -100 || power >= 20) in rtw_phy_power_2_db()
847 i = (power_db - 1) >> 3; in rtw_phy_db_2_linear()
848 j = (power_db - 1) - (i << 3); in rtw_phy_db_2_linear()
879 if (db_invert_table[i][0] - linear > in rtw_phy_linear_2_db()
880 linear - db_invert_table[i - 1][7]) { in rtw_phy_linear_2_db()
881 i = i - 1; in rtw_phy_linear_2_db()
885 if (db_invert_table[3][0] - linear > in rtw_phy_linear_2_db()
886 linear - db_invert_table[2][7]) { in rtw_phy_linear_2_db()
892 if (db_invert_table[i][j] - linear > in rtw_phy_linear_2_db()
893 linear - db_invert_table[i][j - 1]) { in rtw_phy_linear_2_db()
894 j = j - 1; in rtw_phy_linear_2_db()
918 sum = (sum + (1 << (FRAC_BITS - 1))) >> FRAC_BITS; in rtw_phy_rf_power_2_rssi()
940 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_read_rf()
941 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_read_rf()
942 const u32 *base_addr = chip->rf_base_addr; in rtw_phy_read_rf()
945 if (rf_path >= hal->rf_phy_num) { in rtw_phy_read_rf()
963 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_read_rf_sipi()
964 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_read_rf_sipi()
972 if (rf_path >= hal->rf_phy_num) { in rtw_phy_read_rf_sipi()
977 if (!chip->rf_sipi_read_addr) { in rtw_phy_read_rf_sipi()
982 rf_sipi_addr = &chip->rf_sipi_read_addr[rf_path]; in rtw_phy_read_rf_sipi()
983 rf_sipi_addr_a = &chip->rf_sipi_read_addr[RF_PATH_A]; in rtw_phy_read_rf_sipi()
987 val32 = rtw_read32(rtwdev, rf_sipi_addr->hssi_2); in rtw_phy_read_rf_sipi()
989 rtw_write32(rtwdev, rf_sipi_addr->hssi_2, val32); in rtw_phy_read_rf_sipi()
992 val32 = rtw_read32(rtwdev, rf_sipi_addr_a->hssi_2); in rtw_phy_read_rf_sipi()
993 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 & ~LSSI_READ_EDGE_MASK); in rtw_phy_read_rf_sipi()
994 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 | LSSI_READ_EDGE_MASK); in rtw_phy_read_rf_sipi()
998 en_pi = rtw_read32_mask(rtwdev, rf_sipi_addr->hssi_1, BIT(8)); in rtw_phy_read_rf_sipi()
999 r_addr = en_pi ? rf_sipi_addr->lssi_read_pi : rf_sipi_addr->lssi_read; in rtw_phy_read_rf_sipi()
1012 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_write_rf_reg_sipi()
1013 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_write_rf_reg_sipi()
1014 const u32 *sipi_addr = chip->rf_sipi_addr; in rtw_phy_write_rf_reg_sipi()
1019 if (rf_path >= hal->rf_phy_num) { in rtw_phy_write_rf_reg_sipi()
1028 old_data = chip->ops->read_rf(rtwdev, rf_path, addr, RFREG_MASK); in rtw_phy_write_rf_reg_sipi()
1052 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_write_rf_reg()
1053 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_write_rf_reg()
1054 const u32 *base_addr = chip->rf_base_addr; in rtw_phy_write_rf_reg()
1057 if (rf_path >= hal->rf_phy_num) { in rtw_phy_write_rf_reg()
1085 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_setup_phy_cond()
1086 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw_phy_setup_phy_cond()
1090 cond.cut = hal->cut_version ? hal->cut_version : 15; in rtw_phy_setup_phy_cond()
1093 cond.rfe = efuse->rfe_option; in rtw_phy_setup_phy_cond()
1108 if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A || in rtw_phy_setup_phy_cond()
1109 rtwdev->chip->id == RTW_CHIP_TYPE_8821A) { in rtw_phy_setup_phy_cond()
1111 cond.rfe |= efuse->ext_lna_2g; in rtw_phy_setup_phy_cond()
1112 cond.rfe |= efuse->ext_pa_2g << 1; in rtw_phy_setup_phy_cond()
1113 cond.rfe |= efuse->ext_lna_5g << 2; in rtw_phy_setup_phy_cond()
1114 cond.rfe |= efuse->ext_pa_5g << 3; in rtw_phy_setup_phy_cond()
1115 cond.rfe |= efuse->btcoex << 4; in rtw_phy_setup_phy_cond()
1117 cond2.type_alna = efuse->alna_type; in rtw_phy_setup_phy_cond()
1118 cond2.type_glna = efuse->glna_type; in rtw_phy_setup_phy_cond()
1119 cond2.type_apa = efuse->apa_type; in rtw_phy_setup_phy_cond()
1120 cond2.type_gpa = efuse->gpa_type; in rtw_phy_setup_phy_cond()
1123 hal->phy_cond = cond; in rtw_phy_setup_phy_cond()
1124 hal->phy_cond2 = cond2; in rtw_phy_setup_phy_cond()
1127 *((u32 *)&hal->phy_cond), *((u32 *)&hal->phy_cond2)); in rtw_phy_setup_phy_cond()
1133 struct rtw_hal *hal = &rtwdev->hal; in check_positive()
1134 struct rtw_phy_cond drv_cond = hal->phy_cond; in check_positive()
1135 struct rtw_phy_cond2 drv_cond2 = hal->phy_cond2; in check_positive()
1146 if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A || in check_positive()
1147 rtwdev->chip->id == RTW_CHIP_TYPE_8821A) { in check_positive()
1175 const union phy_table_tile *p = tbl->data; in rtw_parse_tbl_phy_cond()
1176 const union phy_table_tile *end = p + tbl->size / 2; in rtw_parse_tbl_phy_cond()
1184 if (p->cond.pos) { in rtw_parse_tbl_phy_cond()
1185 switch (p->cond.branch) { in rtw_parse_tbl_phy_cond()
1196 pos_cond = p->cond; in rtw_parse_tbl_phy_cond()
1197 pos_cond2 = p->cond2; in rtw_parse_tbl_phy_cond()
1200 } else if (p->cond.neg) { in rtw_parse_tbl_phy_cond()
1213 (*tbl->do_cfg)(rtwdev, tbl, p->cfg.addr, p->cfg.data); in rtw_parse_tbl_phy_cond()
1223 if (rtwdev->chip->is_pwr_by_rate_dec) in tbl_to_dec_pwr_by_rate()
1268 pwr_by_rate[i - 1] = in rtw_phy_get_rate_values_of_txpwr_by_rate()
1322 pwr_by_rate[i - 1] = tbl_to_dec_pwr_by_rate(rtwdev, in rtw_phy_get_rate_values_of_txpwr_by_rate()
1538 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_store_tx_power_by_rate()
1558 hal->tx_pwr_by_rate_offset_2g[rfpath][rate] = offset; in rtw_phy_store_tx_power_by_rate()
1560 hal->tx_pwr_by_rate_offset_5g[rfpath][rate] = offset; in rtw_phy_store_tx_power_by_rate()
1566 const struct rtw_phy_pg_cfg_pair *p = tbl->data; in rtw_parse_tbl_bb_pg()
1567 const struct rtw_phy_pg_cfg_pair *end = p + tbl->size; in rtw_parse_tbl_bb_pg()
1570 if (p->addr == 0xfe || p->addr == 0xffe) { in rtw_parse_tbl_bb_pg()
1574 rtw_phy_store_tx_power_by_rate(rtwdev, p->band, p->rf_path, in rtw_parse_tbl_bb_pg()
1575 p->tx_num, p->addr, p->bitmask, in rtw_parse_tbl_bb_pg()
1576 p->data); in rtw_parse_tbl_bb_pg()
1596 ch_idx = channel - 1; in rtw_channel_to_idx()
1604 return -1; in rtw_channel_to_idx()
1608 return -1; in rtw_channel_to_idx()
1616 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_set_tx_power_limit()
1617 u8 max_power_index = rtwdev->chip->max_power_index; in rtw_phy_set_tx_power_limit()
1622 -max_power_index, max_power_index); in rtw_phy_set_tx_power_limit()
1634 hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit; in rtw_phy_set_tx_power_limit()
1635 ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx]; in rtw_phy_set_tx_power_limit()
1637 hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww; in rtw_phy_set_tx_power_limit()
1639 hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit; in rtw_phy_set_tx_power_limit()
1640 ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx]; in rtw_phy_set_tx_power_limit()
1642 hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww; in rtw_phy_set_tx_power_limit()
1646 /* cross-reference 5G power limits if values are not assigned */
1651 struct rtw_hal *hal = &rtwdev->hal; in rtw_xref_5g_txpwr_lmt()
1652 u8 max_power_index = rtwdev->chip->max_power_index; in rtw_xref_5g_txpwr_lmt()
1653 s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx]; in rtw_xref_5g_txpwr_lmt()
1654 s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx]; in rtw_xref_5g_txpwr_lmt()
1660 hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht; in rtw_xref_5g_txpwr_lmt()
1663 hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht; in rtw_xref_5g_txpwr_lmt()
1666 /* cross-reference power limits for ht and vht */
1686 /* cross-reference power limits for 5G channels */
1696 /* cross-reference power limits for 20/40M bandwidth */
1706 /* cross-reference power limits */
1721 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = in __cfg_txpwr_lmt_by_alt()
1722 hal->tx_pwr_limit_2g[regd_alt][bw][rs][ch]; in __cfg_txpwr_lmt_by_alt()
1725 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = in __cfg_txpwr_lmt_by_alt()
1726 hal->tx_pwr_limit_5g[regd_alt][bw][rs][ch]; in __cfg_txpwr_lmt_by_alt()
1736 __cfg_txpwr_lmt_by_alt(&rtwdev->hal, regd, regd_alt, in rtw_cfg_txpwr_lmt_by_alt()
1743 const struct rtw_txpwr_lmt_cfg_pair *p = tbl->data; in rtw_parse_tbl_txpwr_lmt()
1744 const struct rtw_txpwr_lmt_cfg_pair *end = p + tbl->size; in rtw_parse_tbl_txpwr_lmt()
1750 regd_cfg_flag |= BIT(p->regd); in rtw_parse_tbl_txpwr_lmt()
1751 rtw_phy_set_tx_power_limit(rtwdev, p->regd, p->band, in rtw_parse_tbl_txpwr_lmt()
1752 p->bw, p->rs, p->ch, p->txpwr_lmt); in rtw_parse_tbl_txpwr_lmt()
1825 rtw_write_rf(rtwdev, tbl->rf_path, addr, RFREG_MASK, data); in rtw_phy_cfg_rf()
1833 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_load_rfk_table()
1834 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; in rtw_load_rfk_table()
1836 if (!chip->rfk_init_tbl) in rtw_load_rfk_table()
1845 rtw_load_table(rtwdev, chip->rfk_init_tbl); in rtw_load_rfk_table()
1847 dpk_info->is_dpk_pwr_on = true; in rtw_load_rfk_table()
1853 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_load_tables()
1856 rtw_load_table(rtwdev, chip->mac_tbl); in rtw_phy_load_tables()
1857 rtw_load_table(rtwdev, chip->bb_tbl); in rtw_phy_load_tables()
1858 rtw_load_table(rtwdev, chip->agc_tbl); in rtw_phy_load_tables()
1859 if (rfe_def->agc_btg_tbl) in rtw_phy_load_tables()
1860 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); in rtw_phy_load_tables()
1863 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) { in rtw_phy_load_tables()
1866 tbl = chip->rf_tbl[rf_path]; in rtw_phy_load_tables()
1964 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_get_dis_dpd_by_rate_diff()
1967 if (!chip->en_dis_dpd) in rtw_phy_get_dis_dpd_by_rate_diff()
1972 if (DIS_DPD_RATE ## _rate & chip->dpd_ratemask) \ in rtw_phy_get_dis_dpd_by_rate_diff()
1973 dpd_diff = -6 * chip->txgi_factor; \ in rtw_phy_get_dis_dpd_by_rate_diff()
1998 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_get_2g_tx_power_index()
2000 u8 factor = chip->txgi_factor; in rtw_phy_get_2g_tx_power_index()
2005 tx_power = pwr_idx_2g->cck_base[group]; in rtw_phy_get_2g_tx_power_index()
2007 tx_power = pwr_idx_2g->bw40_base[group]; in rtw_phy_get_2g_tx_power_index()
2010 tx_power += pwr_idx_2g->ht_1s_diff.ofdm * factor; in rtw_phy_get_2g_tx_power_index()
2030 tx_power += pwr_idx_2g->ht_1s_diff.bw20 * factor; in rtw_phy_get_2g_tx_power_index()
2032 tx_power += pwr_idx_2g->ht_2s_diff.bw20 * factor; in rtw_phy_get_2g_tx_power_index()
2034 tx_power += pwr_idx_2g->ht_3s_diff.bw20 * factor; in rtw_phy_get_2g_tx_power_index()
2036 tx_power += pwr_idx_2g->ht_4s_diff.bw20 * factor; in rtw_phy_get_2g_tx_power_index()
2041 tx_power += pwr_idx_2g->ht_2s_diff.bw40 * factor; in rtw_phy_get_2g_tx_power_index()
2043 tx_power += pwr_idx_2g->ht_3s_diff.bw40 * factor; in rtw_phy_get_2g_tx_power_index()
2045 tx_power += pwr_idx_2g->ht_4s_diff.bw40 * factor; in rtw_phy_get_2g_tx_power_index()
2057 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_get_5g_tx_power_index()
2059 u8 factor = chip->txgi_factor; in rtw_phy_get_5g_tx_power_index()
2064 tx_power = pwr_idx_5g->bw40_base[group]; in rtw_phy_get_5g_tx_power_index()
2077 tx_power += pwr_idx_5g->ht_1s_diff.ofdm * factor; in rtw_phy_get_5g_tx_power_index()
2086 tx_power += pwr_idx_5g->ht_1s_diff.bw20 * factor; in rtw_phy_get_5g_tx_power_index()
2088 tx_power += pwr_idx_5g->ht_2s_diff.bw20 * factor; in rtw_phy_get_5g_tx_power_index()
2090 tx_power += pwr_idx_5g->ht_3s_diff.bw20 * factor; in rtw_phy_get_5g_tx_power_index()
2092 tx_power += pwr_idx_5g->ht_4s_diff.bw20 * factor; in rtw_phy_get_5g_tx_power_index()
2097 tx_power += pwr_idx_5g->ht_2s_diff.bw40 * factor; in rtw_phy_get_5g_tx_power_index()
2099 tx_power += pwr_idx_5g->ht_3s_diff.bw40 * factor; in rtw_phy_get_5g_tx_power_index()
2101 tx_power += pwr_idx_5g->ht_4s_diff.bw40 * factor; in rtw_phy_get_5g_tx_power_index()
2104 /* the base idx of bw80 is the average of bw40+/bw40- */ in rtw_phy_get_5g_tx_power_index()
2105 lower = pwr_idx_5g->bw40_base[group]; in rtw_phy_get_5g_tx_power_index()
2106 upper = pwr_idx_5g->bw40_base[group + 1]; in rtw_phy_get_5g_tx_power_index()
2109 tx_power += pwr_idx_5g->vht_1s_diff.bw80 * factor; in rtw_phy_get_5g_tx_power_index()
2111 tx_power += pwr_idx_5g->vht_2s_diff.bw80 * factor; in rtw_phy_get_5g_tx_power_index()
2113 tx_power += pwr_idx_5g->vht_3s_diff.bw80 * factor; in rtw_phy_get_5g_tx_power_index()
2115 tx_power += pwr_idx_5g->vht_4s_diff.bw80 * factor; in rtw_phy_get_5g_tx_power_index()
2153 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_get_tx_power_limit()
2154 u8 *cch_by_bw = hal->cch_by_bw; in rtw_phy_get_tx_power_limit()
2155 s8 power_limit = (s8)rtwdev->chip->max_power_index; in rtw_phy_get_tx_power_limit()
2184 hal->tx_pwr_limit_2g[regd][cur_bw][rs][ch_idx] : in rtw_phy_get_tx_power_limit()
2185 hal->tx_pwr_limit_5g[regd][cur_bw][rs][ch_idx]; in rtw_phy_get_tx_power_limit()
2195 return (s8)rtwdev->chip->max_power_index; in rtw_phy_get_tx_power_limit()
2216 return (s8)rtwdev->chip->max_power_index; in rtw_phy_get_tx_power_sar()
2222 struct rtw_hal *hal = &rtwdev->hal; in rtw_get_tx_power_params()
2223 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_get_tx_power_params()
2226 u8 *base = &pwr_param->pwr_base; in rtw_get_tx_power_params()
2227 s8 *offset = &pwr_param->pwr_offset; in rtw_get_tx_power_params()
2228 s8 *limit = &pwr_param->pwr_limit; in rtw_get_tx_power_params()
2229 s8 *remnant = &pwr_param->pwr_remnant; in rtw_get_tx_power_params()
2230 s8 *sar = &pwr_param->pwr_sar; in rtw_get_tx_power_params() local
2232 pwr_idx = &rtwdev->efuse.txpwr_idx_table[path]; in rtw_get_tx_power_params()
2239 &pwr_idx->pwr_idx_2g, in rtw_get_tx_power_params()
2241 *offset = hal->tx_pwr_by_rate_offset_2g[path][rate]; in rtw_get_tx_power_params()
2245 &pwr_idx->pwr_idx_5g, in rtw_get_tx_power_params()
2247 *offset = hal->tx_pwr_by_rate_offset_5g[path][rate]; in rtw_get_tx_power_params()
2252 *remnant = rate <= DESC_RATE11M ? dm_info->txagc_remnant_cck : in rtw_get_tx_power_params()
2253 dm_info->txagc_remnant_ofdm[path]; in rtw_get_tx_power_params()
2254 *sar = rtw_phy_get_tx_power_sar(rtwdev, hal->sar_band, path, rate); in rtw_get_tx_power_params()
2273 if (rtwdev->chip->en_dis_dpd) in rtw_phy_get_tx_power_index()
2278 if (tx_power > rtwdev->chip->max_power_index) in rtw_phy_get_tx_power_index()
2279 tx_power = rtwdev->chip->max_power_index; in rtw_phy_get_tx_power_index()
2288 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_set_tx_power_index_by_rs()
2302 bw = hal->current_band_width; in rtw_phy_set_tx_power_index_by_rs()
2307 hal->tx_pwr_tbl[path][rate] = pwr_idx; in rtw_phy_set_tx_power_index_by_rs()
2313 * power index into a four-byte power index register, and calls set_tx_agc to
2319 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_set_tx_power_level_by_path()
2323 if (hal->current_band_type == RTW_BAND_2G) in rtw_phy_set_tx_power_level_by_path()
2334 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_set_tx_power_level()
2335 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_set_tx_power_level()
2338 mutex_lock(&hal->tx_power_mutex); in rtw_phy_set_tx_power_level()
2340 for (path = 0; path < hal->rf_path_num; path++) in rtw_phy_set_tx_power_level()
2343 chip->ops->set_tx_power_index(rtwdev); in rtw_phy_set_tx_power_level()
2344 mutex_unlock(&hal->tx_power_mutex); in rtw_phy_set_tx_power_level()
2357 base_idx = rates[size - 3]; in rtw_phy_tx_power_by_rate_config_by_path()
2359 base_idx = rates[size - 1]; in rtw_phy_tx_power_by_rate_config_by_path()
2360 base_2g = hal->tx_pwr_by_rate_offset_2g[path][base_idx]; in rtw_phy_tx_power_by_rate_config_by_path()
2361 base_5g = hal->tx_pwr_by_rate_offset_5g[path][base_idx]; in rtw_phy_tx_power_by_rate_config_by_path()
2362 hal->tx_pwr_by_rate_base_2g[path][rs] = base_2g; in rtw_phy_tx_power_by_rate_config_by_path()
2363 hal->tx_pwr_by_rate_base_5g[path][rs] = base_5g; in rtw_phy_tx_power_by_rate_config_by_path()
2366 hal->tx_pwr_by_rate_offset_2g[path][rate_idx] -= base_2g; in rtw_phy_tx_power_by_rate_config_by_path()
2367 hal->tx_pwr_by_rate_offset_5g[path][rate_idx] -= base_5g; in rtw_phy_tx_power_by_rate_config_by_path()
2388 base = hal->tx_pwr_by_rate_base_2g[0][rs]; in __rtw_phy_tx_power_limit_config()
2389 hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base; in __rtw_phy_tx_power_limit_config()
2393 base = hal->tx_pwr_by_rate_base_5g[0][rs]; in __rtw_phy_tx_power_limit_config()
2394 hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base; in __rtw_phy_tx_power_limit_config()
2403 hal->cch_by_bw[RTW_CHANNEL_WIDTH_20] = 1; in rtw_phy_tx_power_limit_config()
2414 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_init_tx_power_limit()
2415 s8 max_power_index = (s8)rtwdev->chip->max_power_index; in rtw_phy_init_tx_power_limit()
2420 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index; in rtw_phy_init_tx_power_limit()
2424 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index; in rtw_phy_init_tx_power_limit()
2429 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_init_tx_power()
2435 hal->tx_pwr_by_rate_offset_2g[path][rate] = 0; in rtw_phy_init_tx_power()
2436 hal->tx_pwr_by_rate_offset_5g[path][rate] = 0; in rtw_phy_init_tx_power()
2452 const struct rtw_pwr_track_tbl *tbl = rfe_def->pwr_track_tbl; in rtw_phy_config_swing_table()
2453 u8 channel = rtwdev->hal.current_channel; in rtw_phy_config_swing_table()
2456 if (rtwdev->dm_info.tx_rate <= DESC_RATE11M) { in rtw_phy_config_swing_table()
2457 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2g_ccka_p; in rtw_phy_config_swing_table()
2458 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2g_ccka_n; in rtw_phy_config_swing_table()
2459 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2g_cckb_p; in rtw_phy_config_swing_table()
2460 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2g_cckb_n; in rtw_phy_config_swing_table()
2461 swing_table->p[RF_PATH_C] = tbl->pwrtrk_2g_cckc_p; in rtw_phy_config_swing_table()
2462 swing_table->n[RF_PATH_C] = tbl->pwrtrk_2g_cckc_n; in rtw_phy_config_swing_table()
2463 swing_table->p[RF_PATH_D] = tbl->pwrtrk_2g_cckd_p; in rtw_phy_config_swing_table()
2464 swing_table->n[RF_PATH_D] = tbl->pwrtrk_2g_cckd_n; in rtw_phy_config_swing_table()
2466 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p; in rtw_phy_config_swing_table()
2467 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n; in rtw_phy_config_swing_table()
2468 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p; in rtw_phy_config_swing_table()
2469 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n; in rtw_phy_config_swing_table()
2470 swing_table->p[RF_PATH_C] = tbl->pwrtrk_2gc_p; in rtw_phy_config_swing_table()
2471 swing_table->n[RF_PATH_C] = tbl->pwrtrk_2gc_n; in rtw_phy_config_swing_table()
2472 swing_table->p[RF_PATH_D] = tbl->pwrtrk_2gd_p; in rtw_phy_config_swing_table()
2473 swing_table->n[RF_PATH_D] = tbl->pwrtrk_2gd_n; in rtw_phy_config_swing_table()
2476 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_1]; in rtw_phy_config_swing_table()
2477 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_1]; in rtw_phy_config_swing_table()
2478 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_1]; in rtw_phy_config_swing_table()
2479 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_1]; in rtw_phy_config_swing_table()
2480 swing_table->p[RF_PATH_C] = tbl->pwrtrk_5gc_p[RTW_PWR_TRK_5G_1]; in rtw_phy_config_swing_table()
2481 swing_table->n[RF_PATH_C] = tbl->pwrtrk_5gc_n[RTW_PWR_TRK_5G_1]; in rtw_phy_config_swing_table()
2482 swing_table->p[RF_PATH_D] = tbl->pwrtrk_5gd_p[RTW_PWR_TRK_5G_1]; in rtw_phy_config_swing_table()
2483 swing_table->n[RF_PATH_D] = tbl->pwrtrk_5gd_n[RTW_PWR_TRK_5G_1]; in rtw_phy_config_swing_table()
2485 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_2]; in rtw_phy_config_swing_table()
2486 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_2]; in rtw_phy_config_swing_table()
2487 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_2]; in rtw_phy_config_swing_table()
2488 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_2]; in rtw_phy_config_swing_table()
2489 swing_table->p[RF_PATH_C] = tbl->pwrtrk_5gc_p[RTW_PWR_TRK_5G_2]; in rtw_phy_config_swing_table()
2490 swing_table->n[RF_PATH_C] = tbl->pwrtrk_5gc_n[RTW_PWR_TRK_5G_2]; in rtw_phy_config_swing_table()
2491 swing_table->p[RF_PATH_D] = tbl->pwrtrk_5gd_p[RTW_PWR_TRK_5G_2]; in rtw_phy_config_swing_table()
2492 swing_table->n[RF_PATH_D] = tbl->pwrtrk_5gd_n[RTW_PWR_TRK_5G_2]; in rtw_phy_config_swing_table()
2494 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_3]; in rtw_phy_config_swing_table()
2495 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_3]; in rtw_phy_config_swing_table()
2496 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_3]; in rtw_phy_config_swing_table()
2497 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_3]; in rtw_phy_config_swing_table()
2498 swing_table->p[RF_PATH_C] = tbl->pwrtrk_5gc_p[RTW_PWR_TRK_5G_3]; in rtw_phy_config_swing_table()
2499 swing_table->n[RF_PATH_C] = tbl->pwrtrk_5gc_n[RTW_PWR_TRK_5G_3]; in rtw_phy_config_swing_table()
2500 swing_table->p[RF_PATH_D] = tbl->pwrtrk_5gd_p[RTW_PWR_TRK_5G_3]; in rtw_phy_config_swing_table()
2501 swing_table->n[RF_PATH_D] = tbl->pwrtrk_5gd_n[RTW_PWR_TRK_5G_3]; in rtw_phy_config_swing_table()
2503 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p; in rtw_phy_config_swing_table()
2504 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n; in rtw_phy_config_swing_table()
2505 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p; in rtw_phy_config_swing_table()
2506 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n; in rtw_phy_config_swing_table()
2507 swing_table->p[RF_PATH_C] = tbl->pwrtrk_2gc_p; in rtw_phy_config_swing_table()
2508 swing_table->n[RF_PATH_C] = tbl->pwrtrk_2gc_n; in rtw_phy_config_swing_table()
2509 swing_table->p[RF_PATH_D] = tbl->pwrtrk_2gd_p; in rtw_phy_config_swing_table()
2510 swing_table->n[RF_PATH_D] = tbl->pwrtrk_2gd_n; in rtw_phy_config_swing_table()
2517 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_pwrtrack_avg()
2519 ewma_thermal_add(&dm_info->avg_thermal[path], thermal); in rtw_phy_pwrtrack_avg()
2520 dm_info->thermal_avg[path] = in rtw_phy_pwrtrack_avg()
2521 ewma_thermal_read(&dm_info->avg_thermal[path]); in rtw_phy_pwrtrack_avg()
2528 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_pwrtrack_thermal_changed()
2529 u8 avg = ewma_thermal_read(&dm_info->avg_thermal[path]); in rtw_phy_pwrtrack_thermal_changed()
2540 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_pwrtrack_get_delta()
2543 therm_avg = dm_info->thermal_avg[path]; in rtw_phy_pwrtrack_get_delta()
2544 therm_efuse = rtwdev->efuse.thermal_meter[path]; in rtw_phy_pwrtrack_get_delta()
2545 therm_delta = abs(therm_avg - therm_efuse); in rtw_phy_pwrtrack_get_delta()
2547 return min_t(u8, therm_delta, RTW_PWR_TRK_TBL_SZ - 1); in rtw_phy_pwrtrack_get_delta()
2555 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_pwrtrack_get_pwridx()
2569 delta_swing_table_idx_pos = swing_table->p[tbl_path]; in rtw_phy_pwrtrack_get_pwridx()
2570 delta_swing_table_idx_neg = swing_table->n[tbl_path]; in rtw_phy_pwrtrack_get_pwridx()
2577 if (dm_info->thermal_avg[therm_path] > in rtw_phy_pwrtrack_get_pwridx()
2578 rtwdev->efuse.thermal_meter[therm_path]) in rtw_phy_pwrtrack_get_pwridx()
2581 return -delta_swing_table_idx_neg[delta]; in rtw_phy_pwrtrack_get_pwridx()
2587 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_pwrtrack_need_lck()
2590 delta_lck = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_lck); in rtw_phy_pwrtrack_need_lck()
2591 if (delta_lck >= rtwdev->chip->lck_threshold) { in rtw_phy_pwrtrack_need_lck()
2592 dm_info->thermal_meter_lck = dm_info->thermal_avg[0]; in rtw_phy_pwrtrack_need_lck()
2601 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_pwrtrack_need_iqk()
2604 delta_iqk = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_k); in rtw_phy_pwrtrack_need_iqk()
2605 if (delta_iqk >= rtwdev->chip->iqk_threshold) { in rtw_phy_pwrtrack_need_iqk()
2606 dm_info->thermal_meter_k = dm_info->thermal_avg[0]; in rtw_phy_pwrtrack_need_iqk()
2616 struct rtw_path_div *path_div = &rtwdev->dm_path_div; in rtw_phy_set_tx_path_by_reg()
2618 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_set_tx_path_by_reg()
2620 if (tx_path_sel_1ss == path_div->current_tx_path) in rtw_phy_set_tx_path_by_reg()
2623 path_div->current_tx_path = tx_path_sel_1ss; in rtw_phy_set_tx_path_by_reg()
2626 chip->ops->config_tx_path(rtwdev, rtwdev->hal.antenna_tx, in rtw_phy_set_tx_path_by_reg()
2632 struct rtw_path_div *path_div = &rtwdev->dm_path_div; in rtw_phy_tx_path_div_select()
2633 enum rtw_bb_path path = path_div->current_tx_path; in rtw_phy_tx_path_div_select()
2636 if (path_div->path_a_cnt) in rtw_phy_tx_path_div_select()
2637 rssi_a = path_div->path_a_sum / path_div->path_a_cnt; in rtw_phy_tx_path_div_select()
2640 if (path_div->path_b_cnt) in rtw_phy_tx_path_div_select()
2641 rssi_b = path_div->path_b_sum / path_div->path_b_cnt; in rtw_phy_tx_path_div_select()
2648 path_div->path_a_cnt = 0; in rtw_phy_tx_path_div_select()
2649 path_div->path_a_sum = 0; in rtw_phy_tx_path_div_select()
2650 path_div->path_b_cnt = 0; in rtw_phy_tx_path_div_select()
2651 path_div->path_b_sum = 0; in rtw_phy_tx_path_div_select()
2657 if (rtwdev->hal.antenna_rx != BB_PATH_AB) { in rtw_phy_tx_path_diversity_2ss()
2660 rtwdev->hal.antenna_tx, rtwdev->hal.antenna_rx); in rtw_phy_tx_path_diversity_2ss()
2663 if (rtwdev->sta_cnt == 0) { in rtw_phy_tx_path_diversity_2ss()
2673 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_tx_path_diversity()
2675 if (!chip->path_div_supported) in rtw_phy_tx_path_diversity()