Lines Matching +full:0 +full:xe10
110 PHY_BAND_2G = 0,
119 for (i = 0; i <= RTW_CHANNEL_WIDTH_40; i++) {
120 for (j = 0; j < RTW_RF_PATH_MAX; j++)
197 path_div->path_a_cnt = 0;
198 path_div->path_a_sum = 0;
199 path_div->path_b_cnt = 0;
200 path_div->path_b_sum = 0;
209 dm_info->fa_history[3] = 0;
210 dm_info->fa_history[2] = 0;
211 dm_info->fa_history[1] = 0;
212 dm_info->fa_history[0] = 0;
213 dm_info->igi_bitmap = 0;
214 dm_info->igi_history[3] = 0;
215 dm_info->igi_history[2] = 0;
216 dm_info->igi_history[1] = 0;
218 addr = chip->dig[0].addr;
219 mask = chip->dig[0].mask;
220 dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask);
238 const struct rtw_hw_reg *dig_cck = &chip->dig_cck[0];
242 for (path = 0; path < hal->rf_path_num; path++) {
262 u8 new_level = 0;
265 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++)
269 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
317 memset(&dm_info->cur_pkt_count, 0, sizeof(dm_info->cur_pkt_count));
330 #define DIG_PERF_MAX 0x5a
331 #define DIG_PERF_MID 0x40
335 #define DIG_CVRG_MAX 0x2a
336 #define DIG_CVRG_MID 0x26
337 #define DIG_CVRG_MIN 0x1c
368 igi_bitmap = dm_info->igi_bitmap & 0xf;
372 if (igi_history[0] > igi_history[1] &&
374 igi_history[0] - igi_history[1] >= 2 &&
376 fa_history[0] > fa_hi && fa_history[1] < fa_lo &&
382 if (igi_history[0] > igi_history[1] &&
384 igi_history[0] - igi_history[1] >= 4 &&
386 fa_history[0] > fa_hi && fa_history[1] < fa_lo &&
396 dm_info->damping_cnt = 0;
436 step[0] = 4;
441 fa_th[0] = DIG_PERF_FA_TH_EXTRA_HIGH;
445 step[0] = 6;
450 fa_th[0] = DIG_CVRG_FA_TH_EXTRA_HIGH;
463 igi_bitmap = dm_info->igi_bitmap << 1 & 0xfe;
467 up = igi > igi_history[0];
472 igi_history[1] = igi_history[0];
473 igi_history[0] = igi;
477 fa_history[1] = fa_history[0];
478 fa_history[0] = fa;
502 pre_igi = dm_info->igi_history[0];
512 for (level = 0; level < 3; level++) {
554 if (rtwdev->watch_dog_cnt & 0x3)
587 if (rate_idx >= DESC_RATEMCS0 || rate_order == 0)
590 return GENMASK(rate_order + RRSR_RATE_ORDER_CCK_LEN - 1, 0);
598 u32 mask = 0;
643 for (i = 0; i < rtwdev->hal.rf_path_num; i++) {
695 #define CCK_PD_IGI_LV4_VAL 0x38
696 #define CCK_PD_IGI_LV3_VAL 0x2a
697 #define CCK_PD_IGI_LV2_VAL 0x24
705 u8 igi = dm_info->igi_history[0];
746 rtw_dbg(rtwdev, RTW_DBG_PHY, "IGI=0x%x, rssi_min=%d, cck_fa=%d\n",
747 dm_info->igi_history[0], dm_info->min_rssi,
748 dm_info->fa_history[0]);
796 return 0;
797 else if (power >= 0)
829 for (i = 0; i < 12; i++) {
830 for (j = 0; j < 8; j++) {
841 if (j == 0 && i == 0)
844 if (j == 0) {
846 if (db_invert_table[i][0] - linear >
852 if (db_invert_table[3][0] - linear >
875 u64 sum = 0;
878 for (path = 0; path < path_num; path++) {
917 addr &= 0xff;
952 addr &= 0xff;
983 u32 old_data = 0;
991 addr &= 0xff;
1006 data_and_addr = ((addr << 20) | (data & 0x000fffff)) & 0x0fffffff;
1029 addr &= 0xff;
1043 if (addr != 0x00)
1059 cond.plat = 0x04;
1077 cond.rfe = 0;
1093 rtw_dbg(rtwdev, RTW_DBG_PHY, "phy cond=0x%08x cond2=0x%08x\n",
1115 if (!(cond.rfe & 0x0f))
1121 if ((cond.rfe & BIT(0)) && cond2.type_glna != drv_cond2.type_glna)
1193 return (hex >> (i * 8)) & 0xFF;
1204 case 0xE00:
1205 case 0x830:
1206 rate[0] = DESC_RATE6M;
1210 for (i = 0; i < 4; ++i)
1214 case 0xE04:
1215 case 0x834:
1216 rate[0] = DESC_RATE24M;
1220 for (i = 0; i < 4; ++i)
1224 case 0xE08:
1225 rate[0] = DESC_RATE1M;
1226 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 1);
1229 case 0x86C:
1230 if (mask == 0xffffff00) {
1231 rate[0] = DESC_RATE2M;
1238 } else if (mask == 0x000000ff) {
1239 rate[0] = DESC_RATE11M;
1240 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 0);
1244 case 0xE10:
1245 case 0x83C:
1246 rate[0] = DESC_RATEMCS0;
1250 for (i = 0; i < 4; ++i)
1254 case 0xE14:
1255 case 0x848:
1256 rate[0] = DESC_RATEMCS4;
1260 for (i = 0; i < 4; ++i)
1264 case 0xE18:
1265 case 0x84C:
1266 rate[0] = DESC_RATEMCS8;
1270 for (i = 0; i < 4; ++i)
1274 case 0xE1C:
1275 case 0x868:
1276 rate[0] = DESC_RATEMCS12;
1280 for (i = 0; i < 4; ++i)
1284 case 0x838:
1285 rate[0] = DESC_RATE1M;
1293 case 0xC20:
1294 case 0xE20:
1295 case 0x1820:
1296 case 0x1A20:
1297 rate[0] = DESC_RATE1M;
1301 for (i = 0; i < 4; ++i)
1305 case 0xC24:
1306 case 0xE24:
1307 case 0x1824:
1308 case 0x1A24:
1309 rate[0] = DESC_RATE6M;
1313 for (i = 0; i < 4; ++i)
1317 case 0xC28:
1318 case 0xE28:
1319 case 0x1828:
1320 case 0x1A28:
1321 rate[0] = DESC_RATE24M;
1325 for (i = 0; i < 4; ++i)
1329 case 0xC2C:
1330 case 0xE2C:
1331 case 0x182C:
1332 case 0x1A2C:
1333 rate[0] = DESC_RATEMCS0;
1337 for (i = 0; i < 4; ++i)
1341 case 0xC30:
1342 case 0xE30:
1343 case 0x1830:
1344 case 0x1A30:
1345 rate[0] = DESC_RATEMCS4;
1349 for (i = 0; i < 4; ++i)
1353 case 0xC34:
1354 case 0xE34:
1355 case 0x1834:
1356 case 0x1A34:
1357 rate[0] = DESC_RATEMCS8;
1361 for (i = 0; i < 4; ++i)
1365 case 0xC38:
1366 case 0xE38:
1367 case 0x1838:
1368 case 0x1A38:
1369 rate[0] = DESC_RATEMCS12;
1373 for (i = 0; i < 4; ++i)
1377 case 0xC3C:
1378 case 0xE3C:
1379 case 0x183C:
1380 case 0x1A3C:
1381 rate[0] = DESC_RATEVHT1SS_MCS0;
1385 for (i = 0; i < 4; ++i)
1389 case 0xC40:
1390 case 0xE40:
1391 case 0x1840:
1392 case 0x1A40:
1393 rate[0] = DESC_RATEVHT1SS_MCS4;
1397 for (i = 0; i < 4; ++i)
1401 case 0xC44:
1402 case 0xE44:
1403 case 0x1844:
1404 case 0x1A44:
1405 rate[0] = DESC_RATEVHT1SS_MCS8;
1409 for (i = 0; i < 4; ++i)
1413 case 0xC48:
1414 case 0xE48:
1415 case 0x1848:
1416 case 0x1A48:
1417 rate[0] = DESC_RATEVHT2SS_MCS2;
1421 for (i = 0; i < 4; ++i)
1425 case 0xC4C:
1426 case 0xE4C:
1427 case 0x184C:
1428 case 0x1A4C:
1429 rate[0] = DESC_RATEVHT2SS_MCS6;
1433 for (i = 0; i < 4; ++i)
1437 case 0xCD8:
1438 case 0xED8:
1439 case 0x18D8:
1440 case 0x1AD8:
1441 rate[0] = DESC_RATEMCS16;
1445 for (i = 0; i < 4; ++i)
1449 case 0xCDC:
1450 case 0xEDC:
1451 case 0x18DC:
1452 case 0x1ADC:
1453 rate[0] = DESC_RATEMCS20;
1457 for (i = 0; i < 4; ++i)
1461 case 0xCE0:
1462 case 0xEE0:
1463 case 0x18E0:
1464 case 0x1AE0:
1465 rate[0] = DESC_RATEVHT3SS_MCS0;
1469 for (i = 0; i < 4; ++i)
1473 case 0xCE4:
1474 case 0xEE4:
1475 case 0x18E4:
1476 case 0x1AE4:
1477 rate[0] = DESC_RATEVHT3SS_MCS4;
1481 for (i = 0; i < 4; ++i)
1485 case 0xCE8:
1486 case 0xEE8:
1487 case 0x18E8:
1488 case 0x1AE8:
1489 rate[0] = DESC_RATEVHT3SS_MCS8;
1491 for (i = 0; i < 2; ++i)
1496 rtw_warn(rtwdev, "invalid tx power index addr 0x%08x\n", addr);
1506 u8 rate_num = 0;
1508 u8 rates[RTW_RF_PATH_MAX] = {0};
1510 s8 pwr_by_rate[RTW_RF_PATH_MAX] = {0};
1521 for (i = 0; i < rate_num; i++) {
1537 if (p->addr == 0xfe || p->addr == 0xffe) {
1567 for (ch_idx = 0; ch_idx < n_channel; ch_idx++)
1593 rs >= RTW_RATE_SECTION_MAX || ch_idx < 0) {
1641 for (rs_idx = 0; rs_idx < 2; rs_idx++) {
1642 rs_ht = rs_cmp[rs_idx][0];
1655 for (ch_idx = 0; ch_idx < RTW_MAX_CHANNEL_NUM_5G; ch_idx++)
1674 for (regd = 0; regd < RTW_REGD_MAX; regd++)
1683 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++)
1687 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++)
1697 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
1698 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
1708 u32 regd_cfg_flag = 0;
1718 for (i = 0; i < RTW_REGD_MAX; i++) {
1763 if (addr == 0xfe)
1765 else if (addr == 0xfd)
1767 else if (addr == 0xfc)
1769 else if (addr == 0xfb)
1771 else if (addr == 0xfa)
1773 else if (addr == 0xf9)
1783 if (addr == 0xffe) {
1785 } else if (addr == 0xfe) {
1802 rtw_write32_mask(rtwdev, 0x1e24, BIT(17), 0x1);
1803 rtw_write32_mask(rtwdev, 0x1cd0, BIT(28), 0x1);
1804 rtw_write32_mask(rtwdev, 0x1cd0, BIT(29), 0x1);
1805 rtw_write32_mask(rtwdev, 0x1cd0, BIT(30), 0x1);
1806 rtw_write32_mask(rtwdev, 0x1cd0, BIT(31), 0x0);
1826 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) {
1847 return 0;
1928 s8 dpd_diff = 0;
1931 return 0;
2107 if (ch_idx < 0)
2188 struct rtw_power_params pwr_param = {0};
2230 for (i = 0; i < size; i++) {
2267 for (path = 0; path < hal->rf_path_num; path++)
2291 for (rate = 0; rate < size; rate++) {
2302 for (path = 0; path < RTW_RF_PATH_MAX; path++) {
2330 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++) {
2331 base = hal->tx_pwr_by_rate_base_2g[0][rs];
2335 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++) {
2336 base = hal->tx_pwr_by_rate_base_5g[0][rs];
2348 for (regd = 0; regd < RTW_REGD_MAX; regd++)
2349 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
2350 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
2362 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++)
2366 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++)
2376 for (path = 0; path < RTW_RF_PATH_MAX; path++) {
2377 for (rate = 0; rate < DESC_RATE_MAX; rate++) {
2378 hal->tx_pwr_by_rate_offset_2g[path][rate] = 0;
2379 hal->tx_pwr_by_rate_offset_5g[path][rate] = 0;
2384 for (regd = 0; regd < RTW_REGD_MAX; regd++)
2385 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
2386 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
2480 return 0;
2485 return 0;
2493 return 0;
2509 delta_lck = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_lck);
2511 dm_info->thermal_meter_lck = dm_info->thermal_avg[0];
2523 delta_iqk = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_k);
2525 dm_info->thermal_meter_k = dm_info->thermal_avg[0];
2553 s32 rssi_a = 0, rssi_b = 0;
2558 rssi_a = 0;
2562 rssi_b = 0;
2567 path_div->path_a_cnt = 0;
2568 path_div->path_a_sum = 0;
2569 path_div->path_b_cnt = 0;
2570 path_div->path_b_sum = 0;
2582 if (rtwdev->sta_cnt == 0) {