Lines Matching +full:0 +full:xc40
107 PHY_BAND_2G = 0,
116 for (i = 0; i <= RTW_CHANNEL_WIDTH_40; i++) {
117 for (j = 0; j < RTW_RF_PATH_MAX; j++)
194 path_div->path_a_cnt = 0;
195 path_div->path_a_sum = 0;
196 path_div->path_b_cnt = 0;
197 path_div->path_b_sum = 0;
206 dm_info->fa_history[3] = 0;
207 dm_info->fa_history[2] = 0;
208 dm_info->fa_history[1] = 0;
209 dm_info->fa_history[0] = 0;
210 dm_info->igi_bitmap = 0;
211 dm_info->igi_history[3] = 0;
212 dm_info->igi_history[2] = 0;
213 dm_info->igi_history[1] = 0;
215 addr = chip->dig[0].addr;
216 mask = chip->dig[0].mask;
217 dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask);
235 const struct rtw_hw_reg *dig_cck = &chip->dig_cck[0];
239 for (path = 0; path < hal->rf_path_num; path++) {
259 u8 new_level = 0;
262 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++)
266 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
314 memset(&dm_info->cur_pkt_count, 0, sizeof(dm_info->cur_pkt_count));
327 #define DIG_PERF_MAX 0x5a
328 #define DIG_PERF_MID 0x40
332 #define DIG_CVRG_MAX 0x2a
333 #define DIG_CVRG_MID 0x26
334 #define DIG_CVRG_MIN 0x1c
365 igi_bitmap = dm_info->igi_bitmap & 0xf;
369 if (igi_history[0] > igi_history[1] &&
371 igi_history[0] - igi_history[1] >= 2 &&
373 fa_history[0] > fa_hi && fa_history[1] < fa_lo &&
379 if (igi_history[0] > igi_history[1] &&
381 igi_history[0] - igi_history[1] >= 4 &&
383 fa_history[0] > fa_hi && fa_history[1] < fa_lo &&
393 dm_info->damping_cnt = 0;
433 step[0] = 4;
438 fa_th[0] = DIG_PERF_FA_TH_EXTRA_HIGH;
442 step[0] = 6;
447 fa_th[0] = DIG_CVRG_FA_TH_EXTRA_HIGH;
460 igi_bitmap = dm_info->igi_bitmap << 1 & 0xfe;
464 up = igi > igi_history[0];
469 igi_history[1] = igi_history[0];
470 igi_history[0] = igi;
474 fa_history[1] = fa_history[0];
475 fa_history[0] = fa;
499 pre_igi = dm_info->igi_history[0];
509 for (level = 0; level < 3; level++) {
544 if (rtwdev->watch_dog_cnt & 0x3)
577 if (rate_idx >= DESC_RATEMCS0 || rate_order == 0)
580 return GENMASK(rate_order + RRSR_RATE_ORDER_CCK_LEN - 1, 0);
588 u32 mask = 0;
633 for (i = 0; i < rtwdev->hal.rf_path_num; i++) {
685 #define CCK_PD_IGI_LV4_VAL 0x38
686 #define CCK_PD_IGI_LV3_VAL 0x2a
687 #define CCK_PD_IGI_LV2_VAL 0x24
695 u8 igi = dm_info->igi_history[0];
736 rtw_dbg(rtwdev, RTW_DBG_PHY, "IGI=0x%x, rssi_min=%d, cck_fa=%d\n",
737 dm_info->igi_history[0], dm_info->min_rssi,
738 dm_info->fa_history[0]);
786 return 0;
787 else if (power >= 0)
819 for (i = 0; i < 12; i++) {
820 for (j = 0; j < 8; j++) {
831 if (j == 0 && i == 0)
834 if (j == 0) {
836 if (db_invert_table[i][0] - linear >
842 if (db_invert_table[3][0] - linear >
865 u64 sum = 0;
868 for (path = 0; path < path_num; path++) {
907 addr &= 0xff;
942 addr &= 0xff;
973 u32 old_data = 0;
981 addr &= 0xff;
996 data_and_addr = ((addr << 20) | (data & 0x000fffff)) & 0x0fffffff;
1019 addr &= 0xff;
1033 if (addr != 0x00)
1044 struct rtw_phy_cond cond = {0};
1048 cond.plat = 0x04;
1066 rtw_dbg(rtwdev, RTW_DBG_PHY, "phy cond=0x%08x\n", *((u32 *)&hal->phy_cond));
1093 struct rtw_phy_cond pos_cond = {0};
1140 return (hex >> (i * 8)) & 0xFF;
1151 case 0xE00:
1152 case 0x830:
1153 rate[0] = DESC_RATE6M;
1157 for (i = 0; i < 4; ++i)
1161 case 0xE04:
1162 case 0x834:
1163 rate[0] = DESC_RATE24M;
1167 for (i = 0; i < 4; ++i)
1171 case 0xE08:
1172 rate[0] = DESC_RATE1M;
1173 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 1);
1176 case 0x86C:
1177 if (mask == 0xffffff00) {
1178 rate[0] = DESC_RATE2M;
1185 } else if (mask == 0x000000ff) {
1186 rate[0] = DESC_RATE11M;
1187 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 0);
1191 case 0xE10:
1192 case 0x83C:
1193 rate[0] = DESC_RATEMCS0;
1197 for (i = 0; i < 4; ++i)
1201 case 0xE14:
1202 case 0x848:
1203 rate[0] = DESC_RATEMCS4;
1207 for (i = 0; i < 4; ++i)
1211 case 0xE18:
1212 case 0x84C:
1213 rate[0] = DESC_RATEMCS8;
1217 for (i = 0; i < 4; ++i)
1221 case 0xE1C:
1222 case 0x868:
1223 rate[0] = DESC_RATEMCS12;
1227 for (i = 0; i < 4; ++i)
1231 case 0x838:
1232 rate[0] = DESC_RATE1M;
1240 case 0xC20:
1241 case 0xE20:
1242 case 0x1820:
1243 case 0x1A20:
1244 rate[0] = DESC_RATE1M;
1248 for (i = 0; i < 4; ++i)
1252 case 0xC24:
1253 case 0xE24:
1254 case 0x1824:
1255 case 0x1A24:
1256 rate[0] = DESC_RATE6M;
1260 for (i = 0; i < 4; ++i)
1264 case 0xC28:
1265 case 0xE28:
1266 case 0x1828:
1267 case 0x1A28:
1268 rate[0] = DESC_RATE24M;
1272 for (i = 0; i < 4; ++i)
1276 case 0xC2C:
1277 case 0xE2C:
1278 case 0x182C:
1279 case 0x1A2C:
1280 rate[0] = DESC_RATEMCS0;
1284 for (i = 0; i < 4; ++i)
1288 case 0xC30:
1289 case 0xE30:
1290 case 0x1830:
1291 case 0x1A30:
1292 rate[0] = DESC_RATEMCS4;
1296 for (i = 0; i < 4; ++i)
1300 case 0xC34:
1301 case 0xE34:
1302 case 0x1834:
1303 case 0x1A34:
1304 rate[0] = DESC_RATEMCS8;
1308 for (i = 0; i < 4; ++i)
1312 case 0xC38:
1313 case 0xE38:
1314 case 0x1838:
1315 case 0x1A38:
1316 rate[0] = DESC_RATEMCS12;
1320 for (i = 0; i < 4; ++i)
1324 case 0xC3C:
1325 case 0xE3C:
1326 case 0x183C:
1327 case 0x1A3C:
1328 rate[0] = DESC_RATEVHT1SS_MCS0;
1332 for (i = 0; i < 4; ++i)
1336 case 0xC40:
1337 case 0xE40:
1338 case 0x1840:
1339 case 0x1A40:
1340 rate[0] = DESC_RATEVHT1SS_MCS4;
1344 for (i = 0; i < 4; ++i)
1348 case 0xC44:
1349 case 0xE44:
1350 case 0x1844:
1351 case 0x1A44:
1352 rate[0] = DESC_RATEVHT1SS_MCS8;
1356 for (i = 0; i < 4; ++i)
1360 case 0xC48:
1361 case 0xE48:
1362 case 0x1848:
1363 case 0x1A48:
1364 rate[0] = DESC_RATEVHT2SS_MCS2;
1368 for (i = 0; i < 4; ++i)
1372 case 0xC4C:
1373 case 0xE4C:
1374 case 0x184C:
1375 case 0x1A4C:
1376 rate[0] = DESC_RATEVHT2SS_MCS6;
1380 for (i = 0; i < 4; ++i)
1384 case 0xCD8:
1385 case 0xED8:
1386 case 0x18D8:
1387 case 0x1AD8:
1388 rate[0] = DESC_RATEMCS16;
1392 for (i = 0; i < 4; ++i)
1396 case 0xCDC:
1397 case 0xEDC:
1398 case 0x18DC:
1399 case 0x1ADC:
1400 rate[0] = DESC_RATEMCS20;
1404 for (i = 0; i < 4; ++i)
1408 case 0xCE0:
1409 case 0xEE0:
1410 case 0x18E0:
1411 case 0x1AE0:
1412 rate[0] = DESC_RATEVHT3SS_MCS0;
1416 for (i = 0; i < 4; ++i)
1420 case 0xCE4:
1421 case 0xEE4:
1422 case 0x18E4:
1423 case 0x1AE4:
1424 rate[0] = DESC_RATEVHT3SS_MCS4;
1428 for (i = 0; i < 4; ++i)
1432 case 0xCE8:
1433 case 0xEE8:
1434 case 0x18E8:
1435 case 0x1AE8:
1436 rate[0] = DESC_RATEVHT3SS_MCS8;
1438 for (i = 0; i < 2; ++i)
1443 rtw_warn(rtwdev, "invalid tx power index addr 0x%08x\n", addr);
1453 u8 rate_num = 0;
1455 u8 rates[RTW_RF_PATH_MAX] = {0};
1457 s8 pwr_by_rate[RTW_RF_PATH_MAX] = {0};
1468 for (i = 0; i < rate_num; i++) {
1486 if (p->addr == 0xfe || p->addr == 0xffe) {
1516 for (ch_idx = 0; ch_idx < n_channel; ch_idx++)
1542 rs >= RTW_RATE_SECTION_MAX || ch_idx < 0) {
1590 for (rs_idx = 0; rs_idx < 2; rs_idx++) {
1591 rs_ht = rs_cmp[rs_idx][0];
1604 for (ch_idx = 0; ch_idx < RTW_MAX_CHANNEL_NUM_5G; ch_idx++)
1623 for (regd = 0; regd < RTW_REGD_MAX; regd++)
1632 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++)
1636 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++)
1646 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
1647 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
1657 u32 regd_cfg_flag = 0;
1667 for (i = 0; i < RTW_REGD_MAX; i++) {
1712 if (addr == 0xfe)
1714 else if (addr == 0xfd)
1716 else if (addr == 0xfc)
1718 else if (addr == 0xfb)
1720 else if (addr == 0xfa)
1722 else if (addr == 0xf9)
1732 if (addr == 0xffe) {
1734 } else if (addr == 0xfe) {
1751 rtw_write32_mask(rtwdev, 0x1e24, BIT(17), 0x1);
1752 rtw_write32_mask(rtwdev, 0x1cd0, BIT(28), 0x1);
1753 rtw_write32_mask(rtwdev, 0x1cd0, BIT(29), 0x1);
1754 rtw_write32_mask(rtwdev, 0x1cd0, BIT(30), 0x1);
1755 rtw_write32_mask(rtwdev, 0x1cd0, BIT(31), 0x0);
1775 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) {
1796 return 0;
1877 s8 dpd_diff = 0;
1880 return 0;
2056 if (ch_idx < 0)
2137 struct rtw_power_params pwr_param = {0};
2179 for (i = 0; i < size; i++) {
2216 for (path = 0; path < hal->rf_path_num; path++)
2240 for (rate = 0; rate < size; rate++) {
2251 for (path = 0; path < RTW_RF_PATH_MAX; path++) {
2279 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++) {
2280 base = hal->tx_pwr_by_rate_base_2g[0][rs];
2284 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++) {
2285 base = hal->tx_pwr_by_rate_base_5g[0][rs];
2297 for (regd = 0; regd < RTW_REGD_MAX; regd++)
2298 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
2299 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
2311 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++)
2315 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++)
2325 for (path = 0; path < RTW_RF_PATH_MAX; path++) {
2326 for (rate = 0; rate < DESC_RATE_MAX; rate++) {
2327 hal->tx_pwr_by_rate_offset_2g[path][rate] = 0;
2328 hal->tx_pwr_by_rate_offset_5g[path][rate] = 0;
2333 for (regd = 0; regd < RTW_REGD_MAX; regd++)
2334 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
2335 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
2428 return 0;
2433 return 0;
2441 return 0;
2457 delta_lck = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_lck);
2459 dm_info->thermal_meter_lck = dm_info->thermal_avg[0];
2471 delta_iqk = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_k);
2473 dm_info->thermal_meter_k = dm_info->thermal_avg[0];
2501 s32 rssi_a = 0, rssi_b = 0;
2506 rssi_a = 0;
2510 rssi_b = 0;
2515 path_div->path_a_cnt = 0;
2516 path_div->path_a_sum = 0;
2517 path_div->path_b_cnt = 0;
2518 path_div->path_b_sum = 0;
2530 if (rtwdev->sta_cnt == 0) {