Lines Matching defs:hal
230 struct rtw_hal *hal = &rtwdev->hal;
239 for (path = 0; path < hal->rf_path_num; path++) {
633 for (i = 0; i < rtwdev->hal.rf_path_num; i++) {
728 if (rtwdev->hal.current_band_type != RTW_BAND_2G)
897 struct rtw_hal *hal = &rtwdev->hal;
902 if (rf_path >= hal->rf_phy_num) {
920 struct rtw_hal *hal = &rtwdev->hal;
929 if (rf_path >= hal->rf_phy_num) {
969 struct rtw_hal *hal = &rtwdev->hal;
976 if (rf_path >= hal->rf_phy_num) {
1009 struct rtw_hal *hal = &rtwdev->hal;
1014 if (rf_path >= hal->rf_phy_num) {
1042 struct rtw_hal *hal = &rtwdev->hal;
1046 cond.cut = hal->cut_version ? hal->cut_version : 15;
1064 hal->phy_cond = cond;
1066 rtw_dbg(rtwdev, RTW_DBG_PHY, "phy cond=0x%08x\n", *((u32 *)&hal->phy_cond));
1071 struct rtw_hal *hal = &rtwdev->hal;
1072 struct rtw_phy_cond drv_cond = hal->phy_cond;
1452 struct rtw_hal *hal = &rtwdev->hal;
1472 hal->tx_pwr_by_rate_offset_2g[rfpath][rate] = offset;
1474 hal->tx_pwr_by_rate_offset_5g[rfpath][rate] = offset;
1532 struct rtw_hal *hal = &rtwdev->hal;
1550 hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit;
1551 ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx];
1553 hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1555 hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit;
1556 ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx];
1558 hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1567 struct rtw_hal *hal = &rtwdev->hal;
1569 s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx];
1570 s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx];
1576 hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht;
1579 hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht;
1628 __cfg_txpwr_lmt_by_alt(struct rtw_hal *hal, u8 regd, u8 regd_alt, u8 bw, u8 rs)
1633 hal->tx_pwr_limit_2g[regd][bw][rs][ch] =
1634 hal->tx_pwr_limit_2g[regd_alt][bw][rs][ch];
1637 hal->tx_pwr_limit_5g[regd][bw][rs][ch] =
1638 hal->tx_pwr_limit_5g[regd_alt][bw][rs][ch];
1648 __cfg_txpwr_lmt_by_alt(&rtwdev->hal, regd, regd_alt,
1775 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) {
2029 struct rtw_hal *hal = &rtwdev->hal;
2030 u8 *cch_by_bw = hal->cch_by_bw;
2060 hal->tx_pwr_limit_2g[regd][cur_bw][rs][ch_idx] :
2061 hal->tx_pwr_limit_5g[regd][cur_bw][rs][ch_idx];
2098 struct rtw_hal *hal = &rtwdev->hal;
2117 *offset = hal->tx_pwr_by_rate_offset_2g[path][rate];
2123 *offset = hal->tx_pwr_by_rate_offset_5g[path][rate];
2130 *sar = rtw_phy_get_tx_power_sar(rtwdev, hal->sar_band, path, rate);
2164 struct rtw_hal *hal = &rtwdev->hal;
2178 bw = hal->current_band_width;
2183 hal->tx_pwr_tbl[path][rate] = pwr_idx;
2195 struct rtw_hal *hal = &rtwdev->hal;
2199 if (hal->current_band_type == RTW_BAND_2G)
2211 struct rtw_hal *hal = &rtwdev->hal;
2214 mutex_lock(&hal->tx_power_mutex);
2216 for (path = 0; path < hal->rf_path_num; path++)
2220 mutex_unlock(&hal->tx_power_mutex);
2225 rtw_phy_tx_power_by_rate_config_by_path(struct rtw_hal *hal, u8 path,
2236 base_2g = hal->tx_pwr_by_rate_offset_2g[path][base_idx];
2237 base_5g = hal->tx_pwr_by_rate_offset_5g[path][base_idx];
2238 hal->tx_pwr_by_rate_base_2g[path][rs] = base_2g;
2239 hal->tx_pwr_by_rate_base_5g[path][rs] = base_5g;
2242 hal->tx_pwr_by_rate_offset_2g[path][rate_idx] -= base_2g;
2243 hal->tx_pwr_by_rate_offset_5g[path][rate_idx] -= base_5g;
2247 void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal)
2252 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2255 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2258 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2261 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2264 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2267 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2274 __rtw_phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs)
2280 base = hal->tx_pwr_by_rate_base_2g[0][rs];
2281 hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base;
2285 base = hal->tx_pwr_by_rate_base_5g[0][rs];
2286 hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base;
2290 void rtw_phy_tx_power_limit_config(struct rtw_hal *hal)
2295 hal->cch_by_bw[RTW_CHANNEL_WIDTH_20] = 1;
2300 __rtw_phy_tx_power_limit_config(hal, regd, bw, rs);
2306 struct rtw_hal *hal = &rtwdev->hal;
2312 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index;
2316 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index;
2321 struct rtw_hal *hal = &rtwdev->hal;
2327 hal->tx_pwr_by_rate_offset_2g[path][rate] = 0;
2328 hal->tx_pwr_by_rate_offset_5g[path][rate] = 0;
2344 u8 channel = rtwdev->hal.current_channel;
2493 chip->ops->config_tx_path(rtwdev, rtwdev->hal.antenna_tx,
2524 if (rtwdev->hal.antenna_rx != BB_PATH_AB) {
2527 rtwdev->hal.antenna_tx, rtwdev->hal.antenna_rx);