Lines Matching defs:rtwdev
58 static u8 rtw_pci_read8(struct rtw_dev *rtwdev, u32 addr)
60 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
68 rtw_dbg(rtwdev, RTW_DBG_IO_RW, "R08 (%#010x) -> %#04x\n", addr, val);
73 static u16 rtw_pci_read16(struct rtw_dev *rtwdev, u32 addr)
75 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
83 rtw_dbg(rtwdev, RTW_DBG_IO_RW, "R16 (%#010x) -> %#06x\n", addr, val);
88 static u32 rtw_pci_read32(struct rtw_dev *rtwdev, u32 addr)
90 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
98 rtw_dbg(rtwdev, RTW_DBG_IO_RW, "R32 (%#010x) -> %#010x\n", addr, val);
103 static void rtw_pci_write8(struct rtw_dev *rtwdev, u32 addr, u8 val)
105 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
110 rtw_dbg(rtwdev, RTW_DBG_IO_RW, "W08 (%#010x) <- %#04x\n", addr, val);
115 static void rtw_pci_write16(struct rtw_dev *rtwdev, u32 addr, u16 val)
117 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
122 rtw_dbg(rtwdev, RTW_DBG_IO_RW, "W16 (%#010x) <- %#06x\n", addr, val);
127 static void rtw_pci_write32(struct rtw_dev *rtwdev, u32 addr, u32 val)
129 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
134 rtw_dbg(rtwdev, RTW_DBG_IO_RW, "W32 (%#010x) <- %#010x\n", addr, val);
139 static void rtw_pci_free_tx_ring_skbs(struct rtw_dev *rtwdev,
142 struct pci_dev *pdev = to_pci_dev(rtwdev->dev);
158 static void rtw_pci_free_tx_ring(struct rtw_dev *rtwdev,
161 struct pci_dev *pdev = to_pci_dev(rtwdev->dev);
166 rtw_pci_free_tx_ring_skbs(rtwdev, tx_ring);
173 static void rtw_pci_free_rx_ring_skbs(struct rtw_dev *rtwdev,
176 struct pci_dev *pdev = to_pci_dev(rtwdev->dev);
194 static void rtw_pci_free_rx_ring(struct rtw_dev *rtwdev,
197 struct pci_dev *pdev = to_pci_dev(rtwdev->dev);
201 rtw_pci_free_rx_ring_skbs(rtwdev, rx_ring);
206 static void rtw_pci_free_trx_ring(struct rtw_dev *rtwdev)
208 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
215 rtw_pci_free_tx_ring(rtwdev, tx_ring);
220 rtw_pci_free_rx_ring(rtwdev, rx_ring);
224 static int rtw_pci_init_tx_ring(struct rtw_dev *rtwdev,
228 struct pci_dev *pdev = to_pci_dev(rtwdev->dev);
234 rtw_err(rtwdev, "len %d exceeds maximum TX entries\n", len);
240 rtw_err(rtwdev, "failed to allocate tx ring\n");
255 static int rtw_pci_reset_rx_desc(struct rtw_dev *rtwdev, struct sk_buff *skb,
259 struct pci_dev *pdev = to_pci_dev(rtwdev->dev);
281 static void rtw_pci_sync_rx_desc_device(struct rtw_dev *rtwdev, dma_addr_t dma,
285 struct device *dev = rtwdev->dev;
298 static int rtw_pci_init_rx_ring(struct rtw_dev *rtwdev,
302 struct pci_dev *pdev = to_pci_dev(rtwdev->dev);
313 rtw_err(rtwdev, "failed to allocate rx ring\n");
328 ret = rtw_pci_reset_rx_desc(rtwdev, skb, rx_ring, i, desc_size);
356 rtw_err(rtwdev, "failed to init rx buffer\n");
361 static int rtw_pci_init_trx_ring(struct rtw_dev *rtwdev)
363 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
366 const struct rtw_chip_info *chip = rtwdev->chip;
377 ret = rtw_pci_init_tx_ring(rtwdev, tx_ring, tx_desc_size, len);
386 ret = rtw_pci_init_rx_ring(rtwdev, rx_ring, rx_desc_size,
398 rtw_pci_free_tx_ring(rtwdev, tx_ring);
404 rtw_pci_free_rx_ring(rtwdev, rx_ring);
410 static void rtw_pci_deinit(struct rtw_dev *rtwdev)
412 rtw_pci_free_trx_ring(rtwdev);
415 static int rtw_pci_init(struct rtw_dev *rtwdev)
417 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
436 ret = rtw_pci_init_trx_ring(rtwdev);
441 static void rtw_pci_reset_buf_desc(struct rtw_dev *rtwdev)
443 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
448 tmp = rtw_read8(rtwdev, RTK_PCI_CTRL + 3);
449 rtw_write8(rtwdev, RTK_PCI_CTRL + 3, tmp | 0xf7);
452 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BCNQ, dma);
454 if (!rtw_chip_wcpu_11n(rtwdev)) {
459 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_H2CQ, len & TRX_BD_IDX_MASK);
460 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_H2CQ, dma);
467 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_BKQ, len & TRX_BD_IDX_MASK);
468 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BKQ, dma);
474 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_BEQ, len & TRX_BD_IDX_MASK);
475 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BEQ, dma);
481 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_VOQ, len & TRX_BD_IDX_MASK);
482 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_VOQ, dma);
488 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_VIQ, len & TRX_BD_IDX_MASK);
489 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_VIQ, dma);
495 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_MGMTQ, len & TRX_BD_IDX_MASK);
496 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_MGMTQ, dma);
502 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_HI0Q, len & TRX_BD_IDX_MASK);
503 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_HI0Q, dma);
509 rtw_write16(rtwdev, RTK_PCI_RXBD_NUM_MPDUQ, len & TRX_BD_IDX_MASK);
510 rtw_write32(rtwdev, RTK_PCI_RXBD_DESA_MPDUQ, dma);
513 rtw_write32(rtwdev, RTK_PCI_TXBD_RWPTR_CLR, 0xffffffff);
516 if (rtw_chip_wcpu_11ac(rtwdev))
517 rtw_write32_set(rtwdev, RTK_PCI_TXBD_H2CQ_CSR,
521 static void rtw_pci_reset_trx_ring(struct rtw_dev *rtwdev)
523 rtw_pci_reset_buf_desc(rtwdev);
526 static void rtw_pci_enable_interrupt(struct rtw_dev *rtwdev,
534 rtw_write32(rtwdev, RTK_PCI_HIMR0, rtwpci->irq_mask[0] & ~imr0_unmask);
535 rtw_write32(rtwdev, RTK_PCI_HIMR1, rtwpci->irq_mask[1]);
536 if (rtw_chip_wcpu_11ac(rtwdev))
537 rtw_write32(rtwdev, RTK_PCI_HIMR3, rtwpci->irq_mask[3]);
544 static void rtw_pci_disable_interrupt(struct rtw_dev *rtwdev,
554 rtw_write32(rtwdev, RTK_PCI_HIMR0, 0);
555 rtw_write32(rtwdev, RTK_PCI_HIMR1, 0);
556 if (rtw_chip_wcpu_11ac(rtwdev))
557 rtw_write32(rtwdev, RTK_PCI_HIMR3, 0);
565 static void rtw_pci_dma_reset(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci)
568 rtw_write32_set(rtwdev, RTK_PCI_CTRL,
573 static int rtw_pci_setup(struct rtw_dev *rtwdev)
575 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
577 rtw_pci_reset_trx_ring(rtwdev);
578 rtw_pci_dma_reset(rtwdev, rtwpci);
583 static void rtw_pci_dma_release(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci)
588 rtw_pci_reset_trx_ring(rtwdev);
591 rtw_pci_free_tx_ring_skbs(rtwdev, tx_ring);
595 static void rtw_pci_napi_start(struct rtw_dev *rtwdev)
597 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
605 static void rtw_pci_napi_stop(struct rtw_dev *rtwdev)
607 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
616 static int rtw_pci_start(struct rtw_dev *rtwdev)
618 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
620 rtw_pci_napi_start(rtwdev);
624 rtw_pci_enable_interrupt(rtwdev, rtwpci, false);
630 static void rtw_pci_stop(struct rtw_dev *rtwdev)
632 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
637 rtw_pci_disable_interrupt(rtwdev, rtwpci);
641 rtw_pci_napi_stop(rtwdev);
644 rtw_pci_dma_release(rtwdev, rtwpci);
648 static void rtw_pci_deep_ps_enter(struct rtw_dev *rtwdev)
650 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
655 if (rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_TX_WAKE))
679 rtw_dbg(rtwdev, RTW_DBG_PS,
684 set_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags);
685 rtw_power_mode_change(rtwdev, true);
688 static void rtw_pci_deep_ps_leave(struct rtw_dev *rtwdev)
691 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
695 lockdep_assert_held(&((struct rtw_pci *)rtwdev->priv)->irq_lock);
698 if (test_and_clear_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags))
699 rtw_power_mode_change(rtwdev, false);
702 static void rtw_pci_deep_ps(struct rtw_dev *rtwdev, bool enter)
704 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
708 if (enter && !test_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags))
709 rtw_pci_deep_ps_enter(rtwdev);
711 if (!enter && test_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags))
712 rtw_pci_deep_ps_leave(rtwdev);
733 static void rtw_pci_dma_check(struct rtw_dev *rtwdev,
737 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
738 const struct rtw_chip_info *chip = rtwdev->chip;
749 rtw_warn(rtwdev, "pci bus timeout, check dma status\n");
754 static u32 __pci_get_hw_tx_ring_rp(struct rtw_dev *rtwdev, u8 pci_q)
757 u32 bd_idx = rtw_read16(rtwdev, bd_idx_addr + 2);
762 static void __pci_flush_queue(struct rtw_dev *rtwdev, u8 pci_q, bool drop)
764 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
775 cur_rp = __pci_get_hw_tx_ring_rp(rtwdev, pci_q);
783 rtw_dbg(rtwdev, RTW_DBG_UNEXP,
787 static void __rtw_pci_flush_queues(struct rtw_dev *rtwdev, u32 pci_queues,
799 __pci_flush_queue(rtwdev, q, drop);
803 static void rtw_pci_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop)
811 if (queues == BIT(rtwdev->hw->queues) - 1) {
814 for (i = 0; i < rtwdev->hw->queues; i++)
819 __rtw_pci_flush_queues(rtwdev, pci_queues, drop);
822 static void rtw_pci_tx_kick_off_queue(struct rtw_dev *rtwdev,
825 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
833 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_TX_WAKE))
834 rtw_pci_deep_ps_leave(rtwdev);
835 rtw_write16(rtwdev, bd_idx, ring->r.wp & TRX_BD_IDX_MASK);
839 static void rtw_pci_tx_kick_off(struct rtw_dev *rtwdev)
841 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
846 rtw_pci_tx_kick_off_queue(rtwdev, queue);
849 static int rtw_pci_tx_write_data(struct rtw_dev *rtwdev,
854 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
855 const struct rtw_chip_info *chip = rtwdev->chip;
919 static int rtw_pci_write_data_rsvd_page(struct rtw_dev *rtwdev, u8 *buf,
927 skb = rtw_tx_write_data_rsvd_page_get(rtwdev, &pkt_info, buf, size);
931 ret = rtw_pci_tx_write_data(rtwdev, &pkt_info, skb, RTW_TX_QUEUE_BCN);
936 rtw_err(rtwdev, "failed to write rsvd page data\n");
941 reg_bcn_work = rtw_read8(rtwdev, RTK_PCI_TXBD_BCN_WORK);
943 rtw_write8(rtwdev, RTK_PCI_TXBD_BCN_WORK, reg_bcn_work);
948 static int rtw_pci_write_data_h2c(struct rtw_dev *rtwdev, u8 *buf, u32 size)
954 skb = rtw_tx_write_data_h2c_get(rtwdev, &pkt_info, buf, size);
958 ret = rtw_pci_tx_write_data(rtwdev, &pkt_info, skb, RTW_TX_QUEUE_H2C);
963 rtw_err(rtwdev, "failed to write h2c data\n");
967 rtw_pci_tx_kick_off_queue(rtwdev, RTW_TX_QUEUE_H2C);
972 static int rtw_pci_tx_write(struct rtw_dev *rtwdev,
977 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
981 ret = rtw_pci_tx_write_data(rtwdev, pkt_info, skb, queue);
988 ieee80211_stop_queue(rtwdev->hw, skb_get_queue_mapping(skb));
996 static void rtw_pci_tx_isr(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci,
999 struct ieee80211_hw *hw = rtwdev->hw;
1012 bd_idx = rtw_read32(rtwdev, bd_idx_addr);
1024 rtw_err(rtwdev, "failed to dequeue %d skb TX queue %d, BD=0x%08x, rp %d -> %d\n",
1048 skb_pull(skb, rtwdev->chip->tx_pkt_desc_sz);
1054 rtw_tx_report_enqueue(rtwdev, skb, tx_data->sn);
1071 static void rtw_pci_rx_isr(struct rtw_dev *rtwdev)
1073 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
1079 static int rtw_pci_get_hw_rx_ring_nr(struct rtw_dev *rtwdev,
1087 tmp = rtw_read32(rtwdev, RTK_PCI_RXBD_IDX_MPDUQ);
1097 static u32 rtw_pci_rx_napi(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci,
1100 const struct rtw_chip_info *chip = rtwdev->chip;
1115 count = rtw_pci_get_hw_rx_ring_nr(rtwdev, rtwpci);
1119 rtw_pci_dma_check(rtwdev, ring, cur_rp);
1122 dma_sync_single_for_cpu(rtwdev->dev, dma, RTK_PCI_RX_BUF_SIZE,
1125 chip->ops->query_rx_desc(rtwdev, rx_desc, &pkt_stat, &rx_status);
1143 rtw_fw_c2h_cmd_rx_irqsafe(rtwdev, pkt_offset, new);
1148 rtw_rx_stats(rtwdev, pkt_stat.vif, new);
1150 ieee80211_rx_napi(rtwdev->hw, NULL, new, napi);
1156 rtw_pci_sync_rx_desc_device(rtwdev, dma, ring, cur_rp,
1169 rtw_write16(rtwdev, RTK_PCI_RXBD_IDX_MPDUQ, ring->r.rp);
1174 static void rtw_pci_irq_recognized(struct rtw_dev *rtwdev,
1181 irq_status[0] = rtw_read32(rtwdev, RTK_PCI_HISR0);
1182 irq_status[1] = rtw_read32(rtwdev, RTK_PCI_HISR1);
1183 if (rtw_chip_wcpu_11ac(rtwdev))
1184 irq_status[3] = rtw_read32(rtwdev, RTK_PCI_HISR3);
1190 rtw_write32(rtwdev, RTK_PCI_HISR0, irq_status[0]);
1191 rtw_write32(rtwdev, RTK_PCI_HISR1, irq_status[1]);
1192 if (rtw_chip_wcpu_11ac(rtwdev))
1193 rtw_write32(rtwdev, RTK_PCI_HISR3, irq_status[3]);
1200 struct rtw_dev *rtwdev = dev;
1201 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
1211 rtw_pci_disable_interrupt(rtwdev, rtwpci);
1218 struct rtw_dev *rtwdev = dev;
1219 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
1224 rtw_pci_irq_recognized(rtwdev, rtwpci, irq_status);
1227 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_MGMT);
1229 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_HI0);
1231 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_BE);
1233 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_BK);
1235 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_VO);
1237 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_VI);
1239 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_H2C);
1241 rtw_pci_rx_isr(rtwdev);
1245 rtw_fw_c2h_cmd_isr(rtwdev);
1249 rtw_pci_enable_interrupt(rtwdev, rtwpci, rx);
1255 static int rtw_pci_io_mapping(struct rtw_dev *rtwdev,
1258 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
1265 rtw_err(rtwdev, "failed to request pci regions\n");
1272 rtw_err(rtwdev, "failed to set dma mask to 32-bit\n");
1278 rtw_err(rtwdev, "failed to set consistent dma mask to 32-bit\n");
1290 rtw_err(rtwdev, "failed to map pci memory\n");
1302 static void rtw_pci_io_unmapping(struct rtw_dev *rtwdev,
1305 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
1313 static void rtw_dbi_write8(struct rtw_dev *rtwdev, u16 addr, u8 data)
1322 rtw_write8(rtwdev, REG_DBI_WDATA_V1 + remainder, data);
1323 rtw_write16(rtwdev, REG_DBI_FLAG_V1, write_addr);
1324 rtw_write8(rtwdev, REG_DBI_FLAG_V1 + 2, BIT_DBI_WFLAG >> 16);
1327 flag = rtw_read8(rtwdev, REG_DBI_FLAG_V1 + 2);
1337 static int rtw_dbi_read8(struct rtw_dev *rtwdev, u16 addr, u8 *value)
1343 rtw_write16(rtwdev, REG_DBI_FLAG_V1, read_addr);
1344 rtw_write8(rtwdev, REG_DBI_FLAG_V1 + 2, BIT_DBI_RFLAG >> 16);
1347 flag = rtw_read8(rtwdev, REG_DBI_FLAG_V1 + 2);
1350 *value = rtw_read8(rtwdev, read_addr);
1361 static void rtw_mdio_write(struct rtw_dev *rtwdev, u8 addr, u16 data, bool g1)
1367 rtw_write16(rtwdev, REG_MDIO_V1, data);
1371 rtw_write8(rtwdev, REG_PCIE_MIX_CFG, addr & BITS_MDIO_ADDR_MASK);
1372 rtw_write8(rtwdev, REG_PCIE_MIX_CFG + 3, page);
1373 rtw_write32_mask(rtwdev, REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1, 1);
1376 wflag = rtw_read32_mask(rtwdev, REG_PCIE_MIX_CFG,
1387 static void rtw_pci_clkreq_set(struct rtw_dev *rtwdev, bool enable)
1395 ret = rtw_dbi_read8(rtwdev, RTK_PCIE_LINK_CFG, &value);
1397 rtw_err(rtwdev, "failed to read CLKREQ_L1, ret=%d", ret);
1406 rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value);
1409 static void rtw_pci_clkreq_pad_low(struct rtw_dev *rtwdev, bool enable)
1414 ret = rtw_dbi_read8(rtwdev, RTK_PCIE_LINK_CFG, &value);
1416 rtw_err(rtwdev, "failed to read CLKREQ_L1, ret=%d", ret);
1425 rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value);
1428 static void rtw_pci_aspm_set(struct rtw_dev *rtwdev, bool enable)
1436 ret = rtw_dbi_read8(rtwdev, RTK_PCIE_LINK_CFG, &value);
1438 rtw_err(rtwdev, "failed to read ASPM, ret=%d", ret);
1447 rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value);
1450 static void rtw_pci_link_ps(struct rtw_dev *rtwdev, bool enter)
1452 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
1469 rtw_pci_aspm_set(rtwdev, enter);
1472 static void rtw_pci_link_cfg(struct rtw_dev *rtwdev)
1474 const struct rtw_chip_info *chip = rtwdev->chip;
1475 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
1484 rtw_dbi_write8(rtwdev, RTK_PCIE_CLKDLY_CTRL, 0);
1504 rtw_err(rtwdev, "failed to read PCI cap, ret=%d\n", ret);
1509 rtw_pci_clkreq_set(rtwdev, true);
1514 static void rtw_pci_interface_cfg(struct rtw_dev *rtwdev)
1516 const struct rtw_chip_info *chip = rtwdev->chip;
1520 if (rtwdev->hal.cut_version >= RTW_CHIP_VER_CUT_D)
1521 rtw_write32_mask(rtwdev, REG_HCI_MIX_CFG,
1529 static void rtw_pci_phy_cfg(struct rtw_dev *rtwdev)
1531 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
1532 const struct rtw_chip_info *chip = rtwdev->chip;
1533 struct rtw_efuse *efuse = &rtwdev->efuse;
1542 cut = BIT(0) << rtwdev->hal.cut_version;
1553 rtw_mdio_write(rtwdev, offset, value, true);
1555 rtw_dbi_write8(rtwdev, offset, value);
1567 rtw_mdio_write(rtwdev, offset, value, false);
1569 rtw_dbi_write8(rtwdev, offset, value);
1572 rtw_pci_link_cfg(rtwdev);
1579 rtw_err(rtwdev, "failed to set PCI cap, ret = %d\n",
1584 rtw_write32_mask(rtwdev, REG_ANAPARSW_MAC_0, BIT_CF_L_V2, 0x1);
1590 struct rtw_dev *rtwdev = hw->priv;
1591 const struct rtw_chip_info *chip = rtwdev->chip;
1592 struct rtw_efuse *efuse = &rtwdev->efuse;
1595 rtw_pci_clkreq_pad_low(rtwdev, true);
1602 struct rtw_dev *rtwdev = hw->priv;
1603 const struct rtw_chip_info *chip = rtwdev->chip;
1604 struct rtw_efuse *efuse = &rtwdev->efuse;
1607 rtw_pci_clkreq_pad_low(rtwdev, false);
1614 static int rtw_pci_claim(struct rtw_dev *rtwdev, struct pci_dev *pdev)
1620 rtw_err(rtwdev, "failed to enable pci device\n");
1625 pci_set_drvdata(pdev, rtwdev->hw);
1626 SET_IEEE80211_DEV(rtwdev->hw, &pdev->dev);
1631 static void rtw_pci_declaim(struct rtw_dev *rtwdev, struct pci_dev *pdev)
1636 static int rtw_pci_setup_resource(struct rtw_dev *rtwdev, struct pci_dev *pdev)
1641 rtwpci = (struct rtw_pci *)rtwdev->priv;
1645 ret = rtw_pci_io_mapping(rtwdev, pdev);
1647 rtw_err(rtwdev, "failed to request pci io region\n");
1651 ret = rtw_pci_init(rtwdev);
1653 rtw_err(rtwdev, "failed to allocate pci resources\n");
1660 rtw_pci_io_unmapping(rtwdev, pdev);
1666 static void rtw_pci_destroy(struct rtw_dev *rtwdev, struct pci_dev *pdev)
1668 rtw_pci_deinit(rtwdev);
1669 rtw_pci_io_unmapping(rtwdev, pdev);
1693 static int rtw_pci_request_irq(struct rtw_dev *rtwdev, struct pci_dev *pdev)
1703 rtw_err(rtwdev, "failed to alloc PCI irq vectors\n");
1707 ret = devm_request_threaded_irq(rtwdev->dev, pdev->irq,
1710 IRQF_SHARED, KBUILD_MODNAME, rtwdev);
1712 rtw_err(rtwdev, "failed to request irq %d\n", ret);
1719 static void rtw_pci_free_irq(struct rtw_dev *rtwdev, struct pci_dev *pdev)
1721 devm_free_irq(rtwdev->dev, pdev->irq, rtwdev);
1728 struct rtw_dev *rtwdev = container_of((void *)rtwpci, struct rtw_dev,
1733 rtw_pci_link_ps(rtwdev, false);
1738 work_done_once = rtw_pci_rx_napi(rtwdev, rtwpci, RTW_RX_QUEUE_MPDU,
1748 rtw_pci_enable_interrupt(rtwdev, rtwpci, false);
1755 if (rtw_pci_get_hw_rx_ring_nr(rtwdev, rtwpci))
1759 rtw_pci_link_ps(rtwdev, true);
1764 static int rtw_pci_napi_init(struct rtw_dev *rtwdev)
1766 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
1776 static void rtw_pci_napi_deinit(struct rtw_dev *rtwdev)
1778 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv;
1780 rtw_pci_napi_stop(rtwdev);
1790 struct rtw_dev *rtwdev;
1802 rtwdev = hw->priv;
1803 rtwdev->hw = hw;
1804 rtwdev->dev = &pdev->dev;
1805 rtwdev->chip = (struct rtw_chip_info *)id->driver_data;
1806 rtwdev->hci.ops = &rtw_pci_ops;
1807 rtwdev->hci.type = RTW_HCI_TYPE_PCIE;
1809 rtwpci = (struct rtw_pci *)rtwdev->priv;
1812 ret = rtw_core_init(rtwdev);
1816 rtw_dbg(rtwdev, RTW_DBG_PCI,
1820 ret = rtw_pci_claim(rtwdev, pdev);
1822 rtw_err(rtwdev, "failed to claim pci device\n");
1826 ret = rtw_pci_setup_resource(rtwdev, pdev);
1828 rtw_err(rtwdev, "failed to setup pci resources\n");
1832 ret = rtw_pci_napi_init(rtwdev);
1834 rtw_err(rtwdev, "failed to setup NAPI\n");
1838 ret = rtw_chip_info_setup(rtwdev);
1840 rtw_err(rtwdev, "failed to setup chip information\n");
1845 if (rtwdev->chip->id == RTW_CHIP_TYPE_8821C && bridge->vendor == PCI_VENDOR_ID_INTEL)
1848 rtw_pci_phy_cfg(rtwdev);
1850 ret = rtw_register_hw(rtwdev, hw);
1852 rtw_err(rtwdev, "failed to register hw\n");
1856 ret = rtw_pci_request_irq(rtwdev, pdev);
1865 rtw_pci_napi_deinit(rtwdev);
1866 rtw_pci_destroy(rtwdev, pdev);
1869 rtw_pci_declaim(rtwdev, pdev);
1872 rtw_core_deinit(rtwdev);
1884 struct rtw_dev *rtwdev;
1890 rtwdev = hw->priv;
1891 rtwpci = (struct rtw_pci *)rtwdev->priv;
1893 rtw_unregister_hw(rtwdev, hw);
1894 rtw_pci_disable_interrupt(rtwdev, rtwpci);
1895 rtw_pci_napi_deinit(rtwdev);
1896 rtw_pci_destroy(rtwdev, pdev);
1897 rtw_pci_declaim(rtwdev, pdev);
1898 rtw_pci_free_irq(rtwdev, pdev);
1899 rtw_core_deinit(rtwdev);
1907 struct rtw_dev *rtwdev;
1913 rtwdev = hw->priv;
1914 chip = rtwdev->chip;
1917 chip->ops->shutdown(rtwdev);