Lines Matching full:u8
79 u8 bulkout_num;
459 u8 cck_base[6];
460 u8 bw40_base[5];
512 u8 bw40_base[14];
530 u8 center_chan;
531 u8 primary_chan;
532 u8 bandwidth;
561 u8 domain;
573 u8 offset;
577 u8 len;
600 u8 offset;
601 u8 pkt_offset;
602 u8 tim_offset;
603 u8 mac_id;
604 u8 rate_id;
605 u8 rate;
606 u8 qsel;
607 u8 bw;
608 u8 sec_type;
609 u8 sn;
611 u8 ampdu_factor;
612 u8 ampdu_density;
626 u8 hw_ssn_sel;
641 u8 bw;
642 u8 drv_info_sz;
643 u8 shift;
644 u8 rate;
645 u8 mac_id;
646 u8 cam_id;
647 u8 ppdu_cnt;
650 u8 rssi;
651 u8 rxsc;
653 u8 rx_evm[RTW_RF_PATH_MAX];
656 u8 band;
704 u8 awake_interval;
705 u8 rlbm;
706 u8 smart_ps;
707 u8 port_id;
723 u8 addr[ETH_ALEN];
724 u8 hw_key_type;
748 u8 desc_rate;
764 u8 rssi_level;
766 u8 mac_id;
767 u8 rate_id;
769 u8 stbc_en:2;
770 u8 ldpc_en:2;
773 u8 init_ra_lv;
796 u8 g_id;
797 u8 mac_addr[ETH_ALEN];
798 u8 sound_dim;
801 u8 su_reg_index;
808 u8 bfer_mu_cnt;
809 u8 bfer_su_cnt;
811 u8 cur_csi_rpt_rate;
817 u8 mac_id;
818 u8 mac_addr[ETH_ALEN];
819 u8 bssid[ETH_ALEN];
820 u8 port;
821 u8 bcn_ctrl;
835 u8 txpwr_regd_2g;
836 u8 txpwr_regd_5g;
859 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
861 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
862 u8 bandwidth, u8 primary_chan_idx);
863 void (*query_phy_status)(struct rtw_dev *rtwdev, u8 *phy_status,
870 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
880 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
887 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
888 u8 fixrate_en, u8 *new_rate);
893 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path,
897 void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path,
898 u8 rx_path, bool is_tx2_path);
903 u8 *txdesc);
908 u8 ctrl_type, u8 pos_type);
912 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
952 u8 cut_mask;
953 u8 intf_mask;
954 u8 base:4;
955 u8 cmd:4;
956 u8 mask;
957 u8 value;
1050 u8 type;
1051 u8 valid;
1052 u8 mask[RTW_MAX_PATTERN_MASK_SIZE];
1059 u8 channel_cnt;
1067 u8 txpause;
1068 u8 pattern_cnt;
1080 u8 n_usb2_para;
1081 u8 n_usb3_para;
1082 u8 n_gen1_para;
1083 u8 n_gen2_para;
1142 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM];
1143 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM];
1144 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM];
1145 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM];
1146 const u8 *pwrtrk_2gb_n;
1147 const u8 *pwrtrk_2gb_p;
1148 const u8 *pwrtrk_2ga_n;
1149 const u8 *pwrtrk_2ga_p;
1150 const u8 *pwrtrk_2g_cckb_n;
1151 const u8 *pwrtrk_2g_cckb_p;
1152 const u8 *pwrtrk_2g_ccka_n;
1153 const u8 *pwrtrk_2g_ccka_p;
1186 u8 id;
1190 u8 tx_pkt_desc_sz;
1191 u8 tx_buf_desc_sz;
1192 u8 rx_pkt_desc_sz;
1193 u8 rx_buf_desc_sz;
1201 u8 band;
1203 u8 csi_buf_pg_num;
1204 u8 dig_max;
1205 u8 dig_min;
1206 u8 txgi_factor;
1210 u8 max_power_index;
1211 u8 ampdu_density;
1216 u8 usb_tx_agg_desc_num;
1218 u8 c2h_ra_report_size;
1221 u8 default_1ss_tx_path;
1226 u8 lps_deep_mode_supported;
1229 u8 sys_func_en;
1242 u8 fix_rf_phy_num;
1256 u8 iqk_threshold;
1257 u8 lck_threshold;
1259 u8 bfer_su_max_num;
1260 u8 bfer_mu_max_num;
1268 const u8 max_sched_scan_ssids;
1273 u8 bt_desired_ver;
1278 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
1279 u8 bt_rssi_type;
1280 u8 ant_isolation;
1281 u8 rssi_tolerance;
1282 u8 table_sant_num;
1283 u8 table_nsant_num;
1284 u8 tdma_sant_num;
1285 u8 tdma_nsant_num;
1286 u8 bt_afh_span_bw20;
1287 u8 bt_afh_span_bw40;
1288 u8 afh_5g_num;
1289 u8 wl_rf_para_num;
1290 u8 coex_info_hw_regs_num;
1291 const u8 *bt_rssi_step;
1292 const u8 *wl_rssi_step;
1340 u8 rfe_module_type;
1341 u8 ant_switch_polarity;
1354 u8 reason;
1355 u8 bt_rssi_state[4];
1356 u8 wl_rssi_state[4];
1357 u8 wl_ch_info[3];
1358 u8 cur_ps_tdma;
1359 u8 cur_table;
1360 u8 ps_tdma_para[5];
1361 u8 cur_bt_pwr_lvl;
1362 u8 cur_bt_lna_lvl;
1363 u8 cur_wl_pwr_lvl;
1364 u8 bt_status;
1368 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH];
1402 u8 hid_handle;
1403 u8 hid_vendor;
1404 u8 hid_name[COEX_BT_HIDINFO_NAME];
1410 u8 cmd_id;
1411 u8 len;
1412 u8 subid;
1413 u8 handle_cnt;
1414 u8 handle[COEX_BT_HIDINFO_HANDLE_NUM];
1418 u8 cmd_id;
1419 u8 len;
1420 u8 subid;
1421 u8 handle;
1422 u8 vendor;
1423 u8 name[COEX_BT_HIDINFO_NAME];
1490 u8 kt_ver;
1491 u8 gnt_workaround_state;
1492 u8 tdma_timer_base;
1493 u8 bt_profile_num;
1494 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
1495 u8 bt_info_lb2;
1496 u8 bt_info_lb3;
1497 u8 bt_info_hb0;
1498 u8 bt_info_hb1;
1499 u8 bt_info_hb2;
1500 u8 bt_info_hb3;
1501 u8 bt_ble_scan_type;
1502 u8 bt_hid_pair_num;
1503 u8 bt_hid_slot;
1504 u8 bt_a2dp_bitpool;
1505 u8 bt_iqk_state;
1506 u8 bt_disable_cnt;
1509 u8 wl_noisy_level;
1510 u8 wl_fw_dbg_info[10];
1511 u8 wl_fw_dbg_info_pre[10];
1512 u8 wl_rx_rate;
1513 u8 wl_tx_rate;
1514 u8 wl_rts_rx_rate;
1515 u8 wl_coex_mode;
1516 u8 wl_iot_peer;
1517 u8 ampdu_max_time;
1518 u8 wl_tput_dir;
1520 u8 wl_toggle_para[6];
1521 u8 wl_toggle_interval;
1581 u8 thermal_dpk[DPK_RF_PATH_NUM];
1587 u8 result[RTW_RF_PATH_MAX];
1588 u8 dpk_txagc[RTW_RF_PATH_MAX];
1591 u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
1592 u8 pre_pwsf[RTW_RF_PATH_MAX];
1594 u8 dpk_band;
1595 u8 dpk_ch;
1596 u8 dpk_bw;
1610 const u8 *p[RTW_RF_PATH_MAX];
1611 const u8 *n[RTW_RF_PATH_MAX];
1650 u8 read_txgain;
1651 u8 channel;
1670 u8 crystal_cap;
1703 u8 min_rssi;
1704 u8 pre_min_rssi;
1706 u8 igi_history[4];
1707 u8 igi_bitmap;
1709 u8 damping_cnt;
1710 u8 damping_rssi;
1712 u8 cck_gi_u_bnd;
1713 u8 cck_gi_l_bnd;
1715 u8 fix_rate;
1716 u8 tx_rate;
1719 u8 thermal_avg[RTW_RF_PATH_MAX];
1720 u8 thermal_meter_k;
1721 u8 thermal_meter_lck;
1724 u8 default_ofdm_index;
1725 u8 default_cck_index;
1731 u8 rx_cck_agc_report_type;
1736 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
1742 u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
1744 u8 cck_pd_default;
1748 u8 rx_evm_dbm[RTW_RF_PATH_MAX];
1750 u8 rssi[RTW_RF_PATH_MAX];
1751 u8 curr_rx_rate;
1764 u8 scan_density;
1773 u8 addr[ETH_ALEN];
1774 u8 channel_plan;
1775 u8 country_code[2];
1776 u8 rf_board_option;
1777 u8 rfe_option;
1778 u8 power_track_type;
1779 u8 thermal_meter[RTW_RF_PATH_MAX];
1780 u8 thermal_meter_k;
1781 u8 crystal_cap;
1782 u8 ant_div_cfg;
1783 u8 ant_div_type;
1784 u8 regd;
1785 u8 afe;
1787 u8 lna_type_2g;
1788 u8 lna_type_5g;
1789 u8 glna_type;
1790 u8 alna_type;
1793 u8 pa_type_2g;
1794 u8 pa_type_5g;
1795 u8 gpa_type;
1796 u8 apa_type;
1799 u8 tx_bb_swing_setting_2g;
1800 u8 tx_bb_swing_setting_5g;
1805 u8 bt_setting;
1807 u8 usb_mode_switch;
1810 u8 hci;
1811 u8 bw;
1812 u8 ptcl;
1813 u8 nss;
1814 u8 ant_num;
1855 u8 type_glna;
1856 u8 type_gpa;
1857 u8 type_alna;
1858 u8 type_apa;
1860 u8 type_apa;
1861 u8 type_alna;
1862 u8 type_gpa;
1863 u8 type_glna;
1886 u8 *next;
1887 u8 *data;
1892 u8 num;
1904 u8 sub_version;
1905 u8 sub_index;
1943 u8 cut_version;
1944 u8 mp_chip;
1945 u8 oem_id;
1946 u8 pkg_type;
1951 u8 ps_mode;
1952 u8 current_channel;
1953 u8 current_primary_channel_index;
1954 u8 current_band_width;
1955 u8 current_band_type;
1956 u8 primary_channel;
1961 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
1963 u8 sec_ch_offset;
1964 u8 rf_type;
1965 u8 rf_path_num;
1966 u8 rf_phy_num;
1969 u8 bfee_sts_cap;
2013 u8 extra_info;
2014 u8 channel;
2027 u8 probe_pg_size;
2028 u8 op_pri_ch_idx;
2029 u8 op_pri_ch;
2030 u8 op_chan;
2031 u8 op_bw;
2081 u8 last_box_num;
2093 u8 sta_cnt;
2100 u8 mp_mode;
2115 u8 priv[] __aligned(sizeof(void *));
2171 static inline u8 rtw_acquire_macid(struct rtw_dev *rtwdev)
2182 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id)
2209 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel);
2218 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss);
2227 const u8 *mac_addr, bool hw_scan);
2238 u16 rtw_desc_to_bitrate(u8 desc_rate);
2253 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel,
2254 u8 primary_channel, enum rtw_supported_band band,