Lines Matching +full:efuse +full:- +full:size
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
20 #include "efuse.h"
163 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4,
176 struct rtw_bf_info *bf_info = &rtwdev->bf_info;
180 if (rtwvif->bfee.role != RTW_BFEE_SU &&
181 rtwvif->bfee.role != RTW_BFEE_MU)
184 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi,
185 bf_info->cur_csi_rpt_rate,
188 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
189 bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
195 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
197 if (vif->type == NL80211_IFTYPE_STATION)
198 if (vif->cfg.assoc)
199 iter_data->rtwvif = rtwvif;
201 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif);
203 rtwvif->stats.tx_unicast = 0;
204 rtwvif->stats.rx_unicast = 0;
205 rtwvif->stats.tx_cnt = 0;
206 rtwvif->stats.rx_cnt = 0;
216 struct rtw_traffic_stats *stats = &rtwdev->stats;
218 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
221 mutex_lock(&rtwdev->mutex);
223 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags))
226 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
229 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100)
230 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
232 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
234 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags))
237 if (stats->tx_cnt > RTW_LPS_THRESHOLD ||
238 stats->rx_cnt > RTW_LPS_THRESHOLD)
243 ewma_tp_add(&stats->tx_ewma_tp,
244 (u32)(stats->tx_unicast >> RTW_TP_SHIFT));
245 ewma_tp_add(&stats->rx_ewma_tp,
246 (u32)(stats->rx_unicast >> RTW_TP_SHIFT));
247 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
248 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
251 stats->tx_unicast = 0;
252 stats->rx_unicast = 0;
253 stats->tx_cnt = 0;
254 stats->rx_cnt = 0;
256 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
268 * to avoid taking local->iflist_mtx mutex
277 * ps by vif->type and vif->cfg.ps, all we need to do here is to
281 if (rtwdev->ps_enabled && data.rtwvif && !ps_active &&
282 !rtwdev->beacon_loss && !rtwdev->ap_active)
283 rtw_enter_lps(rtwdev, data.rtwvif->port);
285 rtwdev->watch_dog_cnt++;
288 mutex_unlock(&rtwdev->mutex);
296 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
297 skb_unlink(skb, &rtwdev->c2h_queue);
307 mutex_lock(&rtwdev->mutex);
308 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)
310 mutex_unlock(&rtwdev->mutex);
317 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM);
319 set_bit(mac_id, rtwdev->mac_id_map);
328 struct rtw_dev *rtwdev = si->rtwdev;
330 mutex_lock(&rtwdev->mutex);
332 mutex_unlock(&rtwdev->mutex);
338 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
339 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
342 si->mac_id = rtw_acquire_macid(rtwdev);
343 if (si->mac_id >= RTW_MAX_MAC_ID_NUM)
344 return -ENOSPC;
346 if (vif->type == NL80211_IFTYPE_STATION && vif->cfg.assoc == 0)
347 rtwvif->mac_id = si->mac_id;
348 si->rtwdev = rtwdev;
349 si->sta = sta;
350 si->vif = vif;
351 si->init_ra_lv = 1;
352 ewma_rssi_init(&si->avg_rssi);
353 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
354 rtw_txq_init(rtwdev, sta->txq[i]);
355 INIT_WORK(&si->rc_work, rtw_sta_rc_work);
358 rtw_fw_media_status_report(rtwdev, si->mac_id, true);
360 rtwdev->sta_cnt++;
361 rtwdev->beacon_loss = false;
364 sta->addr, si->mac_id);
367 sta->addr, ":", si->mac_id);
376 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
379 cancel_work_sync(&si->rc_work);
381 rtw_release_macid(rtwdev, si->mac_id);
383 rtw_fw_media_status_report(rtwdev, si->mac_id, false);
385 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
386 rtw_txq_cleanup(rtwdev, sta->txq[i]);
388 kfree(si->mask);
390 rtwdev->sta_cnt--;
393 sta->addr, si->mac_id);
396 sta->addr, ":", si->mac_id);
402 u32 size;
409 const struct rtw_chip_info *chip = rtwdev->chip;
410 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
411 const struct rtw_fwcd_segs *segs = chip->fwcd_segs;
412 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr);
416 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr);
418 for (i = 0; i < segs->num; i++)
419 prep_size += segs->segs[i];
422 desc->data = vmalloc(prep_size);
423 if (!desc->data)
424 return -ENOMEM;
426 desc->size = prep_size;
427 desc->next = desc->data;
432 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size)
434 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
438 if (!desc->data) {
443 next = desc->next + sizeof(struct rtw_fwcd_hdr);
444 if (next - desc->data + size > desc->size) {
449 hdr = (struct rtw_fwcd_hdr *)(desc->next);
450 hdr->item = item;
451 hdr->size = size;
452 hdr->padding1 = 0x01234567;
453 hdr->padding2 = 0x89abcdef;
454 desc->next = next + size;
461 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
470 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL);
475 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
479 vfree(desc->data);
482 desc->data = NULL;
483 desc->next = NULL;
488 u32 size = rtwdev->chip->fw_rxff_size;
492 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size);
494 return -ENOMEM;
496 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) {
498 return -EINVAL;
503 return -EINVAL;
510 return -EINVAL;
516 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
519 u32 rxff = rtwdev->chip->fw_rxff_size;
524 buf = rtw_fwcd_next(rtwdev, fwcd_item, size);
526 return -ENOMEM;
528 while (size) {
529 dump_size = size > rxff ? rxff : size;
549 size -= dump_size;
557 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size)
563 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr);
564 return -EINVAL;
567 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size);
569 return -ENOMEM;
571 for (i = 0; i < size; i += 4)
586 if (conf && vif->cfg.assoc) {
587 rtwvif->aid = vif->cfg.aid;
588 rtwvif->net_type = RTW_NET_MGD_LINKED;
590 rtwvif->aid = 0;
591 rtwvif->net_type = RTW_NET_NO_LINK;
602 struct rtw_sec_desc *sec = &rtwdev->sec;
604 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx);
611 if (rtwdev->sta_cnt == 0) {
621 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
625 rtw_txq_cleanup(rtwdev, vif->txq);
630 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags))
631 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work);
638 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags);
639 clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags);
663 bitmap_zero(rtwdev->hw_port, RTW_PORT_NUM);
672 mutex_lock(&rtwdev->mutex);
674 mutex_unlock(&rtwdev->mutex);
676 ieee80211_restart_hw(rtwdev->hw);
684 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
688 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
690 clear_bit(tid, si->tid_ba);
692 if (ret == -EINVAL) {
696 txq = sta->txq[tid];
697 rtwtxq = (struct rtw_txq *)txq->drv_priv;
698 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags);
701 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
716 pkt_stat->band = NL80211_BAND_2GHZ;
718 pkt_stat->band = NL80211_BAND_5GHZ;
722 pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band);
729 rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1);
737 struct rtw_hal *hal = &rtwdev->hal;
738 u8 *cch_by_bw = hal->cch_by_bw;
765 if (primary_freq - center_freq == 10)
775 if (center_freq - primary_freq == 10)
783 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel - 4;
807 hal->current_primary_channel_index = primary_channel_idx;
808 hal->current_band_width = bandwidth;
809 hal->primary_channel = primary_channel;
810 hal->current_channel = center_channel;
811 hal->current_band_type = band;
812 hal->sar_band = sar_band;
818 struct ieee80211_channel *channel = chandef->chan;
819 enum nl80211_chan_width width = chandef->width;
824 center_chan = channel->hw_value;
825 primary_freq = channel->center_freq;
826 center_freq = chandef->center_freq1;
836 center_chan -= 2;
843 if (primary_freq - center_freq == 10)
844 center_chan -= 2;
846 center_chan -= 6;
848 if (center_freq - primary_freq == 10)
859 chan_params->center_chan = center_chan;
860 chan_params->bandwidth = bandwidth;
861 chan_params->primary_chan = channel->hw_value;
866 const struct rtw_chip_info *chip = rtwdev->chip;
867 struct ieee80211_hw *hw = rtwdev->hw;
868 struct rtw_hal *hal = &rtwdev->hal;
872 rtw_get_channel_params(&hw->conf.chandef, &ch_param);
883 if (rtwdev->scan_info.op_chan)
886 chip->ops->set_channel(rtwdev, center_chan, bandwidth,
887 hal->current_primary_channel_index);
889 if (hal->current_band_type == RTW_BAND_5G) {
892 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
904 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
905 rtwdev->need_rfk = true;
910 const struct rtw_chip_info *chip = rtwdev->chip;
912 if (rtwdev->need_rfk) {
913 rtwdev->need_rfk = false;
914 chip->ops->phy_calibration(rtwdev);
933 addr = rtwvif->conf->mac_addr.addr;
934 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr);
937 addr = rtwvif->conf->bssid.addr;
938 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid);
941 addr = rtwvif->conf->net_type.addr;
942 mask = rtwvif->conf->net_type.mask;
943 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type);
946 addr = rtwvif->conf->aid.addr;
947 mask = rtwvif->conf->aid.mask;
948 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid);
951 addr = rtwvif->conf->bcn_ctrl.addr;
952 mask = rtwvif->conf->bcn_ctrl.mask;
953 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl);
979 const struct rtw_chip_info *chip = rtwdev->chip;
980 struct rtw_hal *hal = &rtwdev->hal;
983 hw_ant_num >= hal->rf_path_num)
988 hal->rf_type = RF_1T1R;
989 hal->rf_path_num = 1;
990 if (!chip->fix_rf_phy_num)
991 hal->rf_phy_num = hal->rf_path_num;
992 hal->antenna_tx = BB_PATH_A;
993 hal->antenna_rx = BB_PATH_A;
996 WARN(1, "invalid hw configuration from efuse\n");
1004 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map);
1133 u8 rssi_level = si->rssi_level;
1166 struct rtw_hal *hal = &rtwdev->hal;
1167 const struct cfg80211_bitrate_mask *mask = si->mask;
1171 if (!si->use_cfg_mask)
1174 band = hal->current_band_type;
1177 cfg_mask = mask->control[band].legacy;
1180 cfg_mask = u64_encode_bits(mask->control[band].legacy,
1186 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
1189 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
1193 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
1196 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
1208 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1209 struct ieee80211_sta *sta = si->sta;
1210 struct rtw_efuse *efuse = &rtwdev->efuse;
1211 struct rtw_hal *hal = &rtwdev->hal;
1224 if (sta->deflink.vht_cap.vht_supported) {
1227 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
1229 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
1231 } else if (sta->deflink.ht_cap.ht_supported) {
1232 ra_mask |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) |
1233 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1234 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
1236 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
1240 if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss)
1243 if (hal->current_band_type == RTW_BAND_5G) {
1244 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4;
1246 if (sta->deflink.vht_cap.vht_supported) {
1249 } else if (sta->deflink.ht_cap.ht_supported) {
1255 dm_info->rrsr_val_init = RRSR_INIT_5G;
1256 } else if (hal->current_band_type == RTW_BAND_2G) {
1257 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ];
1259 if (sta->deflink.vht_cap.vht_supported) {
1264 } else if (sta->deflink.ht_cap.ht_supported) {
1270 } else if (sta->deflink.supp_rates[0] <= 0xf) {
1272 } else if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] <= 0xf) {
1279 dm_info->rrsr_val_init = RRSR_INIT_2G;
1286 switch (sta->deflink.bandwidth) {
1289 is_support_sgi = sta->deflink.vht_cap.vht_supported &&
1290 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
1294 is_support_sgi = sta->deflink.ht_cap.ht_supported &&
1295 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
1299 is_support_sgi = sta->deflink.ht_cap.ht_supported &&
1300 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
1304 if (sta->deflink.vht_cap.vht_supported && ra_mask & 0xffc00000) {
1307 } else if (sta->deflink.ht_cap.ht_supported && ra_mask & 0xfff00000) {
1318 si->bw_mode = bw_mode;
1319 si->stbc_en = stbc_en;
1320 si->ldpc_en = ldpc_en;
1321 si->rf_type = rf_type;
1322 si->sgi_enable = is_support_sgi;
1323 si->vht_enable = is_vht_enable;
1324 si->ra_mask = ra_mask;
1325 si->rate_id = rate_id;
1332 const struct rtw_chip_info *chip = rtwdev->chip;
1335 fw = &rtwdev->fw;
1336 wait_for_completion(&fw->completion);
1337 if (!fw->firmware)
1338 return -EINVAL;
1340 if (chip->wow_fw_name) {
1341 fw = &rtwdev->wow_fw;
1342 wait_for_completion(&fw->completion);
1343 if (!fw->firmware)
1344 return -EINVAL;
1353 const struct rtw_chip_info *chip = rtwdev->chip;
1355 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported ||
1356 !fw->feature)
1359 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) &&
1363 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) &&
1372 const struct rtw_chip_info *chip = rtwdev->chip;
1373 struct rtw_fw_state *fw = &rtwdev->fw;
1409 chip->ops->phy_set_param(rtwdev);
1421 wifi_only = !rtwdev->efuse.btcoex;
1436 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN))
1442 reinit_completion(&rtwdev->fw_scan_density);
1444 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density,
1458 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) {
1466 ether_addr_copy(rtwvif->mac_addr, mac_addr);
1473 set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
1474 set_bit(RTW_FLAG_SCANNING, rtwdev->flags);
1480 struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL;
1486 clear_bit(RTW_FLAG_SCANNING, rtwdev->flags);
1487 clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
1491 ether_addr_copy(rtwvif->mac_addr, vif->addr);
1497 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
1498 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work);
1511 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw);
1512 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw);
1515 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr);
1517 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
1520 set_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1534 struct rtw_coex *coex = &rtwdev->coex;
1536 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1537 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
1539 mutex_unlock(&rtwdev->mutex);
1541 cancel_work_sync(&rtwdev->c2h_work);
1542 cancel_work_sync(&rtwdev->update_beacon_work);
1543 cancel_delayed_work_sync(&rtwdev->watch_dog_work);
1544 cancel_delayed_work_sync(&coex->bt_relink_work);
1545 cancel_delayed_work_sync(&coex->bt_reenable_work);
1546 cancel_delayed_work_sync(&coex->defreeze_work);
1547 cancel_delayed_work_sync(&coex->wl_remain_work);
1548 cancel_delayed_work_sync(&coex->bt_remain_work);
1549 cancel_delayed_work_sync(&coex->wl_connecting_work);
1550 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work);
1551 cancel_delayed_work_sync(&coex->wl_ccklock_work);
1553 mutex_lock(&rtwdev->mutex);
1561 const struct rtw_chip_info *chip = rtwdev->chip;
1562 struct rtw_efuse *efuse = &rtwdev->efuse;
1564 ht_cap->ht_supported = true;
1565 ht_cap->cap = 0;
1566 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
1571 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
1573 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC;
1575 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40))
1576 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1579 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1580 ht_cap->ampdu_density = chip->ampdu_density;
1581 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
1582 if (efuse->hw_cap.nss > 1) {
1583 ht_cap->mcs.rx_mask[0] = 0xFF;
1584 ht_cap->mcs.rx_mask[1] = 0xFF;
1585 ht_cap->mcs.rx_mask[4] = 0x01;
1586 ht_cap->mcs.rx_highest = cpu_to_le16(300);
1588 ht_cap->mcs.rx_mask[0] = 0xFF;
1589 ht_cap->mcs.rx_mask[1] = 0x00;
1590 ht_cap->mcs.rx_mask[4] = 0x01;
1591 ht_cap->mcs.rx_highest = cpu_to_le16(150);
1598 struct rtw_efuse *efuse = &rtwdev->efuse;
1602 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE &&
1603 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT)
1606 vht_cap->vht_supported = true;
1607 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
1613 if (rtwdev->hal.rf_path_num > 1)
1614 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
1615 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
1617 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap <<
1621 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
1630 if (efuse->hw_cap.nss > 1) {
1638 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
1639 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
1640 vht_cap->vht_mcs.rx_highest = highest;
1641 vht_cap->vht_mcs.tx_highest = highest;
1648 len = rtwdev->chip->max_scan_ie_len;
1650 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_SCAN_OFFLOAD) &&
1651 rtwdev->chip->id == RTW_CHIP_TYPE_8822C)
1653 else if (rtw_fw_feature_ext_check(&rtwdev->fw, FW_FEATURE_EXT_OLD_PAGE_NUM))
1654 len -= RTW_OLD_PROBE_PG_CNT * TX_PAGE_SIZE;
1662 struct rtw_dev *rtwdev = hw->priv;
1665 if (chip->band & RTW_BAND_2G) {
1669 if (chip->ht_supported)
1670 rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1671 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
1674 if (chip->band & RTW_BAND_5G) {
1678 if (chip->ht_supported)
1679 rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1680 if (chip->vht_supported)
1681 rtw_init_vht_cap(rtwdev, &sband->vht_cap);
1682 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
1694 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
1695 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
1703 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
1706 if (rtwdev->hal.txrx_1ss)
1714 const struct rtw_chip_info *chip = rtwdev->chip;
1715 struct rtw_hal *hal = &rtwdev->hal;
1717 if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss)
1720 rtwdev->hal.txrx_1ss = txrx_1ss;
1722 chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false);
1724 chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx,
1725 hal->antenna_rx, false);
1734 (const struct rtw_fw_hdr *)fw->firmware->data;
1736 feature = le32_to_cpu(fw_hdr->feature);
1737 fw->feature = feature & FW_FEATURE_SIG ? feature : 0;
1739 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C &&
1740 RTW_FW_SUIT_VER_CODE(rtwdev->fw) < RTW_FW_VER_CODE(9, 9, 13))
1741 fw->feature_ext |= FW_FEATURE_EXT_OLD_PAGE_NUM;
1748 (const struct rtw_fw_hdr *)fw->firmware->data;
1750 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver);
1751 fw->version = le16_to_cpu(fw_hdr->version);
1752 fw->sub_version = fw_hdr->subversion;
1753 fw->sub_index = fw_hdr->subindex;
1763 (struct rtw_fw_hdr_legacy *)fw->firmware->data;
1765 __DECONST(struct rtw_fw_hdr_legacy *, fw->firmware->data);
1768 fw->h2c_version = 0;
1769 fw->version = le16_to_cpu(legacy->version);
1770 fw->sub_version = legacy->subversion1;
1771 fw->sub_index = legacy->subversion2;
1786 struct rtw_dev *rtwdev = fw->rtwdev;
1788 if (!firmware || !firmware->data) {
1790 complete_all(&fw->completion);
1794 fw->firmware = firmware;
1796 complete_all(&fw->completion);
1799 fw->type == RTW_WOWLAN_FW ? "WOW " : "",
1800 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version);
1811 fw = &rtwdev->wow_fw;
1812 fw_name = rtwdev->chip->wow_fw_name;
1816 fw = &rtwdev->fw;
1817 fw_name = rtwdev->chip->fw_name;
1822 return -ENOENT;
1825 fw->type = type;
1826 fw->rtwdev = rtwdev;
1827 init_completion(&fw->completion);
1829 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev,
1841 const struct rtw_chip_info *chip = rtwdev->chip;
1842 struct rtw_hal *hal = &rtwdev->hal;
1843 struct rtw_efuse *efuse = &rtwdev->efuse;
1847 rtwdev->hci.rpwm_addr = 0x03d9;
1848 rtwdev->hci.cpwm_addr = 0x03da;
1851 rtwdev->hci.rpwm_addr = REG_SDIO_HRPWM1;
1852 rtwdev->hci.cpwm_addr = REG_SDIO_HCPWM1_V2;
1855 rtwdev->hci.rpwm_addr = 0xfe58;
1856 rtwdev->hci.cpwm_addr = 0xfe57;
1860 return -EINVAL;
1863 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1);
1864 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version);
1865 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1;
1866 if (hal->chip_version & BIT_RF_TYPE_ID) {
1867 hal->rf_type = RF_2T2R;
1868 hal->rf_path_num = 2;
1869 hal->antenna_tx = BB_PATH_AB;
1870 hal->antenna_rx = BB_PATH_AB;
1872 hal->rf_type = RF_1T1R;
1873 hal->rf_path_num = 1;
1874 hal->antenna_tx = BB_PATH_A;
1875 hal->antenna_rx = BB_PATH_A;
1877 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num :
1878 hal->rf_path_num;
1880 efuse->physical_size = chip->phy_efuse_size;
1881 efuse->logical_size = chip->log_efuse_size;
1882 efuse->protect_size = chip->ptct_efuse_size;
1885 rtwdev->hal.rcr |= BIT_VHT_DACK;
1887 hal->bfee_sts_cap = 3;
1894 struct rtw_fw_state *fw = &rtwdev->fw;
1911 wait_for_completion(&fw->completion);
1912 if (!fw->firmware) {
1913 ret = -EINVAL;
1935 struct rtw_efuse *efuse = &rtwdev->efuse;
1944 return -EBUSY;
1953 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw);
1954 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature);
1955 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature);
1956 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature);
1957 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature);
1959 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num);
1961 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE ||
1962 efuse->hw_cap.nss > rtwdev->hal.rf_path_num)
1963 efuse->hw_cap.nss = rtwdev->hal.rf_path_num;
1967 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
1968 efuse->hw_cap.ant_num, efuse->hw_cap.nss);
1981 struct rtw_efuse *efuse = &rtwdev->efuse;
1984 mutex_lock(&rtwdev->mutex);
1986 /* power on mac to read efuse */
2003 if (efuse->crystal_cap == 0xff)
2004 efuse->crystal_cap = 0;
2005 if (efuse->pa_type_2g == 0xff)
2006 efuse->pa_type_2g = 0;
2007 if (efuse->pa_type_5g == 0xff)
2008 efuse->pa_type_5g = 0;
2009 if (efuse->lna_type_2g == 0xff)
2010 efuse->lna_type_2g = 0;
2011 if (efuse->lna_type_5g == 0xff)
2012 efuse->lna_type_5g = 0;
2013 if (efuse->channel_plan == 0xff)
2014 efuse->channel_plan = 0x7f;
2015 if (efuse->rf_board_option == 0xff)
2016 efuse->rf_board_option = 0;
2017 if (efuse->bt_setting & BIT(0))
2018 efuse->share_ant = true;
2019 if (efuse->regd == 0xff)
2020 efuse->regd = 0;
2021 if (efuse->tx_bb_swing_setting_2g == 0xff)
2022 efuse->tx_bb_swing_setting_2g = 0;
2023 if (efuse->tx_bb_swing_setting_5g == 0xff)
2024 efuse->tx_bb_swing_setting_5g = 0;
2026 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;
2027 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;
2028 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0;
2029 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0;
2030 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0;
2032 if (!is_valid_ether_addr(efuse->addr)) {
2033 eth_random_addr(efuse->addr);
2034 dev_warn(rtwdev->dev, "efuse MAC invalid, using random\n");
2041 mutex_unlock(&rtwdev->mutex);
2047 struct rtw_hal *hal = &rtwdev->hal;
2051 return -ENODEV;
2053 rtw_phy_setup_phy_cond(rtwdev, hal->pkg_type);
2056 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl);
2057 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl);
2076 rtw_err(rtwdev, "failed to setup chip efuse info\n");
2095 struct rtw_traffic_stats *stats = &rtwdev->stats;
2096 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2099 ewma_tp_init(&stats->tx_ewma_tp);
2100 ewma_tp_init(&stats->rx_ewma_tp);
2103 ewma_evm_init(&dm_info->ewma_evm[i]);
2105 ewma_snr_init(&dm_info->ewma_snr[i]);
2110 const struct rtw_chip_info *chip = rtwdev->chip;
2111 struct rtw_coex *coex = &rtwdev->coex;
2114 INIT_LIST_HEAD(&rtwdev->rsvd_page_list);
2115 INIT_LIST_HEAD(&rtwdev->txqs);
2117 timer_setup(&rtwdev->tx_report.purge_timer,
2119 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
2120 if (!rtwdev->tx_wq) {
2122 return -ENOMEM;
2125 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work);
2126 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work);
2127 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work);
2128 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work);
2129 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work);
2130 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work);
2131 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work);
2132 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work,
2134 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work);
2135 INIT_WORK(&rtwdev->tx_work, rtw_tx_work);
2136 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work);
2137 INIT_WORK(&rtwdev->ips_work, rtw_ips_work);
2138 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work);
2139 INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work);
2140 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work);
2141 skb_queue_head_init(&rtwdev->c2h_queue);
2142 skb_queue_head_init(&rtwdev->coex.queue);
2143 skb_queue_head_init(&rtwdev->tx_report.queue);
2145 spin_lock_init(&rtwdev->txq_lock);
2146 spin_lock_init(&rtwdev->tx_report.q_lock);
2148 mutex_init(&rtwdev->mutex);
2149 mutex_init(&rtwdev->hal.tx_power_mutex);
2151 init_waitqueue_head(&rtwdev->coex.wait);
2152 init_completion(&rtwdev->lps_leave_check);
2153 init_completion(&rtwdev->fw_scan_density);
2155 rtwdev->sec.total_cam_num = 32;
2156 rtwdev->hal.current_channel = 1;
2157 rtwdev->dm_info.fix_rate = U8_MAX;
2158 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map);
2163 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV |
2173 if (chip->wow_fw_name) {
2177 wait_for_completion(&rtwdev->fw.completion);
2178 if (rtwdev->fw.firmware)
2179 release_firmware(rtwdev->fw.firmware);
2191 destroy_workqueue(rtwdev->tx_wq);
2198 struct rtw_fw_state *fw = &rtwdev->fw;
2199 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw;
2205 if (fw->firmware)
2206 release_firmware(fw->firmware);
2208 if (wow_fw->firmware)
2209 release_firmware(wow_fw->firmware);
2211 destroy_workqueue(rtwdev->tx_wq);
2212 timer_delete_sync(&rtwdev->tx_report.purge_timer);
2213 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags);
2214 skb_queue_purge(&rtwdev->tx_report.queue);
2215 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags);
2216 skb_queue_purge(&rtwdev->coex.queue);
2217 skb_queue_purge(&rtwdev->c2h_queue);
2219 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list,
2221 list_del(&rsvd_pkt->build_list);
2225 mutex_destroy(&rtwdev->mutex);
2226 mutex_destroy(&rtwdev->hal.tx_power_mutex);
2232 bool sta_mode_only = rtwdev->hci.type == RTW_HCI_TYPE_SDIO;
2233 struct rtw_hal *hal = &rtwdev->hal;
2237 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz;
2242 hw->extra_tx_headroom = max_tx_headroom;
2243 hw->queues = IEEE80211_NUM_ACS;
2244 hw->txq_data_size = sizeof(struct rtw_txq);
2245 hw->sta_data_size = sizeof(struct rtw_sta_info);
2246 hw->vif_data_size = sizeof(struct rtw_vif);
2262 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
2264 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
2267 hw->wiphy->available_antennas_tx = hal->antenna_tx;
2268 hw->wiphy->available_antennas_rx = hal->antenna_rx;
2270 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
2273 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
2274 hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS;
2275 hw->wiphy->max_scan_ie_len = rtw_get_max_scan_ie_len(rtwdev);
2277 if (!sta_mode_only && rtwdev->chip->id == RTW_CHIP_TYPE_8822C) {
2278 hw->wiphy->iface_combinations = rtw_iface_combs;
2279 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw_iface_combs);
2282 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
2283 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
2284 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
2287 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
2288 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids;
2290 rtw_set_supported_band(hw, rtwdev->chip);
2291 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr);
2293 hw->wiphy->sar_capa = &rtw_sar_capa;
2315 rtwdev->bf_info.bfer_mu_cnt = 0;
2316 rtwdev->bf_info.bfer_su_cnt = 0;
2324 const struct rtw_chip_info *chip = rtwdev->chip;
2338 u8 v1 = rtw_read8(rtwdev, reg1->addr + i);
2339 u8 v2 = rtw_read8(rtwdev, reg2->addr + i);
2341 rtw_write8(rtwdev, reg1->addr + i, v2);
2342 rtw_write8(rtwdev, reg2->addr + i, v1);
2352 v1 = rtw_read32_mask(rtwdev, reg1->addr, reg1->mask);
2353 v2 = rtw_read32_mask(rtwdev, reg2->addr, reg2->mask);
2354 rtw_write32_mask(rtwdev, reg2->addr, reg2->mask, v1);
2355 rtw_write32_mask(rtwdev, reg1->addr, reg1->mask, v2);
2366 struct rtw_dev *rtwdev = iter_data->rtwdev;
2367 struct rtw_vif *rtwvif_target = (struct rtw_vif *)vif->drv_priv;
2368 struct rtw_vif *rtwvif_ap = iter_data->rtwvif_ap;
2371 if (rtwvif_target->port != RTW_PORT_0)
2374 rtw_dbg(rtwdev, RTW_DBG_STATE, "AP port switch from %d -> %d\n",
2375 rtwvif_ap->port, rtwvif_target->port);
2380 reg1 = &rtwvif_ap->conf->net_type;
2381 reg2 = &rtwvif_target->conf->net_type;
2384 reg1 = &rtwvif_ap->conf->mac_addr;
2385 reg2 = &rtwvif_target->conf->mac_addr;
2388 reg1 = &rtwvif_ap->conf->bssid;
2389 reg2 = &rtwvif_target->conf->bssid;
2392 reg1 = &rtwvif_ap->conf->bcn_ctrl;
2393 reg2 = &rtwvif_target->conf->bcn_ctrl;
2396 swap(rtwvif_target->port, rtwvif_ap->port);
2397 swap(rtwvif_target->conf, rtwvif_ap->conf);
2404 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
2407 if (vif->type != NL80211_IFTYPE_AP || rtwvif->port == RTW_PORT_0)
2417 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
2423 if (vif->type != NL80211_IFTYPE_STATION)
2426 if (vif->cfg.assoc || !is_zero_ether_addr(rtwvif->bssid))
2436 return rtwdev->ap_active || sta_active;
2441 if (!rtwdev->ap_active)