Lines Matching refs:value32
16 u32 value32;
29 value32 = rtw_read32(rtwdev, REG_WMAC_TRXPTCL_CTL);
30 value32 &= ~BIT_RFMOD;
33 value32 |= BIT_RFMOD_80M;
36 value32 |= BIT_RFMOD_40M;
42 rtw_write32(rtwdev, REG_WMAC_TRXPTCL_CTL, value32);
47 value32 = rtw_read32(rtwdev, REG_AFE_CTRL1) & ~(BIT_MAC_CLK_SEL);
48 value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL);
49 rtw_write32(rtwdev, REG_AFE_CTRL1, value32);
65 u32 value32;
111 value32 = rtw_read32(rtwdev, REG_PAD_CTRL1);
112 value32 |= BIT_PAPE_WLBT_SEL | BIT_LNAON_WLBT_SEL;
113 rtw_write32(rtwdev, REG_PAD_CTRL1, value32);
115 value32 = rtw_read32(rtwdev, REG_LED_CFG);
116 value32 &= ~(BIT_PAPE_SEL_EN | BIT_LNAON_SEL_EN);
117 rtw_write32(rtwdev, REG_LED_CFG, value32);
119 value32 = rtw_read32(rtwdev, REG_GPIO_MUXCFG);
120 value32 |= BIT_WLRFE_4_5_EN;
121 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value32);
132 value32 = rtw_read32(rtwdev, REG_WLRF1);
133 value32 &= ~BIT_WLRF1_BBRF_EN;
134 rtw_write32(rtwdev, REG_WLRF1, value32);
1299 u32 value32;
1311 value32 = rtw_read32(rtwdev, REG_H2C_HEAD);
1312 value32 = (value32 & 0xFFFC0000) | h2cq_addr;
1313 rtw_write32(rtwdev, REG_H2C_HEAD, value32);
1315 value32 = rtw_read32(rtwdev, REG_H2C_READ_ADDR);
1316 value32 = (value32 & 0xFFFC0000) | h2cq_addr;
1317 rtw_write32(rtwdev, REG_H2C_READ_ADDR, value32);
1319 value32 = rtw_read32(rtwdev, REG_H2C_TAIL);
1320 value32 &= 0xFFFC0000;
1321 value32 |= (h2cq_addr + h2cq_size);
1322 rtw_write32(rtwdev, REG_H2C_TAIL, value32);