Lines Matching refs:rtwdev
12 void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw,
26 rtw_write8(rtwdev, REG_DATA_SC,
29 value32 = rtw_read32(rtwdev, REG_WMAC_TRXPTCL_CTL);
42 rtw_write32(rtwdev, REG_WMAC_TRXPTCL_CTL, value32);
44 if (rtw_chip_wcpu_11n(rtwdev))
47 value32 = rtw_read32(rtwdev, REG_AFE_CTRL1) & ~(BIT_MAC_CLK_SEL);
49 rtw_write32(rtwdev, REG_AFE_CTRL1, value32);
51 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED);
52 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED);
54 value8 = rtw_read8(rtwdev, REG_CCK_CHECK);
58 rtw_write8(rtwdev, REG_CCK_CHECK, value8);
62 static int rtw_mac_pre_system_cfg(struct rtw_dev *rtwdev)
68 rtw_write8(rtwdev, REG_RSV_CTRL, 0);
70 if (rtw_chip_wcpu_11n(rtwdev)) {
71 if (rtw_read32(rtwdev, REG_SYS_CFG1) & BIT_LDO)
72 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, LDO_SEL);
74 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, SPS_SEL);
78 switch (rtw_hci_type(rtwdev)) {
80 rtw_write32_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS);
83 rtw_write8_clr(rtwdev, REG_SDIO_HSUS_CTRL, BIT_HCI_SUS_REQ);
86 if (rtw_read8(rtwdev, REG_SDIO_HSUS_CTRL) & BIT_HCI_RESUME_RDY)
93 rtw_err(rtwdev, "failed to poll REG_SDIO_HSUS_CTRL[1]");
97 if (rtw_sdio_is_sdio30_supported(rtwdev))
98 rtw_write8_set(rtwdev, REG_HCI_OPT_CTRL + 2,
101 rtw_write8_clr(rtwdev, REG_HCI_OPT_CTRL + 2,
111 value32 = rtw_read32(rtwdev, REG_PAD_CTRL1);
113 rtw_write32(rtwdev, REG_PAD_CTRL1, value32);
115 value32 = rtw_read32(rtwdev, REG_LED_CFG);
117 rtw_write32(rtwdev, REG_LED_CFG, value32);
119 value32 = rtw_read32(rtwdev, REG_GPIO_MUXCFG);
121 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value32);
124 value8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
126 rtw_write8(rtwdev, REG_SYS_FUNC_EN, value8);
128 value8 = rtw_read8(rtwdev, REG_RF_CTRL);
130 rtw_write8(rtwdev, REG_RF_CTRL, value8);
132 value32 = rtw_read32(rtwdev, REG_WLRF1);
134 rtw_write32(rtwdev, REG_WLRF1, value32);
139 static bool do_pwr_poll_cmd(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target)
147 rtwdev, addr) == 0;
150 static int rtw_pwr_cmd_polling(struct rtw_dev *rtwdev,
161 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
164 if (rtw_hci_type(rtwdev) != RTW_HCI_TYPE_PCIE)
168 value = rtw_read8(rtwdev, REG_SYS_PW_CTRL);
169 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D)
170 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL);
171 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL);
172 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL);
173 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D)
174 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL);
176 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
180 rtw_err(rtwdev, "failed to poll offset=0x%x mask=0x%x value=0x%x\n",
185 static int rtw_sub_pwr_seq_parser(struct rtw_dev *rtwdev, u8 intf_mask,
205 value = rtw_read8(rtwdev, offset);
208 rtw_write8(rtwdev, offset, value);
211 if (rtw_pwr_cmd_polling(rtwdev, cur_cmd))
230 int rtw_pwr_seq_parser(struct rtw_dev *rtwdev,
240 cut = rtwdev->hal.cut_version;
242 switch (rtw_hci_type(rtwdev)) {
261 ret = rtw_sub_pwr_seq_parser(rtwdev, intf_mask, cut_mask, cmd);
272 static int rtw_mac_power_switch(struct rtw_dev *rtwdev, bool pwr_on)
274 const struct rtw_chip_info *chip = rtwdev->chip;
281 if (rtw_chip_wcpu_11ac(rtwdev)) {
282 rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr);
285 if (rtw_read16(rtwdev, REG_MCUFW_CTRL) == 0xC078) {
287 rtw_write8(rtwdev, rtwdev->hci.rpwm_addr, rpwm);
291 if (rtw_read8(rtwdev, REG_CR) == 0xea)
293 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
294 (rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0)))
302 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) {
303 imr = rtw_read32(rtwdev, REG_SDIO_HIMR);
304 rtw_write32(rtwdev, REG_SDIO_HIMR, 0);
308 clear_bit(RTW_FLAG_POWERON, rtwdev->flags);
311 ret = rtw_pwr_seq_parser(rtwdev, pwr_seq);
313 if (pwr_on && rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) {
317 rtw_write8_clr(rtwdev, REG_SYS_STATUS1 + 1, BIT(0));
320 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO)
321 rtw_write32(rtwdev, REG_SDIO_HIMR, imr);
324 set_bit(RTW_FLAG_POWERON, rtwdev->flags);
329 static int __rtw_mac_init_system_cfg(struct rtw_dev *rtwdev)
331 u8 sys_func_en = rtwdev->chip->sys_func_en;
335 value = rtw_read32(rtwdev, REG_CPU_DMEM_CON);
337 rtw_write32(rtwdev, REG_CPU_DMEM_CON, value);
339 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, sys_func_en);
340 value8 = (rtw_read8(rtwdev, REG_CR_EXT + 3) & 0xF0) | 0x0C;
341 rtw_write8(rtwdev, REG_CR_EXT + 3, value8);
344 tmp = rtw_read32(rtwdev, REG_MCUFW_CTRL);
346 rtw_write32(rtwdev, REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN));
347 value = rtw_read32(rtwdev, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN);
348 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value);
354 static int __rtw_mac_init_system_cfg_legacy(struct rtw_dev *rtwdev)
356 rtw_write8(rtwdev, REG_CR, 0xff);
358 rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0x7f);
361 rtw_write8_set(rtwdev, REG_SYS_CLKR, BIT_WAKEPAD_EN);
362 rtw_write16_clr(rtwdev, REG_GPIO_MUXCFG, BIT_EN_SIC);
364 rtw_write16(rtwdev, REG_CR, 0x2ff);
369 static int rtw_mac_init_system_cfg(struct rtw_dev *rtwdev)
371 if (rtw_chip_wcpu_11n(rtwdev))
372 return __rtw_mac_init_system_cfg_legacy(rtwdev);
374 return __rtw_mac_init_system_cfg(rtwdev);
377 int rtw_mac_power_on(struct rtw_dev *rtwdev)
381 ret = rtw_mac_pre_system_cfg(rtwdev);
385 ret = rtw_mac_power_switch(rtwdev, true);
387 rtw_mac_power_switch(rtwdev, false);
389 ret = rtw_mac_pre_system_cfg(rtwdev);
393 ret = rtw_mac_power_switch(rtwdev, true);
400 ret = rtw_mac_init_system_cfg(rtwdev);
407 rtw_err(rtwdev, "mac power on failed");
411 void rtw_mac_power_off(struct rtw_dev *rtwdev)
413 rtw_mac_power_switch(rtwdev, false);
439 static void wlan_cpu_enable(struct rtw_dev *rtwdev, bool enable)
443 rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF);
446 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
449 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
452 rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF);
458 static void download_firmware_reg_backup(struct rtw_dev *rtwdev,
467 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_TXDMA_PQ_MAP + 1);
470 rtw_write8(rtwdev, REG_TXDMA_PQ_MAP + 1, tmp);
475 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_CR);
482 rtw_write8(rtwdev, REG_CR, tmp);
483 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL);
488 bckp[bckp_idx].val = rtw_read16(rtwdev, REG_FIFOPAGE_INFO_1);
492 bckp[bckp_idx].val = rtw_read32(rtwdev, REG_RQPN_CTRL_2) | BIT_LD_RQPN;
494 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, 0x200);
495 rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val);
497 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO)
498 rtw_read32(rtwdev, REG_SDIO_FREE_TXPG);
501 tmp = rtw_read8(rtwdev, REG_BCN_CTRL);
507 rtw_write8(rtwdev, REG_BCN_CTRL, tmp);
512 static void download_firmware_reset_platform(struct rtw_dev *rtwdev)
514 rtw_write8_clr(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16);
515 rtw_write8_clr(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8);
516 rtw_write8_set(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16);
517 rtw_write8_set(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8);
520 static void download_firmware_reg_restore(struct rtw_dev *rtwdev,
524 rtw_restore_reg(rtwdev, bckp, bckp_num);
529 static int send_firmware_pkt_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
539 ret = rtw_fw_write_data_rsvd_page(rtwdev, pg_addr, buf, size);
545 send_firmware_pkt(struct rtw_dev *rtwdev, u16 pg_addr, const u8 *data, u32 size)
549 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
553 ret = send_firmware_pkt_rsvd_page(rtwdev, pg_addr, data, size);
555 rtw_err(rtwdev, "failed to download rsvd page\n");
561 iddma_enable(struct rtw_dev *rtwdev, u32 src, u32 dst, u32 ctrl)
563 rtw_write32(rtwdev, REG_DDMA_CH0SA, src);
564 rtw_write32(rtwdev, REG_DDMA_CH0DA, dst);
565 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, ctrl);
567 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
573 static int iddma_download_firmware(struct rtw_dev *rtwdev, u32 src, u32 dst,
578 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
585 if (iddma_enable(rtwdev, src, dst, ch0_ctrl))
591 int rtw_ddma_to_fw_fifo(struct rtw_dev *rtwdev, u32 ocp_src, u32 size)
595 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) {
596 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to start ddma\n");
602 if (iddma_enable(rtwdev, ocp_src, OCPBASE_RXBUF_FW_88XX, ch0_ctrl)) {
603 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to complete ddma\n");
611 check_fw_checksum(struct rtw_dev *rtwdev, u32 addr)
615 fw_ctrl = rtw_read8(rtwdev, REG_MCUFW_CTRL);
617 if (rtw_read32(rtwdev, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) {
621 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
625 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
628 rtw_err(rtwdev, "invalid fw checksum\n");
635 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
638 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
645 download_firmware_to_mem(struct rtw_dev *rtwdev, const u8 *data,
648 const struct rtw_chip_info *chip = rtwdev->chip;
662 val = rtw_read32(rtwdev, REG_DDMA_CH0CTRL);
664 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, val);
672 ret = send_firmware_pkt(rtwdev, (u16)(src >> 7),
677 ret = iddma_download_firmware(rtwdev, OCPBASE_TXBUF_88XX +
689 if (!check_fw_checksum(rtwdev, dst))
696 start_download_firmware(struct rtw_dev *rtwdev, const u8 *data, u32 size)
715 val = (u16)(rtw_read16(rtwdev, REG_MCUFW_CTRL) & 0x3800);
717 rtw_write16(rtwdev, REG_MCUFW_CTRL, val);
722 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, dmem_size);
729 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, imem_size);
737 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr,
746 static int download_firmware_validate(struct rtw_dev *rtwdev)
750 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, FW_READY_MASK, FW_READY)) {
751 fw_key = rtw_read32(rtwdev, REG_FW_DBG7) & FW_KEY_MASK;
753 rtw_err(rtwdev, "invalid fw key\n");
760 static void download_firmware_end_flow(struct rtw_dev *rtwdev)
764 rtw_write32(rtwdev, REG_TXDMA_STATUS, BTI_PAGE_OVF);
767 fw_ctrl = rtw_read16(rtwdev, REG_MCUFW_CTRL);
772 rtw_write16(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
775 static int __rtw_download_firmware(struct rtw_dev *rtwdev,
787 if (!ltecoex_read_reg(rtwdev, 0x38, <ecoex_bckp))
790 wlan_cpu_enable(rtwdev, false);
792 download_firmware_reg_backup(rtwdev, bckp);
793 download_firmware_reset_platform(rtwdev);
795 ret = start_download_firmware(rtwdev, data, size);
799 download_firmware_reg_restore(rtwdev, bckp, DLFW_RESTORE_REG_NUM);
801 download_firmware_end_flow(rtwdev);
803 wlan_cpu_enable(rtwdev, true);
805 if (!ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp)) {
810 ret = download_firmware_validate(rtwdev);
815 rtw_hci_setup(rtwdev);
817 rtwdev->h2c.last_box_num = 0;
818 rtwdev->h2c.seq = 0;
820 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
826 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
827 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
832 static void en_download_firmware_legacy(struct rtw_dev *rtwdev, bool en)
837 wlan_cpu_enable(rtwdev, false);
838 wlan_cpu_enable(rtwdev, true);
840 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
843 if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_MCUFWDL_EN)
845 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
848 rtw_err(rtwdev, "failed to check fw download ready\n");
850 rtw_write32_clr(rtwdev, REG_MCUFW_CTRL, BIT_ROM_DLEN);
852 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
857 write_firmware_page(struct rtw_dev *rtwdev, u32 page, const u8 *data, u32 size)
870 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
873 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32);
876 rtw_write32(rtwdev, write_addr, le32_to_cpu(*ptr));
884 rtw_write32(rtwdev, write_addr, le32_to_cpu(remain_data));
889 download_firmware_legacy(struct rtw_dev *rtwdev, const u8 *data, u32 size)
901 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT);
904 write_firmware_page(rtwdev, page, data, DLFW_PAGE_SIZE_LEGACY);
908 write_firmware_page(rtwdev, page, data, last_page_size);
910 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT, 1)) {
911 rtw_err(rtwdev, "failed to check download firmware report\n");
918 static int download_firmware_validate_legacy(struct rtw_dev *rtwdev)
923 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
926 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32);
928 wlan_cpu_enable(rtwdev, false);
929 wlan_cpu_enable(rtwdev, true);
932 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
938 rtw_err(rtwdev, "failed to validate firmware\n");
942 static int __rtw_download_firmware_legacy(struct rtw_dev *rtwdev,
948 if (rtwdev->chip->id == RTW_CHIP_TYPE_8703B &&
949 rtw_read8_mask(rtwdev, REG_MCUFW_CTRL, BIT_RAM_DL_SEL)) {
950 rtw_write8(rtwdev, REG_MCUFW_CTRL, 0x00);
953 en_download_firmware_legacy(rtwdev, true);
954 ret = download_firmware_legacy(rtwdev, fw->firmware->data, fw->firmware->size);
955 en_download_firmware_legacy(rtwdev, false);
959 ret = download_firmware_validate_legacy(rtwdev);
964 rtw_hci_setup(rtwdev);
966 rtwdev->h2c.last_box_num = 0;
967 rtwdev->h2c.seq = 0;
969 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
976 int _rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw)
978 if (rtw_chip_wcpu_11n(rtwdev))
979 return __rtw_download_firmware_legacy(rtwdev, fw);
981 return __rtw_download_firmware(rtwdev, fw);
984 int rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw)
988 ret = _rtw_download_firmware(rtwdev, fw);
992 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE &&
993 rtwdev->chip->id == RTW_CHIP_TYPE_8821C)
994 rtw_fw_set_recover_bt_device(rtwdev);
1000 static u32 get_priority_queues(struct rtw_dev *rtwdev, u32 queues)
1002 const struct rtw_rqpn *rqpn = rtwdev->fifo.rqpn;
1017 static void __rtw_mac_flush_prio_queue(struct rtw_dev *rtwdev,
1020 const struct rtw_chip_info *chip = rtwdev->chip;
1034 rsvd_page = wsize ? rtw_read16(rtwdev, addr->rsvd) :
1035 rtw_read8(rtwdev, addr->rsvd);
1036 avail_page = wsize ? rtw_read16(rtwdev, addr->avail) :
1037 rtw_read8(rtwdev, addr->avail);
1051 rtw_dbg(rtwdev, RTW_DBG_UNEXP,
1055 static void rtw_mac_flush_prio_queues(struct rtw_dev *rtwdev,
1062 __rtw_mac_flush_prio_queue(rtwdev, q, drop);
1065 void rtw_mac_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop)
1073 if (queues == BIT(rtwdev->hw->queues) - 1 || !rtwdev->fifo.rqpn)
1076 prio_queues = get_priority_queues(rtwdev, queues);
1078 rtw_mac_flush_prio_queues(rtwdev, prio_queues, drop);
1081 static int txdma_queue_mapping(struct rtw_dev *rtwdev)
1083 const struct rtw_chip_info *chip = rtwdev->chip;
1087 switch (rtw_hci_type(rtwdev)) {
1092 if (rtwdev->hci.bulkout_num == 2)
1094 else if (rtwdev->hci.bulkout_num == 3)
1096 else if (rtwdev->hci.bulkout_num == 4)
1108 rtwdev->fifo.rqpn = rqpn;
1115 rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map);
1117 rtw_write8(rtwdev, REG_CR, 0);
1118 rtw_write8(rtwdev, REG_CR, MAC_TRX_ENABLE);
1119 if (rtw_chip_wcpu_11ac(rtwdev))
1120 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL);
1122 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) {
1123 rtw_read32(rtwdev, REG_SDIO_FREE_TXPG);
1124 rtw_write32(rtwdev, REG_SDIO_TX_CTRL, 0);
1125 } else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) {
1126 rtw_write8_set(rtwdev, REG_TXDMA_PQ_MAP, BIT_RXDMA_ARBBW_EN);
1132 int rtw_set_trx_fifo_info(struct rtw_dev *rtwdev)
1134 const struct rtw_chip_info *chip = rtwdev->chip;
1135 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1142 if (rtw_chip_wcpu_11n(rtwdev))
1160 if (rtw_chip_wcpu_11ac(rtwdev)) {
1178 rtw_err(rtwdev, "wrong rsvd driver address\n");
1186 static int __priority_queue_cfg(struct rtw_dev *rtwdev,
1190 const struct rtw_chip_info *chip = rtwdev->chip;
1191 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1193 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num);
1194 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num);
1195 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num);
1196 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num);
1197 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_5, pubq_num);
1198 rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN);
1200 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary);
1201 rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL + 2, BIT_EN_WR_FREE_TAIL >> 16);
1203 rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary);
1204 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary);
1205 rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary);
1206 rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1);
1208 if (rtwdev->hci.type == RTW_HCI_TYPE_USB) {
1209 rtw_write8_mask(rtwdev, REG_AUTO_LLT_V1, BIT_MASK_BLK_DESC_NUM,
1212 rtw_write8(rtwdev, REG_AUTO_LLT_V1 + 3, chip->usb_tx_agg_desc_num);
1213 rtw_write8_set(rtwdev, REG_TXDMA_OFFSET_CHK + 1, BIT(1));
1216 rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1);
1218 if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0))
1221 rtw_write8(rtwdev, REG_CR + 3, 0);
1226 static int __priority_queue_cfg_legacy(struct rtw_dev *rtwdev,
1230 const struct rtw_chip_info *chip = rtwdev->chip;
1231 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1235 rtw_write32(rtwdev, REG_RQPN_NPQ, val32);
1237 rtw_write32(rtwdev, REG_RQPN, val32);
1239 rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary);
1240 rtw_write16(rtwdev, REG_TRXFF_BNDY + 2, chip->rxff_size - REPORT_BUF - 1);
1241 rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary);
1242 rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary);
1243 rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary);
1244 rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary);
1246 rtw_write32_set(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT);
1248 if (!check_hw_ready(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT, 0))
1254 static int priority_queue_cfg(struct rtw_dev *rtwdev)
1256 const struct rtw_chip_info *chip = rtwdev->chip;
1257 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1262 ret = rtw_set_trx_fifo_info(rtwdev);
1266 switch (rtw_hci_type(rtwdev)) {
1271 if (rtwdev->hci.bulkout_num == 2)
1273 else if (rtwdev->hci.bulkout_num == 3)
1275 else if (rtwdev->hci.bulkout_num == 4)
1289 if (rtw_chip_wcpu_11n(rtwdev))
1290 return __priority_queue_cfg_legacy(rtwdev, pg_tbl, pubq_num);
1292 return __priority_queue_cfg(rtwdev, pg_tbl, pubq_num);
1295 static int init_h2c(struct rtw_dev *rtwdev)
1297 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1305 if (rtw_chip_wcpu_11n(rtwdev))
1311 value32 = rtw_read32(rtwdev, REG_H2C_HEAD);
1313 rtw_write32(rtwdev, REG_H2C_HEAD, value32);
1315 value32 = rtw_read32(rtwdev, REG_H2C_READ_ADDR);
1317 rtw_write32(rtwdev, REG_H2C_READ_ADDR, value32);
1319 value32 = rtw_read32(rtwdev, REG_H2C_TAIL);
1322 rtw_write32(rtwdev, REG_H2C_TAIL, value32);
1324 value8 = rtw_read8(rtwdev, REG_H2C_INFO);
1326 rtw_write8(rtwdev, REG_H2C_INFO, value8);
1328 value8 = rtw_read8(rtwdev, REG_H2C_INFO);
1330 rtw_write8(rtwdev, REG_H2C_INFO, value8);
1332 value8 = rtw_read8(rtwdev, REG_TXDMA_OFFSET_CHK + 1);
1334 rtw_write8(rtwdev, REG_TXDMA_OFFSET_CHK + 1, value8);
1336 wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF;
1337 rp = rtw_read32(rtwdev, REG_H2C_PKT_READADDR) & 0x3FFFF;
1341 rtw_err(rtwdev, "H2C queue mismatch\n");
1348 static int rtw_init_trx_cfg(struct rtw_dev *rtwdev)
1352 ret = txdma_queue_mapping(rtwdev);
1356 ret = priority_queue_cfg(rtwdev);
1360 ret = init_h2c(rtwdev);
1367 static int rtw_drv_info_cfg(struct rtw_dev *rtwdev)
1371 rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE);
1372 if (rtw_chip_wcpu_11ac(rtwdev)) {
1373 value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1);
1377 rtw_write8(rtwdev, REG_TRXFF_BNDY + 1, value8);
1379 rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS);
1380 rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9));
1385 int rtw_mac_init(struct rtw_dev *rtwdev)
1387 const struct rtw_chip_info *chip = rtwdev->chip;
1390 ret = rtw_init_trx_cfg(rtwdev);
1394 ret = chip->ops->mac_init(rtwdev);
1398 ret = rtw_drv_info_cfg(rtwdev);
1402 rtw_hci_interface_cfg(rtwdev);