Lines Matching +full:0 +full:x3ffff
15 u8 txsc40 = 0, txsc20 = 0;
68 rtw_write8(rtwdev, REG_RSV_CTRL, 0);
75 return 0;
85 for (retry = 0; retry < RTW_PWR_POLLING_CNT; retry++) {
136 return 0;
147 rtwdev, addr) == 0;
162 return 0;
177 return 0;
180 rtw_err(rtwdev, "failed to poll offset=0x%x mask=0x%x value=0x%x\n",
227 return 0;
236 u32 idx = 0;
268 return 0;
276 u32 imr = 0;
285 if (rtw_read16(rtwdev, REG_MCUFW_CTRL) == 0xC078) {
291 if (rtw_read8(rtwdev, REG_CR) == 0xea)
294 (rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0)))
304 rtw_write32(rtwdev, REG_SDIO_HIMR, 0);
317 rtw_write8_clr(rtwdev, REG_SYS_STATUS1 + 1, BIT(0));
340 value8 = (rtw_read8(rtwdev, REG_CR_EXT + 3) & 0xF0) | 0x0C;
351 return 0;
356 rtw_write8(rtwdev, REG_CR, 0xff);
358 rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0x7f);
364 rtw_write16(rtwdev, REG_CR, 0x2ff);
366 return 0;
379 int ret = 0;
404 return 0;
427 le32_to_cpu(fw_hdr->emem_size) : 0;
431 emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0;
462 u8 bckp_idx = 0;
494 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, 0x200);
567 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
570 return 0;
578 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
588 return 0;
595 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) {
607 return 0;
654 u32 max_size = 0x1000;
658 mem_offset = 0;
684 first_part = 0;
692 return 0;
710 le32_to_cpu(fw_hdr->emem_size) : 0;
713 emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0;
715 val = (u16)(rtw_read16(rtwdev, REG_MCUFW_CTRL) & 0x3800);
722 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, dmem_size);
729 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, imem_size);
737 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr,
743 return 0;
757 return 0;
787 if (!ltecoex_read_reg(rtwdev, 0x38, <ecoex_bckp))
805 if (!ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp)) {
817 rtwdev->h2c.last_box_num = 0;
818 rtwdev->h2c.seq = 0;
822 return 0;
842 for (try = 0; try < 10; try++) {
865 __le32 remain_data = 0;
875 for (block = 0; block < block_nr; block++) {
903 for (page = 0; page < total_page; page++) {
915 return 0;
931 for (try = 0; try < 10; try++) {
934 return 0;
945 int ret = 0;
950 rtw_write8(rtwdev, REG_MCUFW_CTRL, 0x00);
966 rtwdev->h2c.last_box_num = 0;
967 rtwdev->h2c.seq = 0;
996 return 0;
1003 u32 prio_queues = 0;
1033 for (i = 0; i < 5; i++) {
1060 for (q = 0; q < RTW_DMA_MAPPING_MAX; q++)
1067 u32 prio_queues = 0;
1085 u16 txdma_pq_map = 0;
1102 rqpn = &chip->rqpn_table[0];
1117 rtw_write8(rtwdev, REG_CR, 0);
1124 rtw_write32(rtwdev, REG_SDIO_TX_CTRL, 0);
1129 return 0;
1182 return 0;
1218 if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0))
1221 rtw_write8(rtwdev, REG_CR + 3, 0);
1223 return 0;
1248 if (!check_hw_ready(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT, 0))
1251 return 0;
1281 pg_tbl = &chip->page_table[0];
1306 return 0;
1312 value32 = (value32 & 0xFFFC0000) | h2cq_addr;
1316 value32 = (value32 & 0xFFFC0000) | h2cq_addr;
1320 value32 &= 0xFFFC0000;
1325 value8 = (u8)((value8 & 0xFC) | 0x01);
1329 value8 = (u8)((value8 & 0xFB) | 0x04);
1333 value8 = (u8)((value8 & 0x7f) | 0x80);
1336 wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF;
1337 rp = rtw_read32(rtwdev, REG_H2C_PKT_READADDR) & 0x3FFFF;
1345 return 0;
1364 return 0;
1374 value8 &= 0xF0;
1375 /* For rxdesc len = 0 issue */
1376 value8 |= 0xF;
1382 return 0;
1404 return 0;