Lines Matching +full:0 +full:xf0ffffff
75 rtw_write8_set(rtwdev, REG_LIFETIME_EN, 0xf);
76 rtw_write16(rtwdev, REG_RETRY_LIMIT, 0x0808);
79 rtw_write32(rtwdev, REG_DARFRC, 0x1000000);
80 rtw_write32(rtwdev, REG_DARFRCH, 0x4030201);
83 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, 0xf);
91 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, 0x20);
132 COEX_RSSI_HIGH(coex_dm->bt_rssi_state[0]))
136 bt_rssi = coex_dm->bt_rssi_state[0];
152 u8 para[6] = {0};
154 para[0] = COEX_H2C69_WL_LEAKAP;
160 coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND] = 0;
163 rtw_fw_bt_wifi_control(rtwdev, para[0], ¶[1]);
177 "[BTCoex], set h2c 0x69 opcode 12 to turn off 5ms WL slot extend!!\n");
187 coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND] = 0;
195 "[BTCoex], set h2c 0x69 opcode 12 to turn off 5ms WL slot extend!!\n");
200 "[BTCoex], set h2c 0x69 opcode 12 to turn on 5ms WL slot extend!!\n");
275 coex_stat->cnt_wl[COEX_CNT_WL_NOISY0] = 0;
276 coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] = 0;
283 coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] = 0;
284 coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] = 0;
291 coex_stat->cnt_wl[COEX_CNT_WL_NOISY0] = 0;
292 coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] = 0;
301 coex_stat->wl_noisy_level = 0;
312 u8 para[2] = {0};
321 para[0] = COEX_H2C69_TDMA_SLOT;
328 } else if (tbtt_interval < 80 && tbtt_interval > 0) {
330 if (100 % tbtt_interval != 0)
345 rtw_fw_bt_wifi_control(rtwdev, para[0], ¶[1]);
347 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], %s(): h2c_0x69 = 0x%x\n",
371 u16 val = 0x2;
406 return 0;
417 u8 cnt = 0;
422 coex_stat->bt_iqk_state != 0xff) {
445 coex_stat->bt_iqk_state = 0xff;
510 coex_stat->bt_ble_scan_type = 0;
511 coex_dm->cur_bt_lna_lvl = 0;
566 for (i = 0; i < 4; i++) {
621 if (payload[0] != COEX_RESP_ACK_BY_WL_FW) {
658 struct rtw_coex_info_req req = {0};
676 struct rtw_coex_info_req req = {0};
718 for (i = 0; i < COEX_RSSI_STEP; i++) {
728 coex_stat->cnt_bt[COEX_CNT_BT_INFOUPDATE] % 3 == 0) {
733 if ((coex_stat->bt_ble_scan_type & 0x1) == 0x1)
740 coex_stat->bt_profile_num = 0;
812 u8 link = 0;
813 u8 center_chan = 0;
822 if (center_chan == 0 ||
825 link = 0;
826 center_chan = 0;
827 bw = 0;
829 link = 0x1;
836 for (i = 0; i < chip->afh_5g_num; i++) {
838 link = 0x3;
846 coex_dm->wl_ch_info[0] = link;
852 "[BTCoex], %s: para[0:2] = 0x%x 0x%x 0x%x\n", __func__, link,
895 u8 offset = 0;
912 return 0;
953 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, 0xc000, state);
954 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, 0x0c00, state);
959 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, 0x3000, state);
960 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, 0x0300, state);
985 u8 h2c_para[6] = {0};
986 u32 table_wl = 0x5a5a5a5a;
988 h2c_para[0] = COEX_H2C69_TOGGLE_TABLE_A;
990 h2c_para[1] = 0x1;
1001 h2c_para[2] = (u8)u32_get_bits(table_wl, GENMASK(7, 0));
1006 rtw_fw_bt_wifi_control(rtwdev, h2c_para[0], &h2c_para[1]);
1010 __func__, h2c_para[0], h2c_para[1], h2c_para[2],
1014 #define COEX_WL_SLOT_TOGLLE 0x5a5a5aaa
1020 u8 cur_h2c_para[6] = {0};
1023 cur_h2c_para[0] = COEX_H2C69_TOGGLE_TABLE_B;
1025 cur_h2c_para[2] = (u8)u32_get_bits(table, GENMASK(7, 0));
1032 for (i = 0; i <= 5; i++)
1035 rtw_fw_bt_wifi_control(rtwdev, cur_h2c_para[0], &cur_h2c_para[1]);
1039 __func__, cur_h2c_para[0], cur_h2c_para[1], cur_h2c_para[2],
1046 #define DEF_BRK_TABLE_VAL 0xf0ffffff
1061 "[BTCoex], %s(): 0x6c0 = %x, 0x6c4 = %x\n", __func__, table0,
1108 u8 lps_mode = 0x0;
1123 rtw_fw_coex_tdma_type(rtwdev, 0, 0, 0, 0, 0);
1155 rtw_coex_power_save_state(rtwdev, ps_type, 0x0, 0x0);
1159 "[BTCoex], %s(): Force LPS (byte1 = 0x%x)\n", __func__,
1166 rtw_coex_power_save_state(rtwdev, ps_type, 0x50, 0x4);
1169 "[BTCoex], %s(): native power save (byte1 = 0x%x)\n",
1173 rtw_coex_power_save_state(rtwdev, ps_type, 0x0, 0x0);
1176 coex_dm->ps_tdma_para[0] = byte1;
1209 type = (u8)(tcase & 0xff);
1211 turn_on = (type == 0 || type == 100) ? false : true;
1238 chip->tdma_sant[type].para[0],
1247 chip->tdma_nsant[n].para[0],
1277 "[BTCoex], coex_stat->bt_disabled = 0x%x\n",
1464 u8 profile_map = 0;
1506 if (coex_stat->bt_hid_pair_num > 0)
1533 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1538 tdma_case = 0;
1556 u8 level = 0;
1573 if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[0]))
1603 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1628 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1633 tdma_case = 0;
1651 u32 slot_type = 0;
1656 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1670 tdma_case = 0;
1692 u8 table_case = 0xff, tdma_case = 0xff;
1695 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1702 table_case = 0;
1703 tdma_case = 0;
1710 if (table_case != 0xff && tdma_case != 0xff) {
1738 } else if ((coex_stat->bt_ble_scan_type & 0x2) &&
1761 u32 slot_type = 0;
1765 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1778 if (coex_stat->bt_profile_num > 0)
1789 if (coex_stat->bt_profile_num == 0) {
1811 tdma_case = 0;
1820 if (coex_stat->bt_profile_num > 0)
1872 table_case = 0;
1878 tdma_case = 0;
1894 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1911 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1939 u32 slot_type = 0;
1944 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2023 u32 slot_type = 0;
2028 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2034 if (coex_stat->wl_gl_busy && coex_stat->wl_noisy_level == 0)
2069 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2074 tdma_case = 0;
2106 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2110 if (coex_stat->wl_gl_busy && coex_stat->wl_noisy_level == 0)
2140 u8 table_case, tdma_case, interval = 0;
2141 u32 slot_type = 0;
2148 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2202 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2218 coex_stat->wl_noisy_level == 0)
2241 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2258 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2292 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2327 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2336 table_case = 0;
2337 tdma_case = 0;
2356 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2361 tdma_case = 0;
2390 tdma_case = 0;
2404 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2418 u32 slot_type = 0;
2422 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2459 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2464 tdma_case = 0;
2668 memset(coex_dm, 0, sizeof(*coex_dm));
2669 memset(coex_stat, 0, sizeof(*coex_stat));
2671 for (i = 0; i < COEX_CNT_WL_MAX; i++)
2672 coex_stat->cnt_wl[i] = 0;
2674 for (i = 0; i < COEX_CNT_BT_MAX; i++)
2675 coex_stat->cnt_bt[i] = 0;
2677 for (i = 0; i < ARRAY_SIZE(coex_dm->bt_rssi_state); i++)
2680 for (i = 0; i < ARRAY_SIZE(coex_dm->wl_rssi_state); i++)
2697 coex_stat->kt_ver = u8_get_bits(rtw_read8(rtwdev, 0xf1), GENMASK(7, 4));
2739 rtw_coex_tdma(rtwdev, true, 0);
2753 /* enable BB, we can write 0x948 */
2765 rtw_write8(rtwdev, 0xff1a, 0x0);
2995 rtw_coex_set_wl_pri_mask(rtwdev, COEX_WLPRI_RX_CCK, 0);
3009 u8 i, rsp_source = 0, type;
3012 rsp_source = buf[0] & 0xf;
3019 if (coex_stat->bt_iqk_state == 0)
3025 "[BTCoex], BT IQK by bt_info, data0 = 0x%02x\n",
3033 "[BTCoex], BT Scoreboard change notify by WL FW c2h, 0xaa = 0x%02x, 0xab = 0x%02x\n",
3046 "[BTCoex], H2C 0x60 content replied by WL FW: H2C_0x60 = [%02x %02x %02x %02x %02x]\n",
3084 buf[0], length, buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]);
3086 for (i = 0; i < COEX_BTINFO_LENGTH; i++)
3108 /* 0xff means BT is under WHCK test */
3109 coex_stat->bt_whck_test = (coex_stat->bt_info_lb2 == 0xff);
3127 if (coex_stat->bt_info_hb1 & BIT(0)) {
3134 } else if (coex_stat->bt_info_hb1 & BIT(0)) {
3143 if (coex_stat->bt_info_hb1 & BIT(0)) {
3159 coex_stat->cnt_bt[COEX_CNT_BT_RETRY] = coex_stat->bt_info_lb3 & 0xf;
3181 coex_stat->bt_rssi = 0;
3212 /* for multi_link = 0 but bt pkt remain exist */
3242 coex_stat->bt_opp_exist = ((coex_stat->bt_info_hb2 & BIT(0)) == BIT(0));
3248 coex_stat->bt_hid_slot = (coex_stat->bt_info_hb2 & 0x30) >> 4;
3249 coex_stat->bt_hid_pair_num = (coex_stat->bt_info_hb2 & 0xc0) >> 6;
3250 if (coex_stat->bt_hid_pair_num > 0 && coex_stat->bt_hid_slot >= 2)
3252 else if (coex_stat->bt_hid_pair_num == 0 || coex_stat->bt_hid_slot == 1)
3255 if ((coex_stat->bt_info_lb2 & 0x49) == 0x49)
3256 coex_stat->bt_a2dp_bitpool = (coex_stat->bt_info_hb3 & 0x7f);
3258 coex_stat->bt_a2dp_bitpool = 0;
3266 #define COEX_BT_HIDINFO_MTK 0x46
3267 static const u8 coex_bt_hidinfo_ps[] = {0x57, 0x69, 0x72};
3268 static const u8 coex_bt_hidinfo_xb[] = {0x58, 0x62, 0x6f};
3278 u8 sub_id = buf[2], gamehid_cnt = 0, handle, i;
3286 "[BTCoex], HID info notify, sub_id = 0x%x\n", sub_id);
3295 memset(&coex_stat->hid_info, 0, sizeof(coex_stat->hid_info));
3296 for (i = 0; i < COEX_BT_HIDINFO_HANDLE_NUM; i++) {
3299 hl->handle[i] != 0)
3306 for (i = 0; i < COEX_BT_HIDINFO_HANDLE_NUM; i++) {
3318 for (i = 0; i < COEX_BT_HIDINFO_HANDLE_NUM; i++) {
3323 handle == 0 || handle >= COEX_BT_BLE_HANDLE_THRS) {
3331 COEX_BT_HIDINFO_NAME)) == 0)
3335 COEX_BT_HIDINFO_NAME)) == 0)
3346 if (gamehid_cnt > 0)
3379 rtw_fw_coex_query_hid_info(rtwdev, COEX_BT_HIDINFO_LIST, 0);
3381 for (i = 0; i < COEX_BT_HIDINFO_HANDLE_NUM; i++) {
3385 if (handle == 0 || handle == COEX_BT_HIDINFO_NOTCON ||
3408 if (buf[0] != 0x08)
3586 u8 ans = 0xFF;
3597 for (i = 0; i < n; i++) {
3622 u8 ans = 0xFF;
3633 for (i = 0; i < n; i++) {
3635 for (j = 0; j < 5; j++) {
3661 const char *sep = n == 0 ? "" : "/ ";
3665 if (INFO_SIZE - n <= 0)
3666 return 0;
3684 return 0;
3690 if (ffs == 0 && fls == max_fls)
3705 const char *sep = n == 0 ? "" : "/ ";
3708 if (INFO_SIZE - n <= 0)
3709 return 0;
3728 return 0;
3741 int n_addr = 0;
3743 int n_val = 0;
3746 for (i = 0; i < chip->coex_info_hw_regs_num; i++) {
3754 n_addr = 0;
3755 n_val = 0;
3759 if (n_addr != 0 && n_val != 0)
3766 struct rtw_coex_info_req req = {0};
3774 req.para2 = le16_get_bits(le_addr, GENMASK(7, 0));
3778 *val = 0xeaea;
3792 struct rtw_coex_info_req req = {0};
3811 struct rtw_coex_info_req req = {0};
3830 struct rtw_coex_info_req req = {0};
3936 sys_lte = rtw_read8(rtwdev, 0x73);
3937 lte_coex = rtw_coex_read_indirect_reg(rtwdev, 0x38);
3938 bt_coex = rtw_coex_read_indirect_reg(rtwdev, 0x54);
3948 rtw_coex_get_bt_reg(rtwdev, 3, 0xae, &coex_stat->bt_reg_vendor_ae);
3949 rtw_coex_get_bt_reg(rtwdev, 3, 0xac, &coex_stat->bt_reg_vendor_ac);
3951 if (coex_stat->patch_ver != 0)
3977 seq_printf(m, "%-40s = %08x/ 0x%02x/ 0x%08x %s\n",
3989 seq_printf(m, "%-40s = %u.%u/ 0x%x/ 0x%x/ %c\n",
3996 coex_dm->wl_ch_info[0], coex_dm->wl_ch_info[1],
4024 seq_printf(m, "%-40s = %u/ %u/ %u/ 0x%08x\n",
4036 seq_printf(m, "%-40s = 0x%04x/ 0x%04x/ 0x%04x/ 0x%04x\n",
4037 "0xae/ 0xac/ score board (W->B)/ (B->W)",
4045 for (i = 0; i < COEX_BTINFO_SRC_BT_IQK; i++)
4077 &coex_dm->fw_tdma_para[0]));
4091 seq_printf(m, "%-40s = %d(%d)/ 0x%08x/ 0x%08x/ 0x%08x\n",
4092 "Table/ 0x6c0/ 0x6c4/ 0x6c8",
4096 seq_printf(m, "%-40s = 0x%08x/ 0x%08x/ %d/ reason (%s)\n",
4097 "0x778/ 0x6cc/ Run Count/ Reason",