Lines Matching refs:mt76_wr
131 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x2)); in __mt7996_dma_prefetch()
132 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x2)); in __mt7996_dma_prefetch()
133 mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x8)); in __mt7996_dma_prefetch()
134 mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0x8)); in __mt7996_dma_prefetch()
135 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0x2)); in __mt7996_dma_prefetch()
136 mt76_wr(dev, MT_TXQ_EXT_CTRL(2) + ofs, PREFETCH(0x8)); in __mt7996_dma_prefetch()
137 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x2)); in __mt7996_dma_prefetch()
138 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x2)); in __mt7996_dma_prefetch()
139 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(0x2)); in __mt7996_dma_prefetch()
142 mt76_wr(dev, MT_RXQ_BAND1_CTRL(queue) + ofs, PREFETCH(0x2)); in __mt7996_dma_prefetch()
144 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x10)); in __mt7996_dma_prefetch()
147 mt76_wr(dev, MT_RXQ_BAND1_CTRL(queue) + ofs, PREFETCH(0x10)); in __mt7996_dma_prefetch()
150 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_RRO_BAND0) + ofs, in __mt7996_dma_prefetch()
152 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_RRO_BAND2) + ofs, in __mt7996_dma_prefetch()
154 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MSDU_PAGE_BAND0) + ofs, in __mt7996_dma_prefetch()
156 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MSDU_PAGE_BAND1) + ofs, in __mt7996_dma_prefetch()
158 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MSDU_PAGE_BAND2) + ofs, in __mt7996_dma_prefetch()
160 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_TXFREE_BAND0) + ofs, in __mt7996_dma_prefetch()
162 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_TXFREE_BAND2) + ofs, in __mt7996_dma_prefetch()
271 mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask); in mt7996_dma_start()
289 mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0); in mt7996_dma_enable()
291 mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR + hif1_ofs, ~0); in mt7996_dma_enable()
294 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0); in mt7996_dma_enable()
295 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1, 0); in mt7996_dma_enable()
296 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2, 0); in mt7996_dma_enable()
299 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0 + hif1_ofs, 0); in mt7996_dma_enable()
300 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1 + hif1_ofs, 0); in mt7996_dma_enable()
301 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2 + hif1_ofs, 0); in mt7996_dma_enable()
332 mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_45_TH, 0xc000c); in mt7996_dma_enable()
333 mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_67_TH, 0x10008); in mt7996_dma_enable()
334 mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_89_TH, 0x10008); in mt7996_dma_enable()
335 mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_RRO_TH, 0x20); in mt7996_dma_enable()
356 mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_45_TH + hif1_ofs, 0xc000c); in mt7996_dma_enable()
357 mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_67_TH + hif1_ofs, 0x10008); in mt7996_dma_enable()
358 mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_89_TH + hif1_ofs, 0x10008); in mt7996_dma_enable()
359 mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_RRO_TH + hif1_ofs, 0x20); in mt7996_dma_enable()
437 mt76_wr(dev, MT_INT_MASK_CSR, irq_mask); in mt7996_dma_rro_init()