20 	mt76_wr(dev, dev->irq_map->host_irq_enable, 0);  in mt792x_irq_handler()
35 	u32 intr, mask = 0;  in mt792x_irq_tasklet()
37 	mt76_wr(dev, irq_map->host_irq_enable, 0);  in mt792x_irq_tasklet()
63 	mt76_set_irq_mask(&dev->mt76, irq_map->host_irq_enable, mask, 0);  in mt792x_irq_tasklet()
98 		mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0000, 0x4));  in mt792x_dma_prefetch()
99 		mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL, PREFETCH(0x0040, 0x4));  in mt792x_dma_prefetch()
100 		mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x0080, 0x4));  in mt792x_dma_prefetch()
101 		mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x00c0, 0x4));  in mt792x_dma_prefetch()
103 		mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x0100, 0x10));  in mt792x_dma_prefetch()
104 		mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x0200, 0x10));  in mt792x_dma_prefetch()
105 		mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x0300, 0x10));  in mt792x_dma_prefetch()
106 		mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x0400, 0x10));  in mt792x_dma_prefetch()
107 		mt76_wr(dev, MT_WFDMA0_TX_RING15_EXT_CTRL, PREFETCH(0x0500, 0x4));  in mt792x_dma_prefetch()
108 		mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x0540, 0x4));  in mt792x_dma_prefetch()
111 		mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4));  in mt792x_dma_prefetch()
112 		mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x40, 0x4));  in mt792x_dma_prefetch()
113 		mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x80, 0x4));  in mt792x_dma_prefetch()
114 		mt76_wr(dev, MT_WFDMA0_RX_RING4_EXT_CTRL, PREFETCH(0xc0, 0x4));  in mt792x_dma_prefetch()
115 		mt76_wr(dev, MT_WFDMA0_RX_RING5_EXT_CTRL, PREFETCH(0x100, 0x4));  in mt792x_dma_prefetch()
117 		mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x140, 0x4));  in mt792x_dma_prefetch()
118 		mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x180, 0x4));  in mt792x_dma_prefetch()
119 		mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x1c0, 0x4));  in mt792x_dma_prefetch()
120 		mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x200, 0x4));  in mt792x_dma_prefetch()
121 		mt76_wr(dev, MT_WFDMA0_TX_RING4_EXT_CTRL, PREFETCH(0x240, 0x4));  in mt792x_dma_prefetch()
122 		mt76_wr(dev, MT_WFDMA0_TX_RING5_EXT_CTRL, PREFETCH(0x280, 0x4));  in mt792x_dma_prefetch()
123 		mt76_wr(dev, MT_WFDMA0_TX_RING6_EXT_CTRL, PREFETCH(0x2c0, 0x4));  in mt792x_dma_prefetch()
124 		mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x340, 0x4));  in mt792x_dma_prefetch()
125 		mt76_wr(dev, MT_WFDMA0_TX_RING17_EXT_CTRL, PREFETCH(0x380, 0x4));  in mt792x_dma_prefetch()
135 	mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);  in mt792x_dma_enable()
137 		mt76_wr(dev, MT_WFDMA0_RST_DRX_PTR, ~0);  in mt792x_dma_enable()
140 	mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);  in mt792x_dma_enable()
158 		mt76_set(dev, MT_WFDMA0_INT_RX_PRI, 0x0F00);  in mt792x_dma_enable()
159 		mt76_set(dev, MT_WFDMA0_INT_TX_PRI, 0x7F00);  in mt792x_dma_enable()
172 	return 0;  in mt792x_dma_enable()
186 	for (i = 0; i < __MT_TXQ_MAX; i++)  in mt792x_dma_reset()
189 	for (i = 0; i < __MT_MCUQ_MAX; i++)  in mt792x_dma_reset()
205 	for (i = 0; i < ARRAY_SIZE(dev->mt76.phy.q_tx); i++)  in mt792x_wpdma_reset()
208 	for (i = 0; i < ARRAY_SIZE(dev->mt76.q_mcu); i++)  in mt792x_wpdma_reset()
226 	return 0;  in mt792x_wpdma_reset()
238 		mt76_wr(dev, dev->irq_map->host_irq_enable, 0);  in mt792x_wpdma_reinit_cond()
239 		mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);  in mt792x_wpdma_reinit_cond()
248 		mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);  in mt792x_wpdma_reinit_cond()
252 	return 0;  in mt792x_wpdma_reinit_cond()
268 				 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 100, 1))  in mt792x_dma_disable()
287 	return 0;  in mt792x_dma_disable()
304 			    MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 100, 1);  in mt792x_dma_cleanup()
328 		return 0;  in mt792x_poll_tx()
337 	return 0;  in mt792x_poll_tx()
351 		return 0;  in mt792x_poll_rx()
362 	u32 addr = is_mt7921(&dev->mt76) ? 0x18000140 : 0x7c000140;  in mt792x_wfsys_reset()
372 	return 0;  in mt792x_wfsys_reset()