Lines Matching refs:FIELD_PREP
123 val = FIELD_PREP(MT_ADIE_EFUSE_MODE_MASK, 0) | in mt7986_wmac_adie_efuse_read()
124 FIELD_PREP(MT_ADIE_EFUSE_ADDR_MASK, addr) | in mt7986_wmac_adie_efuse_read()
125 FIELD_PREP(MT_ADIE_EFUSE_KICK_MASK, 1); in mt7986_wmac_adie_efuse_read()
191 FIELD_PREP(MT_TOP_POS_FAST_EN_MASK, 0x1)); in mt7986_wmac_consys_reset()
239 FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable)); in mt7986_wmac_consys_lockup()
248 FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable)); in mt7986_wmac_consys_lockup()
257 FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable)); in mt7986_wmac_consys_lockup()
260 FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable)); in mt7986_wmac_consys_lockup()
396 FIELD_PREP(MT_ADIE_VRPI_SEL_CR_MASK, val)); in mt7986_wmac_adie_thermal_cal()
403 FIELD_PREP(MT_ADIE_PGA_GAIN_MASK, val)); in mt7986_wmac_adie_thermal_cal()
415 FIELD_PREP(MT_ADIE_LDO_CTRL_MASK, val)); in mt7986_wmac_adie_thermal_cal()
477 mode = FIELD_PREP(GENMASK(6, 4), val); in mt7986_wmac_adie_xtal_trim_7976()
481 FIELD_PREP(GENMASK(31, 24), trim_80m)); in mt7986_wmac_adie_xtal_trim_7976()
487 FIELD_PREP(GENMASK(31, 24), trim_80m)); in mt7986_wmac_adie_xtal_trim_7976()
491 FIELD_PREP(GENMASK(23, 16), trim_40m)); in mt7986_wmac_adie_xtal_trim_7976()
497 FIELD_PREP(GENMASK(23, 16), trim_40m)); in mt7986_wmac_adie_xtal_trim_7976()
961 MT_TOP_PWR_KEY | FIELD_PREP(MT_TOP_PWR_EN_MASK, enable)); in mt7986_wmac_wfsys_poweron()
1007 u32 val = FIELD_PREP(MT_MCU_BUS_TIMEOUT_SET_MASK, 1) | in mt7986_wmac_wfsys_set_timeout()
1008 FIELD_PREP(MT_MCU_BUS_TIMEOUT_CG_EN_MASK, 1) | in mt7986_wmac_wfsys_set_timeout()
1009 FIELD_PREP(MT_MCU_BUS_TIMEOUT_EN_MASK, 1); in mt7986_wmac_wfsys_set_timeout()
1018 val = FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_SET_MASK, 0x3aa) | in mt7986_wmac_wfsys_set_timeout()
1019 FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK, 1) | in mt7986_wmac_wfsys_set_timeout()
1020 FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_EN_MASK, 1); in mt7986_wmac_wfsys_set_timeout()
1043 FIELD_PREP(MT_TOP_POS_SKU_MASK, val)); in mt7986_wmac_sku_update()