Lines Matching full:mphy
18 struct mt76_queue *q = dev->mphy.q_tx[MT_TXQ_PSD]; in mt76x02_pre_tbtt_tasklet()
25 if (dev->mphy.offchannel) in mt76x02_pre_tbtt_tasklet()
148 mt76_txq_schedule_all(&dev->mphy); in mt76x02_tx_worker()
161 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false); in mt76x02_poll_tx()
168 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false); in mt76x02_poll_tx()
199 ret = mt76_init_tx_queue(&dev->mphy, i, mt76_ac_to_hwq(i), in mt76x02_dma_init()
206 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT_TX_HW_QUEUE_MGMT, in mt76x02_dma_init()
267 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) in mt76x02_irq_handler()
292 mt76_queue_kick(dev, dev->mphy.q_tx[MT_TXQ_PSD]); in mt76x02_irq_handler()
357 q = dev->mphy.q_tx[i]; in mt76x02_tx_hang()
399 clear_bit(MT76_STATE_RUNNING, &dev->mphy.state); in mt76x02_reset_state()
425 __mt76_sta_remove(&dev->mphy, vif, sta); in mt76x02_reset_state()
440 set_bit(MT76_RESET, &dev->mphy.state); in mt76x02_watchdog_reset()
479 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); in mt76x02_watchdog_reset()
501 clear_bit(MT76_RESET, &dev->mphy.state); in mt76x02_watchdog_reset()
519 set_bit(MT76_RESTART, &dev->mphy.state); in mt76x02_watchdog_reset()
524 mt76_txq_schedule_all(&dev->mphy); in mt76x02_watchdog_reset()
536 clear_bit(MT76_RESTART, &dev->mphy.state); in mt76x02_reconfig_complete()
542 if (test_bit(MT76_RESTART, &dev->mphy.state)) in mt76x02_check_tx_hang()