1 // SPDX-License-Identifier: ISC
3  * Copyright (C) 2016 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
152 				     struct mt76x02_dfs_sequence *seq)  in mt76x02_dfs_seq_pool_put()  argument
154 	struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;  in mt76x02_dfs_seq_pool_put()
156 	list_add(&seq->head, &dfs_pd->seq_pool);  in mt76x02_dfs_seq_pool_put()
158 	dfs_pd->seq_stats.seq_pool_len++;  in mt76x02_dfs_seq_pool_put()
159 	dfs_pd->seq_stats.seq_len--;  in mt76x02_dfs_seq_pool_put()
165 	struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;  in mt76x02_dfs_seq_pool_get()
166 	struct mt76x02_dfs_sequence *seq;  in mt76x02_dfs_seq_pool_get()  local
168 	if (list_empty(&dfs_pd->seq_pool)) {  in mt76x02_dfs_seq_pool_get()
169 		seq = devm_kzalloc(dev->mt76.dev, sizeof(*seq), GFP_ATOMIC);  in mt76x02_dfs_seq_pool_get()
171 		seq = list_first_entry(&dfs_pd->seq_pool,  in mt76x02_dfs_seq_pool_get()
174 		list_del(&seq->head);  in mt76x02_dfs_seq_pool_get()
175 		dfs_pd->seq_stats.seq_pool_len--;  in mt76x02_dfs_seq_pool_get()
177 	if (seq)  in mt76x02_dfs_seq_pool_get()
178 		dfs_pd->seq_stats.seq_len++;  in mt76x02_dfs_seq_pool_get()
180 	return seq;  in mt76x02_dfs_seq_pool_get()
190 	if (abs(val - frac) <= margin)  in mt76x02_dfs_get_multiple()
197 		if ((frac - remainder) <= margin)  in mt76x02_dfs_get_multiple()
207 	struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;  in mt76x02_dfs_detector_reset()
208 	struct mt76x02_dfs_sequence *seq, *tmp_seq;  in mt76x02_dfs_detector_reset()  local
215 	for (i = 0; i < ARRAY_SIZE(dfs_pd->event_rb); i++) {  in mt76x02_dfs_detector_reset()
216 		dfs_pd->event_rb[i].h_rb = 0;  in mt76x02_dfs_detector_reset()
217 		dfs_pd->event_rb[i].t_rb = 0;  in mt76x02_dfs_detector_reset()
220 	list_for_each_entry_safe(seq, tmp_seq, &dfs_pd->sequences, head) {  in mt76x02_dfs_detector_reset()
221 		list_del_init(&seq->head);  in mt76x02_dfs_detector_reset()
222 		mt76x02_dfs_seq_pool_put(dev, seq);  in mt76x02_dfs_detector_reset()
230 	struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;  in mt76x02_dfs_check_chirp()
233 	delta_ts = current_ts - dfs_pd->chirp_pulse_ts;  in mt76x02_dfs_check_chirp()
234 	dfs_pd->chirp_pulse_ts = current_ts;  in mt76x02_dfs_check_chirp()
238 		if (++dfs_pd->chirp_pulse_cnt > 8)  in mt76x02_dfs_check_chirp()
241 		dfs_pd->chirp_pulse_cnt = 1;  in mt76x02_dfs_check_chirp()
253 	data = (MT_DFS_CH_EN << 16) | pulse->engine;  in mt76x02_dfs_get_hw_pulse()
257 	pulse->period = mt76_rr(dev, MT_BBP(DFS, 19));  in mt76x02_dfs_get_hw_pulse()
260 	pulse->w1 = mt76_rr(dev, MT_BBP(DFS, 20));  in mt76x02_dfs_get_hw_pulse()
261 	pulse->w2 = mt76_rr(dev, MT_BBP(DFS, 23));  in mt76x02_dfs_get_hw_pulse()
264 	pulse->burst = mt76_rr(dev, MT_BBP(DFS, 22));  in mt76x02_dfs_get_hw_pulse()
272 	if (!pulse->period || !pulse->w1)  in mt76x02_dfs_check_hw_pulse()
275 	switch (dev->mt76.region) {  in mt76x02_dfs_check_hw_pulse()
277 		if (pulse->engine > 3)  in mt76x02_dfs_check_hw_pulse()
280 		if (pulse->engine == 3) {  in mt76x02_dfs_check_hw_pulse()
286 		if (pulse->w1 < 120)  in mt76x02_dfs_check_hw_pulse()
287 			ret = (pulse->period >= 2900 &&  in mt76x02_dfs_check_hw_pulse()
288 			       (pulse->period <= 4700 ||  in mt76x02_dfs_check_hw_pulse()
289 				pulse->period >= 6400) &&  in mt76x02_dfs_check_hw_pulse()
290 			       (pulse->period <= 6800 ||  in mt76x02_dfs_check_hw_pulse()
291 				pulse->period >= 10200) &&  in mt76x02_dfs_check_hw_pulse()
292 			       pulse->period <= 61600);  in mt76x02_dfs_check_hw_pulse()
293 		else if (pulse->w1 < 130) /* 120 - 130 */  in mt76x02_dfs_check_hw_pulse()
294 			ret = (pulse->period >= 2900 &&  in mt76x02_dfs_check_hw_pulse()
295 			       pulse->period <= 61600);  in mt76x02_dfs_check_hw_pulse()
297 			ret = (pulse->period >= 3500 &&  in mt76x02_dfs_check_hw_pulse()
298 			       pulse->period <= 10100);  in mt76x02_dfs_check_hw_pulse()
301 		if (pulse->engine >= 3)  in mt76x02_dfs_check_hw_pulse()
304 		ret = (pulse->period >= 4900 &&  in mt76x02_dfs_check_hw_pulse()
305 		       (pulse->period <= 10200 ||  in mt76x02_dfs_check_hw_pulse()
306 			pulse->period >= 12400) &&  in mt76x02_dfs_check_hw_pulse()
307 		       pulse->period <= 100100);  in mt76x02_dfs_check_hw_pulse()
310 		if (dev->mphy.chandef.chan->center_freq >= 5250 &&  in mt76x02_dfs_check_hw_pulse()
311 		    dev->mphy.chandef.chan->center_freq <= 5350) {  in mt76x02_dfs_check_hw_pulse()
313 			if (pulse->w1 <= 130)  in mt76x02_dfs_check_hw_pulse()
314 				ret = (pulse->period >= 28360 &&  in mt76x02_dfs_check_hw_pulse()
315 				       (pulse->period <= 28700 ||  in mt76x02_dfs_check_hw_pulse()
316 					pulse->period >= 76900) &&  in mt76x02_dfs_check_hw_pulse()
317 				       pulse->period <= 76940);  in mt76x02_dfs_check_hw_pulse()
321 		if (pulse->engine > 3)  in mt76x02_dfs_check_hw_pulse()
324 		if (pulse->engine == 3) {  in mt76x02_dfs_check_hw_pulse()
330 		if (pulse->w1 < 120)  in mt76x02_dfs_check_hw_pulse()
331 			ret = (pulse->period >= 2900 &&  in mt76x02_dfs_check_hw_pulse()
332 			       (pulse->period <= 4700 ||  in mt76x02_dfs_check_hw_pulse()
333 				pulse->period >= 6400) &&  in mt76x02_dfs_check_hw_pulse()
334 			       (pulse->period <= 6800 ||  in mt76x02_dfs_check_hw_pulse()
335 				pulse->period >= 27560) &&  in mt76x02_dfs_check_hw_pulse()
336 			       (pulse->period <= 27960 ||  in mt76x02_dfs_check_hw_pulse()
337 				pulse->period >= 28360) &&  in mt76x02_dfs_check_hw_pulse()
338 			       (pulse->period <= 28700 ||  in mt76x02_dfs_check_hw_pulse()
339 				pulse->period >= 79900) &&  in mt76x02_dfs_check_hw_pulse()
340 			       pulse->period <= 80100);  in mt76x02_dfs_check_hw_pulse()
341 		else if (pulse->w1 < 130) /* 120 - 130 */  in mt76x02_dfs_check_hw_pulse()
342 			ret = (pulse->period >= 2900 &&  in mt76x02_dfs_check_hw_pulse()
343 			       (pulse->period <= 10100 ||  in mt76x02_dfs_check_hw_pulse()
344 				pulse->period >= 27560) &&  in mt76x02_dfs_check_hw_pulse()
345 			       (pulse->period <= 27960 ||  in mt76x02_dfs_check_hw_pulse()
346 				pulse->period >= 28360) &&  in mt76x02_dfs_check_hw_pulse()
347 			       (pulse->period <= 28700 ||  in mt76x02_dfs_check_hw_pulse()
348 				pulse->period >= 79900) &&  in mt76x02_dfs_check_hw_pulse()
349 			       pulse->period <= 80100);  in mt76x02_dfs_check_hw_pulse()
351 			ret = (pulse->period >= 3900 &&  in mt76x02_dfs_check_hw_pulse()
352 			       pulse->period <= 10100);  in mt76x02_dfs_check_hw_pulse()
367 	/* 1st: DFS_R37[31]: 0 (engine 0) - 1 (engine 2)  in mt76x02_dfs_fetch_event()
380 	event->engine = MT_DFS_EVENT_ENGINE(data);  in mt76x02_dfs_fetch_event()
382 	event->ts = MT_DFS_EVENT_TIMESTAMP(data);  in mt76x02_dfs_fetch_event()
384 	event->width = MT_DFS_EVENT_WIDTH(data);  in mt76x02_dfs_fetch_event()
392 	if (event->engine == 2) {  in mt76x02_dfs_check_event()
393 		struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;  in mt76x02_dfs_check_event()
394 		struct mt76x02_dfs_event_rb *event_buff = &dfs_pd->event_rb[1];  in mt76x02_dfs_check_event()
398 		last_event_idx = mt76_decr(event_buff->t_rb,  in mt76x02_dfs_check_event()
400 		delta_ts = event->ts - event_buff->data[last_event_idx].ts;  in mt76x02_dfs_check_event()
402 		    event_buff->data[last_event_idx].width >= 200)  in mt76x02_dfs_check_event()
411 	struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;  in mt76x02_dfs_queue_event()
415 	event_buff = event->engine == 2 ? &dfs_pd->event_rb[1]  in mt76x02_dfs_queue_event()
416 					: &dfs_pd->event_rb[0];  in mt76x02_dfs_queue_event()
417 	event_buff->data[event_buff->t_rb] = *event;  in mt76x02_dfs_queue_event()
418 	event_buff->data[event_buff->t_rb].fetch_ts = jiffies;  in mt76x02_dfs_queue_event()
420 	event_buff->t_rb = mt76_incr(event_buff->t_rb, MT_DFS_EVENT_BUFLEN);  in mt76x02_dfs_queue_event()
421 	if (event_buff->t_rb == event_buff->h_rb)  in mt76x02_dfs_queue_event()
422 		event_buff->h_rb = mt76_incr(event_buff->h_rb,  in mt76x02_dfs_queue_event()
430 	struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;  in mt76x02_dfs_create_sequence()
433 	struct mt76x02_dfs_sequence seq, *seq_p;  in mt76x02_dfs_create_sequence()  local
438 	event_rb = event->engine == 2 ? &dfs_pd->event_rb[1]  in mt76x02_dfs_create_sequence()
439 				      : &dfs_pd->event_rb[0];  in mt76x02_dfs_create_sequence()
441 	i = mt76_decr(event_rb->t_rb, MT_DFS_EVENT_BUFLEN);  in mt76x02_dfs_create_sequence()
442 	end = mt76_decr(event_rb->h_rb, MT_DFS_EVENT_BUFLEN);  in mt76x02_dfs_create_sequence()
445 		cur_event = &event_rb->data[i];  in mt76x02_dfs_create_sequence()
446 		with_sum = event->width + cur_event->width;  in mt76x02_dfs_create_sequence()
448 		sw_params = &dfs_pd->sw_dpd_params;  in mt76x02_dfs_create_sequence()
449 		switch (dev->mt76.region) {  in mt76x02_dfs_create_sequence()
458 			if (event->engine == 2)  in mt76x02_dfs_create_sequence()
467 			return -EINVAL;  in mt76x02_dfs_create_sequence()
470 		pri = event->ts - cur_event->ts;  in mt76x02_dfs_create_sequence()
471 		if (abs(event->width - cur_event->width) > width_delta ||  in mt76x02_dfs_create_sequence()
472 		    pri < sw_params->min_pri)  in mt76x02_dfs_create_sequence()
475 		if (pri > sw_params->max_pri)  in mt76x02_dfs_create_sequence()
478 		seq.pri = event->ts - cur_event->ts;  in mt76x02_dfs_create_sequence()
479 		seq.first_ts = cur_event->ts;  in mt76x02_dfs_create_sequence()
480 		seq.last_ts = event->ts;  in mt76x02_dfs_create_sequence()
481 		seq.engine = event->engine;  in mt76x02_dfs_create_sequence()
482 		seq.count = 2;  in mt76x02_dfs_create_sequence()
486 			cur_event = &event_rb->data[j];  in mt76x02_dfs_create_sequence()
487 			cur_pri = event->ts - cur_event->ts;  in mt76x02_dfs_create_sequence()
488 			factor = mt76x02_dfs_get_multiple(cur_pri, seq.pri,  in mt76x02_dfs_create_sequence()
489 						sw_params->pri_margin);  in mt76x02_dfs_create_sequence()
491 				seq.first_ts = cur_event->ts;  in mt76x02_dfs_create_sequence()
492 				seq.count++;  in mt76x02_dfs_create_sequence()
497 		if (seq.count <= cur_len)  in mt76x02_dfs_create_sequence()
502 			return -ENOMEM;  in mt76x02_dfs_create_sequence()
504 		*seq_p = seq;  in mt76x02_dfs_create_sequence()
505 		INIT_LIST_HEAD(&seq_p->head);  in mt76x02_dfs_create_sequence()
506 		list_add(&seq_p->head, &dfs_pd->sequences);  in mt76x02_dfs_create_sequence()
516 	struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;  in mt76x02_dfs_add_event_to_sequence()
518 	struct mt76x02_dfs_sequence *seq, *tmp_seq;  in mt76x02_dfs_add_event_to_sequence()  local
522 	sw_params = &dfs_pd->sw_dpd_params;  in mt76x02_dfs_add_event_to_sequence()
523 	list_for_each_entry_safe(seq, tmp_seq, &dfs_pd->sequences, head) {  in mt76x02_dfs_add_event_to_sequence()
524 		if (event->ts > seq->first_ts + MT_DFS_SEQUENCE_WINDOW) {  in mt76x02_dfs_add_event_to_sequence()
525 			list_del_init(&seq->head);  in mt76x02_dfs_add_event_to_sequence()
526 			mt76x02_dfs_seq_pool_put(dev, seq);  in mt76x02_dfs_add_event_to_sequence()
530 		if (event->engine != seq->engine)  in mt76x02_dfs_add_event_to_sequence()
533 		pri = event->ts - seq->last_ts;  in mt76x02_dfs_add_event_to_sequence()
534 		factor = mt76x02_dfs_get_multiple(pri, seq->pri,  in mt76x02_dfs_add_event_to_sequence()
535 						  sw_params->pri_margin);  in mt76x02_dfs_add_event_to_sequence()
537 			seq->last_ts = event->ts;  in mt76x02_dfs_add_event_to_sequence()
538 			seq->count++;  in mt76x02_dfs_add_event_to_sequence()
539 			max_seq_len = max_t(u16, max_seq_len, seq->count);  in mt76x02_dfs_add_event_to_sequence()
547 	struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;  in mt76x02_dfs_check_detection()
548 	struct mt76x02_dfs_sequence *seq;  in mt76x02_dfs_check_detection()  local
550 	if (list_empty(&dfs_pd->sequences))  in mt76x02_dfs_check_detection()
553 	list_for_each_entry(seq, &dfs_pd->sequences, head) {  in mt76x02_dfs_check_detection()
554 		if (seq->count > MT_DFS_SEQUENCE_TH) {  in mt76x02_dfs_check_detection()
555 			dfs_pd->stats[seq->engine].sw_pattern++;  in mt76x02_dfs_check_detection()
564 	struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;  in mt76x02_dfs_add_events()
574 		if (dfs_pd->last_event_ts > event.ts)  in mt76x02_dfs_add_events()
576 		dfs_pd->last_event_ts = event.ts;  in mt76x02_dfs_add_events()
591 	struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;  in mt76x02_dfs_check_event_window()
596 	for (i = 0; i < ARRAY_SIZE(dfs_pd->event_rb); i++) {  in mt76x02_dfs_check_event_window()
597 		event_buff = &dfs_pd->event_rb[i];  in mt76x02_dfs_check_event_window()
599 		while (event_buff->h_rb != event_buff->t_rb) {  in mt76x02_dfs_check_event_window()
600 			event = &event_buff->data[event_buff->h_rb];  in mt76x02_dfs_check_event_window()
603 			if (time_is_after_jiffies(event->fetch_ts +  in mt76x02_dfs_check_event_window()
606 			event_buff->h_rb = mt76_incr(event_buff->h_rb,  in mt76x02_dfs_check_event_window()
620 	if (test_bit(MT76_SCANNING, &dev->mphy.state))  in mt76x02_dfs_tasklet()
623 	if (time_is_before_jiffies(dfs_pd->last_sw_check +  in mt76x02_dfs_tasklet()
627 		dfs_pd->last_sw_check = jiffies;  in mt76x02_dfs_tasklet()
633 			ieee80211_radar_detected(dev->mt76.hw);  in mt76x02_dfs_tasklet()
655 			dfs_pd->stats[i].hw_pulse_discarded++;  in mt76x02_dfs_tasklet()
660 		dfs_pd->stats[i].hw_pattern++;  in mt76x02_dfs_tasklet()
661 		ieee80211_radar_detected(dev->mt76.hw);  in mt76x02_dfs_tasklet()
676 	struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;  in mt76x02_dfs_init_sw_detector()
678 	switch (dev->mt76.region) {  in mt76x02_dfs_init_sw_detector()
680 		dfs_pd->sw_dpd_params.max_pri = MT_DFS_FCC_MAX_PRI;  in mt76x02_dfs_init_sw_detector()
681 		dfs_pd->sw_dpd_params.min_pri = MT_DFS_FCC_MIN_PRI;  in mt76x02_dfs_init_sw_detector()
682 		dfs_pd->sw_dpd_params.pri_margin = MT_DFS_PRI_MARGIN;  in mt76x02_dfs_init_sw_detector()
685 		dfs_pd->sw_dpd_params.max_pri = MT_DFS_ETSI_MAX_PRI;  in mt76x02_dfs_init_sw_detector()
686 		dfs_pd->sw_dpd_params.min_pri = MT_DFS_ETSI_MIN_PRI;  in mt76x02_dfs_init_sw_detector()
687 		dfs_pd->sw_dpd_params.pri_margin = MT_DFS_PRI_MARGIN << 2;  in mt76x02_dfs_init_sw_detector()
690 		dfs_pd->sw_dpd_params.max_pri = MT_DFS_JP_MAX_PRI;  in mt76x02_dfs_init_sw_detector()
691 		dfs_pd->sw_dpd_params.min_pri = MT_DFS_JP_MIN_PRI;  in mt76x02_dfs_init_sw_detector()
692 		dfs_pd->sw_dpd_params.pri_margin = MT_DFS_PRI_MARGIN;  in mt76x02_dfs_init_sw_detector()
706 	switch (dev->mphy.chandef.width) {  in mt76x02_dfs_set_bbp_params()
718 	switch (dev->mt76.region) {  in mt76x02_dfs_set_bbp_params()
726 		if (dev->mphy.chandef.chan->center_freq >= 5250 &&  in mt76x02_dfs_set_bbp_params()
727 		    dev->mphy.chandef.chan->center_freq <= 5350)  in mt76x02_dfs_set_bbp_params()
809 	dfs_r31 -= (agc_r8 & 0x00000038) >> 3;  in mt76x02_phy_dfs_adjust_agc()
826 	if (mt76_phy_dfs_state(&dev->mphy) > MT_DFS_STATE_DISABLED) {  in mt76x02_dfs_init_params()
840 		if (mt76_chip(&dev->mt76) == 0x7610 ||  in mt76x02_dfs_init_params()
841 		    mt76_chip(&dev->mt76) == 0x7630)  in mt76x02_dfs_init_params()
855 	struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;  in mt76x02_dfs_init_detector()
857 	INIT_LIST_HEAD(&dfs_pd->sequences);  in mt76x02_dfs_init_detector()
858 	INIT_LIST_HEAD(&dfs_pd->seq_pool);  in mt76x02_dfs_init_detector()
859 	dev->mt76.region = NL80211_DFS_UNSET;  in mt76x02_dfs_init_detector()
860 	dfs_pd->last_sw_check = jiffies;  in mt76x02_dfs_init_detector()
861 	tasklet_setup(&dfs_pd->dfs_tasklet, mt76x02_dfs_tasklet);  in mt76x02_dfs_init_detector()
868 	struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;  in mt76x02_dfs_set_domain()
870 	mutex_lock(&dev->mt76.mutex);  in mt76x02_dfs_set_domain()
871 	if (dev->mt76.region != region) {  in mt76x02_dfs_set_domain()
872 		tasklet_disable(&dfs_pd->dfs_tasklet);  in mt76x02_dfs_set_domain()
874 		dev->ed_monitor = dev->ed_monitor_enabled &&  in mt76x02_dfs_set_domain()
878 		dev->mt76.region = region;  in mt76x02_dfs_set_domain()
880 		tasklet_enable(&dfs_pd->dfs_tasklet);  in mt76x02_dfs_set_domain()
882 	mutex_unlock(&dev->mt76.mutex);  in mt76x02_dfs_set_domain()
889 	struct mt76x02_dev *dev = hw->priv;  in mt76x02_regd_notifier()
891 	mt76x02_dfs_set_domain(dev, request->dfs_region);  in mt76x02_regd_notifier()