14 	u32 ret = 0;  in mt7603_ac_queue_mask0()
16 	ret |= GENMASK(3, 0) * !!(mask & BIT(0));  in mt7603_ac_queue_mask0()
39 	for (i = 0; i < 2; i++)  in mt7603_mac_reset_counters()
42 	memset(dev->mphy.aggr_stats, 0, sizeof(dev->mphy.aggr_stats));  in mt7603_mac_reset_counters()
92 	mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);  in mt7603_wtbl_update()
129 	u32 w0 = 0, w1 = 0;  in mt7603_wtbl_init()
139 	if (vif < 0)  in mt7603_wtbl_init()
140 		vif = 0;  in mt7603_wtbl_init()
145 	mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);  in mt7603_wtbl_init()
147 	mt76_set(dev, addr + 0 * 4, w0);  in mt7603_wtbl_init()
151 	mt76_stop_tx_ac(dev, GENMASK(3, 0));  in mt7603_wtbl_init()
153 	for (i = 0; i < MT_WTBL2_SIZE; i += 4)  in mt7603_wtbl_init()
154 		mt76_wr(dev, addr + i, 0);  in mt7603_wtbl_init()
156 	mt76_start_tx_ac(dev, GENMASK(3, 0));  in mt7603_wtbl_init()
159 	for (i = 0; i < MT_WTBL3_SIZE; i += 4)  in mt7603_wtbl_init()
160 		mt76_wr(dev, addr + i, 0);  in mt7603_wtbl_init()
163 	for (i = 0; i < MT_WTBL4_SIZE; i += 4)  in mt7603_wtbl_init()
164 		mt76_wr(dev, addr + i, 0);  in mt7603_wtbl_init()
190 		port = 0; /* HIF */  in mt7603_filter_tx()
206 	mt76_poll(dev, MT_WF_ARB_TX_FLUSH_0, flush_mask, 0, 20000);  in mt7603_filter_tx()
209 	mt76_wr(dev, MT_TX_ABORT, 0);  in mt7603_filter_tx()
211 	for (i = 0; i < 4; i++) {  in mt7603_filter_tx()
218 		mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 0, 5000);  in mt7603_filter_tx()
251 		FIELD_PREP(MT_PSE_RTA_PORT_ID, 0) |  in mt7603_wtbl_set_ps()
256 	mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000);  in mt7603_wtbl_set_ps()
291 	mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);  in mt7603_wtbl_clear()
293 	mt76_wr(dev, addr + 0 * 4,  in mt7603_wtbl_clear()
297 	mt76_wr(dev, addr + 1 * 4, 0);  in mt7603_wtbl_clear()
298 	mt76_wr(dev, addr + 2 * 4, 0);  in mt7603_wtbl_clear()
317 	mt76_wr(dev, addr + (15 * 4), 0);  in mt7603_wtbl_clear()
319 	mt76_stop_tx_ac(dev, GENMASK(3, 0));  in mt7603_wtbl_clear()
321 		mt76_wr(dev, addr + (i * 4), 0);  in mt7603_wtbl_clear()
323 	mt76_start_tx_ac(dev, GENMASK(3, 0));  in mt7603_wtbl_clear()
389 	if (ba_size < 0) {  in mt7603_mac_tx_ba_reset()
395 	for (i = 7; i > 0; i--) {  in mt7603_mac_tx_ba_reset()
409 		[IEEE80211_AC_BE] = 0,  in mt7603_mac_sta_poll()
416 	u32 total_airtime = 0;  in mt7603_mac_sta_poll()
438 		for (i = 0; i < 4; i++) {  in mt7603_mac_sta_poll()
453 			memset(msta->tx_airtime_ac, 0,  in mt7603_mac_sta_poll()
461 		for (i = 0; i < 4; i++) {  in mt7603_mac_sta_poll()
470 			ieee80211_sta_register_airtime(sta, tid, txtime, 0);  in mt7603_mac_sta_poll()
514 	u32 rxd0 = le32_to_cpu(rxd[0]);  in mt7603_mac_fill_rx()
523 	memset(status, 0, sizeof(*status));  in mt7603_mac_fill_rx()
546 	if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&  in mt7603_mac_fill_rx()
582 				status->iv[0] = data[5];  in mt7603_mac_fill_rx()
587 				status->iv[5] = data[0];  in mt7603_mac_fill_rx()
599 		status->timestamp = le32_to_cpu(rxd[0]);  in mt7603_mac_fill_rx()
621 		u32 rxdg0 = le32_to_cpu(rxd[0]);  in mt7603_mac_fill_rx()
654 		status->chain_signal[0] = FIELD_GET(MT_RXV4_IB_RSSI0, rxdg3) +  in mt7603_mac_fill_rx()
655 					  dev->rssi_offset[0];  in mt7603_mac_fill_rx()
679 		return 0;  in mt7603_mac_fill_rx()
686 	return 0;  in mt7603_mac_fill_rx()
696 	*bw = 0;  in mt7603_mac_tx_rate_val()
718 		rate_idx = val & 0xff;  in mt7603_mac_tx_rate_val()
739 	u8 bw, bw_prev, bw_idx = 0;  in mt7603_wtbl_set_rates()
746 	if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))  in mt7603_wtbl_set_rates()
752 	rateset = !(sta->rate_set_tsf & BIT(0));  in mt7603_wtbl_set_rates()
760 		ref = &sta->rateset[rateset].rates[0];  in mt7603_wtbl_set_rates()
764 	for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) {  in mt7603_wtbl_set_rates()
775 		for (k = 0; k < i; k++) {  in mt7603_wtbl_set_rates()
792 	val[0] = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw);  in mt7603_wtbl_set_rates()
800 			bw_prev = 0;  in mt7603_wtbl_set_rates()
802 		probe_val = val[0];  in mt7603_wtbl_set_rates()
831 		FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) |  in mt7603_wtbl_set_rates()
846 	sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset;  in mt7603_wtbl_set_rates()
854 		mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);  in mt7603_wtbl_set_rates()
863 	memset(key_data, 0, 32);  in mt7603_mac_get_key_info()
914 	return 0;  in mt7603_wtbl_set_key()
924 	struct ieee80211_tx_rate *rate = &info->control.rates[0];  in mt7603_mac_write_txwi()
935 	u16 seqno = 0;  in mt7603_mac_write_txwi()
936 	u8 vif_idx = 0;  in mt7603_mac_write_txwi()
944 			vif_idx += 0x10;  in mt7603_mac_write_txwi()
963 	txwi[0] = cpu_to_le32(val);  in mt7603_mac_write_txwi()
987 	txwi[4] = 0;  in mt7603_mac_write_txwi()
993 	txwi[6] = 0;  in mt7603_mac_write_txwi()
995 	if (rate->idx >= 0 && rate->count &&  in mt7603_mac_write_txwi()
1018 		tx_count = 0x1f;  in mt7603_mac_write_txwi()
1038 		txwi[4] = cpu_to_le32(pn & GENMASK(31, 0));  in mt7603_mac_write_txwi()
1042 	txwi[7] = 0;  in mt7603_mac_write_txwi()
1044 	return 0;  in mt7603_mac_write_txwi()
1076 		mt7603_wtbl_set_rates(dev, msta, &info->control.rates[0],  in mt7603_tx_prepare_skb()
1085 	return 0;  in mt7603_tx_prepare_skb()
1094 	int first_idx = 0, last_idx;  in mt7603_fill_txs()
1109 	fixed_rate = info->status.rates[0].count;  in mt7603_fill_txs()
1117 	txs = le32_to_cpu(txs_data[0]);  in mt7603_fill_txs()
1137 	first_idx = max_t(int, 0, last_idx - (count - 1) / MT7603_RATE_RETRY);  in mt7603_fill_txs()
1140 		info->status.rates[0].count = count;  in mt7603_fill_txs()
1141 		i = 0;  in mt7603_fill_txs()
1148 	rs_idx ^= rate_set_tsf & BIT(0);  in mt7603_fill_txs()
1151 	if (!first_idx && rs->probe_rate.idx >= 0) {  in mt7603_fill_txs()
1152 		info->status.rates[0] = rs->probe_rate;  in mt7603_fill_txs()
1162 		info->status.rates[0] = rs->rates[first_idx / 2];  in mt7603_fill_txs()
1164 	info->status.rates[0].count = 0;  in mt7603_fill_txs()
1166 	for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) {  in mt7603_fill_txs()
1183 			info->status.rates[i].count = 0;  in mt7603_fill_txs()
1201 		final_rate &= GENMASK(5, 0);  in mt7603_fill_txs()
1204 		final_rate_flags = 0;  in mt7603_fill_txs()
1209 		final_rate &= GENMASK(5, 0);  in mt7603_fill_txs()
1242 			info->status.rates[0].count = 0;  in mt7603_mac_add_txs_skb()
1243 			info->status.rates[0].idx = -1;  in mt7603_mac_add_txs_skb()
1313 	dev->tx_hang_check = 0;  in mt7603_tx_complete_skb()
1323 			 0, 1000);  in wait_for_wpdma()
1341 		dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0;  in mt7603_pse_reset()
1346 		dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0;  in mt7603_pse_reset()
1369 	mt76_wr(dev, MT_WF_ARB_TX_START_0, ~0);  in mt7603_mac_start()
1377 	mt76_wr(dev, MT_WF_ARB_TX_START_0, 0);  in mt7603_mac_stop()
1436 	napi_disable(&dev->mt76.napi[0]);  in mt7603_mac_watchdog_reset()
1442 	mt7603_beacon_set_timer(dev, -1, 0);  in mt7603_mac_watchdog_reset()
1467 	for (i = 0; i < __MT_TXQ_MAX; i++)  in mt7603_mac_watchdog_reset()
1495 	napi_enable(&dev->mt76.napi[0]);  in mt7603_mac_watchdog_reset()
1496 	napi_schedule(&dev->mt76.napi[0]);  in mt7603_mac_watchdog_reset()
1542 	return (val & BIT(8)) && (val & 0xf) != 0xf;  in mt7603_tx_dma_busy()
1551 	for (i = 0; i < 4; i++) {  in mt7603_tx_hang()
1583 	if (is_mt7628(dev) && (val & 0x4001) == 0x4001)  in mt7603_rx_pse_busy()
1586 	return (val & 0x8001) == 0x8001 || (val & 0xe001) == 0xe001;  in mt7603_rx_pse_busy()
1595 		dev->reset_test = 0;  in mt7603_watchdog_check()
1601 			*counter = 0;  in mt7603_watchdog_check()
1628 	u32 rxtd_6 = 0xd7c80000;  in mt7603_edcca_set_strict()
1637 		rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x34);  in mt7603_edcca_set_strict()
1639 		rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x7d);  in mt7603_edcca_set_strict()
1642 		rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x0f);  in mt7603_edcca_set_strict()
1644 		rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x10);  in mt7603_edcca_set_strict()
1679 	else if (dev->ed_strong_signal > 0)  in mt7603_edcca_check()
1692 		if (dev->ed_trigger < 0)  in mt7603_edcca_check()
1693 			dev->ed_trigger = 0;  in mt7603_edcca_check()
1696 		if (dev->ed_trigger > 0)  in mt7603_edcca_check()
1697 			dev->ed_trigger = 0;  in mt7603_edcca_check()
1728 		dev->sensitivity = 0;  in mt7603_adjust_sensitivity()
1732 		agc0 = 0x56f0076f;  in mt7603_adjust_sensitivity()
1735 		agc3 = 0x81d0d5e3;  in mt7603_adjust_sensitivity()
1739 		agc0 = 0x6af0006f;  in mt7603_adjust_sensitivity()
1744 		agc3 = 0x8181d5e3;  in mt7603_adjust_sensitivity()
1751 		agc0 = 0x7ff0000f;  in mt7603_adjust_sensitivity()
1757 		agc3 = 0x818181e3;  in mt7603_adjust_sensitivity()
1760 	mt76_wr(dev, MT_AGC(0), agc0);  in mt7603_adjust_sensitivity()
1761 	mt76_wr(dev, MT_AGC1(0), agc0);  in mt7603_adjust_sensitivity()
1793 		dev->sensitivity = 0;  in mt7603_false_cca_check()
1841 	for (i = 0, idx = 0; i < 2; i++) {  in mt7603_mac_work()
1844 		dev->mphy.aggr_stats[idx++] += val & 0xffff;  in mt7603_mac_work()
1870 		dev->beacon_check = 0;  in mt7603_mac_work()
1871 		dev->tx_dma_check = 0;  in mt7603_mac_work()
1872 		dev->tx_hang_check = 0;  in mt7603_mac_work()
1873 		dev->rx_dma_check = 0;  in mt7603_mac_work()
1874 		dev->rx_pse_check = 0;  in mt7603_mac_work()
1875 		dev->mcu_hang = 0;  in mt7603_mac_work()
1876 		dev->rx_dma_idx = ~0;  in mt7603_mac_work()
1877 		memset(dev->tx_dma_idx, 0xff, sizeof(dev->tx_dma_idx));  in mt7603_mac_work()
1879 		dev->mphy.mac_work_count = 0;  in mt7603_mac_work()
1883 		dev->mphy.mac_work_count = 0;  in mt7603_mac_work()