27 		[1] = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 0xf),  in mt7603_set_tmac_template()
35 	for (i = 0; i < ARRAY_SIZE(desc); i++)  in mt7603_set_tmac_template()
49 	int reserved_count = 0;  in mt7603_dma_sched_init()
64 	mt76_wr(dev, MT_HIGH_PRIORITY_1, 0x55555553);  in mt7603_dma_sched_init()
65 	mt76_wr(dev, MT_HIGH_PRIORITY_2, 0x78555555);  in mt7603_dma_sched_init()
67 	mt76_wr(dev, MT_QUEUE_PRIORITY_1, 0x2b1a096e);  in mt7603_dma_sched_init()
68 	mt76_wr(dev, MT_QUEUE_PRIORITY_2, 0x785f4d3c);  in mt7603_dma_sched_init()
70 	mt76_wr(dev, MT_PRIORITY_MASK, 0xffffffff);  in mt7603_dma_sched_init()
75 	for (i = 0; i <= 4; i++)  in mt7603_dma_sched_init()
89 		reserved_count = 0;  in mt7603_dma_sched_init()
94 		mt76_wr(dev, MT_GROUP_THRESH(0),  in mt7603_dma_sched_init()
97 		mt76_wr(dev, MT_BMAP_0, 0x0080ff5f);  in mt7603_dma_sched_init()
99 		mt76_wr(dev, MT_BMAP_1, 0x00000020);  in mt7603_dma_sched_init()
101 		mt76_wr(dev, MT_GROUP_THRESH(0), page_count);  in mt7603_dma_sched_init()
102 		mt76_wr(dev, MT_BMAP_0, 0xffff);  in mt7603_dma_sched_init()
105 	mt76_wr(dev, MT_SCH_4, 0);  in mt7603_dma_sched_init()
107 	for (i = 0; i <= 15; i++)  in mt7603_dma_sched_init()
108 		mt76_wr(dev, MT_TXTIME_THRESH(i), 0xfffff);  in mt7603_dma_sched_init()
128 	dev->agc0 = mt76_rr(dev, MT_AGC(0));  in mt7603_phy_init()
140 		(MT_AGG_SIZE_LIMIT(0) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |  in mt7603_mac_init()
146 		(MT_AGG_SIZE_LIMIT(4) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |  in mt7603_mac_init()
152 		FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) |  in mt7603_mac_init()
158 		FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) |  in mt7603_mac_init()
164 		FIELD_PREP(MT_AGG_CONTROL_BAR_RATE, 0x4b) |  in mt7603_mac_init()
165 		FIELD_PREP(MT_AGG_CONTROL_CFEND_RATE, 0x69) |  in mt7603_mac_init()
175 	mt76_rmw(dev, MT_DMA_VCFR0, BIT(0), BIT(13));  in mt7603_mac_init()
176 	mt76_rmw(dev, MT_DMA_TMCFR0, BIT(0) | BIT(1), BIT(13));  in mt7603_mac_init()
181 	mt76_rmw(dev, MT_WF_RMAC_MAXMINLEN, 0xffffff, 0x19000);  in mt7603_mac_init()
183 	mt76_wr(dev, MT_WF_RFCR1, 0);  in mt7603_mac_init()
205 	mt76_wr(dev, MT_DMA_RCFR0, 0xc0000000);  in mt7603_mac_init()
220 	for (i = 0; i < MT7603_WTBL_SIZE; i++)  in mt7603_mac_init()
233 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) |  in mt7603_mac_init()
243 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7603_RATE_RETRY - 1) |  in mt7603_mac_init()
264 	for (i = 0; i <= 4; i++)  in mt7603_mac_init()
274 	mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);  in mt7603_init_hardware()
277 	if (ret < 0)  in mt7603_init_hardware()
284 	mt76_wr(dev, MT_WPDMA_GLO_CFG, 0x52000850);  in mt7603_init_hardware()
289 	for (i = 0; i < MT7603_WTBL_SIZE; i++) {  in mt7603_init_hardware()
292 		mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000);  in mt7603_init_hardware()
304 	return 0;  in mt7603_init_hardware()
340 	val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) |  in mt7603_led_set_config()
369 	return 0;  in mt7603_led_set_blink()
379 		mt7603_led_set_config(mphy, 0, 0xff);  in mt7603_led_set_brightness()
381 		mt7603_led_set_config(mphy, 0xff, 0);  in mt7603_led_set_brightness()
386 	if (addr < 0x100000)  in __mt7603_reg_addr()
434 		return 0;  in mt7603_txpower_signed()
436 	val &= GENMASK(5, 0);  in mt7603_txpower_signed()
459 		target_power = -(target_power & GENMASK(5, 0));  in mt7603_init_txpower()
461 	max_offset = 0;  in mt7603_init_txpower()
462 	for (i = 0; i < 14; i++) {  in mt7603_init_txpower()
478 	for (i = 0; i < sband->n_channels; i++) {  in mt7603_init_txpower()
550 	return 0;  in mt7603_register_device()