Lines Matching refs:mmio
14 val = readl(dev->mmio.regs + offset); in mt76_mmio_rr()
16 val = readl((u8 *)dev->mmio.regs + offset); in mt76_mmio_rr()
27 writel(val, dev->mmio.regs + offset); in mt76_mmio_wr()
29 writel(val, (u8 *)dev->mmio.regs + offset); in mt76_mmio_wr()
44 __iowrite32_copy(dev->mmio.regs + offset, data, DIV_ROUND_UP(len, 4)); in mt76_mmio_write_copy()
46 __iowrite32_copy((u8 *)dev->mmio.regs + offset, data, DIV_ROUND_UP(len, 4)); in mt76_mmio_write_copy()
54 __ioread32_copy(data, dev->mmio.regs + offset, DIV_ROUND_UP(len, 4)); in mt76_mmio_read_copy()
56 __ioread32_copy(data, (u8 *)dev->mmio.regs + offset, DIV_ROUND_UP(len, 4)); in mt76_mmio_read_copy()
89 spin_lock_irqsave(&dev->mmio.irq_lock, flags); in mt76_set_irq_mask()
90 dev->mmio.irqmask &= ~clear; in mt76_set_irq_mask()
91 dev->mmio.irqmask |= set; in mt76_set_irq_mask()
93 if (mtk_wed_device_active(&dev->mmio.wed)) in mt76_set_irq_mask()
94 mtk_wed_device_irq_set_mask(&dev->mmio.wed, in mt76_set_irq_mask()
95 dev->mmio.irqmask); in mt76_set_irq_mask()
97 mt76_mmio_wr(dev, addr, dev->mmio.irqmask); in mt76_set_irq_mask()
99 spin_unlock_irqrestore(&dev->mmio.irq_lock, flags); in mt76_set_irq_mask()
117 dev->mmio.regs = regs; in mt76_mmio_init()
119 spin_lock_init(&dev->mmio.irq_lock); in mt76_mmio_init()