Lines Matching refs:trans
23 #include "iwl-trans.h"
40 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
46 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
70 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
74 IWL_ERR(trans, "iwlwifi device config registers:\n");
84 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
86 *ptr = iwl_read32(trans, i);
95 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
114 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
131 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
152 IWL_ERR(trans, "Read failed at 0x%X\n", i);
158 int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, bool retake_ownership)
161 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
162 iwl_set_bit(trans, CSR_GP_CNTRL,
166 iwl_set_bit(trans, CSR_RESET,
172 return iwl_pcie_prepare_card_hw(trans);
177 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
179 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
184 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
192 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
195 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
209 block = dma_alloc_coherent(trans->dev, size, &physical,
214 IWL_INFO(trans,
224 IWL_ERR(trans,
234 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
248 iwl_pcie_alloc_fw_monitor_block(trans, max_power);
251 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
253 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
255 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
258 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
260 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
261 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
265 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
267 if (trans->cfg->apmg_not_supported)
270 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
271 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
275 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
283 void iwl_pcie_apm_config(struct iwl_trans *trans)
285 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
294 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
297 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
300 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
301 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
303 trans->ltr_enabled ? "En" : "Dis");
311 static int iwl_pcie_apm_init(struct iwl_trans *trans)
315 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
323 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
324 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
331 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
335 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
341 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
344 iwl_pcie_apm_config(trans);
347 if (trans->trans_cfg->base_params->pll_cfg)
348 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
350 ret = iwl_finish_nic_init(trans);
354 if (trans->cfg->host_interrupt_operation_mode) {
369 iwl_read_prph(trans, OSC_CLK);
370 iwl_read_prph(trans, OSC_CLK);
371 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
372 iwl_read_prph(trans, OSC_CLK);
373 iwl_read_prph(trans, OSC_CLK);
383 if (!trans->cfg->apmg_not_supported) {
384 iwl_write_prph(trans, APMG_CLK_EN_REG,
389 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
393 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
397 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
409 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
417 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
420 ret = iwl_trans_pcie_sw_reset(trans, true);
423 ret = iwl_finish_nic_init(trans);
427 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
436 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
443 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
445 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
449 ret = iwl_trans_pcie_sw_reset(trans, true);
451 IWL_ERR(trans,
455 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
456 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
461 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
462 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
469 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
476 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
479 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
483 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
488 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
493 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
499 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
500 iwl_set_bit(trans, CSR_GP_CNTRL,
503 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
509 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
511 ret = iwl_poll_bit(trans, CSR_RESET,
517 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
519 IWL_DEBUG_INFO(trans, "stop master\n");
522 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
524 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
527 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
528 iwl_pcie_apm_init(trans);
531 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
532 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
534 else if (trans->trans_cfg->device_family >=
536 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
538 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
542 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
548 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
551 iwl_pcie_apm_stop_master(trans);
553 if (trans->cfg->lp_xtal_workaround) {
554 iwl_pcie_apm_lp_xtal_enable(trans);
558 iwl_trans_pcie_sw_reset(trans, false);
564 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
567 static int iwl_pcie_nic_init(struct iwl_trans *trans)
569 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
574 ret = iwl_pcie_apm_init(trans);
580 iwl_pcie_set_pwr(trans, false);
582 iwl_op_mode_nic_config(trans->op_mode);
585 ret = iwl_pcie_rx_init(trans);
590 if (iwl_pcie_tx_init(trans)) {
591 iwl_pcie_rx_free(trans);
595 if (trans->trans_cfg->base_params->shadow_reg_enable) {
597 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
598 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
607 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
611 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
615 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
621 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
623 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
628 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
633 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
635 ret = iwl_pcie_set_hw_ready(trans);
638 trans->csme_own = false;
642 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
650 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
654 ret = iwl_pcie_set_hw_ready(trans);
656 trans->csme_own = false;
661 IWL_DEBUG_INFO(trans,
663 trans->csme_own = true;
664 if (trans->trans_cfg->device_family !=
666 IWL_ERR(trans,
678 IWL_ERR(trans, "Couldn't prepare the card\n");
686 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
690 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
693 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
696 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
699 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
703 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
708 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
714 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
718 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
723 if (!iwl_trans_grab_nic_access(trans))
726 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
728 iwl_trans_release_nic_access(trans);
733 IWL_ERR(trans, "Failed to load firmware chunk!\n");
734 iwl_trans_pcie_dump_regs(trans);
741 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
749 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
752 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
755 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
757 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
775 iwl_set_bits_prph(trans, LMPM_CHICK,
779 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
783 iwl_clear_bits_prph(trans, LMPM_CHICK,
787 IWL_ERR(trans,
794 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
798 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
827 IWL_DEBUG_FW(trans,
833 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
838 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
840 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
847 iwl_enable_interrupts(trans);
849 if (trans->trans_cfg->gen2) {
851 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
854 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
858 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
861 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
868 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
893 IWL_DEBUG_FW(trans,
899 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
909 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
913 &trans->dbg.fw_mon_cfg[alloc_id];
916 if (!iwl_trans_dbg_ini_valid(trans))
921 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
923 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
931 !trans->dbg.fw_mon_ini[alloc_id].num_frags)
934 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
936 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
939 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
941 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
946 void iwl_pcie_apply_destination(struct iwl_trans *trans)
948 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
949 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
952 if (iwl_trans_dbg_ini_valid(trans)) {
953 iwl_pcie_apply_destination_ini(trans);
957 IWL_INFO(trans, "Applying debug destination %s\n",
961 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
963 IWL_WARN(trans, "PCI should have external buffer debug\n");
965 for (i = 0; i < trans->dbg.n_dest_reg; i++) {
971 iwl_write32(trans, addr, val);
974 iwl_set_bit(trans, addr, BIT(val));
977 iwl_clear_bit(trans, addr, BIT(val));
980 iwl_write_prph(trans, addr, val);
983 iwl_set_bits_prph(trans, addr, BIT(val));
986 iwl_clear_bits_prph(trans, addr, BIT(val));
989 if (iwl_read_prph(trans, addr) & BIT(val)) {
990 IWL_ERR(trans,
997 IWL_ERR(trans, "FW debug - unknown OP %d\n",
1005 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
1007 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1008 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
1012 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
1018 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
1024 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1028 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1034 iwl_write_prph(trans,
1039 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1045 if (iwl_pcie_dbg_on(trans))
1046 iwl_pcie_apply_destination(trans);
1048 iwl_enable_interrupts(trans);
1051 iwl_write32(trans, CSR_RESET, 0);
1056 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1062 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1065 if (iwl_pcie_dbg_on(trans))
1066 iwl_pcie_apply_destination(trans);
1068 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1069 iwl_read_prph(trans, WFPM_GP2));
1076 iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1080 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1083 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1089 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1093 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
1095 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1096 bool hw_rfkill = iwl_is_rfkill_set(trans);
1097 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1101 set_bit(STATUS_RFKILL_HW, &trans->status);
1102 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1104 clear_bit(STATUS_RFKILL_HW, &trans->status);
1106 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1109 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1112 iwl_trans_pcie_rf_kill(trans, report, false);
1159 static void iwl_pcie_map_list(struct iwl_trans *trans,
1166 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1167 iwl_clear_bit(trans, causes[i].mask_reg,
1172 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1174 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1181 iwl_pcie_map_list(trans, causes_list_common,
1183 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1184 iwl_pcie_map_list(trans, causes_list_bz,
1187 iwl_pcie_map_list(trans, causes_list_pre_bz,
1191 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1193 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1205 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1206 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1210 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1215 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1218 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1223 struct iwl_trans *trans = trans_pcie->trans;
1226 if (trans->trans_cfg->mq_rx_supported &&
1227 test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1228 iwl_write_umac_prph(trans, UREG_CHICK,
1237 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1238 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1247 iwl_pcie_map_rx_causes(trans);
1249 iwl_pcie_map_non_rx_causes(trans);
1254 struct iwl_trans *trans = trans_pcie->trans;
1261 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1263 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1267 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool from_irq)
1269 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1279 iwl_disable_interrupts(trans);
1282 iwl_pcie_disable_ict(trans);
1291 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1292 IWL_DEBUG_INFO(trans,
1295 iwl_pcie_synchronize_irqs(trans);
1296 iwl_pcie_rx_napi_sync(trans);
1297 iwl_pcie_tx_stop(trans);
1298 iwl_pcie_rx_stop(trans);
1301 if (!trans->cfg->apmg_not_supported) {
1302 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1309 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1310 iwl_clear_bit(trans, CSR_GP_CNTRL,
1313 iwl_clear_bit(trans, CSR_GP_CNTRL,
1317 iwl_pcie_apm_stop(trans, false);
1320 iwl_trans_pcie_sw_reset(trans, true);
1338 iwl_disable_interrupts(trans);
1341 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1342 clear_bit(STATUS_INT_ENABLED, &trans->status);
1343 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1349 iwl_enable_rfkill_int(trans);
1352 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1354 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1366 int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1369 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1374 if (iwl_pcie_prepare_card_hw(trans)) {
1375 IWL_WARN(trans, "Exit HW not ready\n");
1379 iwl_enable_rfkill_int(trans);
1381 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1388 iwl_disable_interrupts(trans);
1391 iwl_pcie_synchronize_irqs(trans);
1396 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1404 IWL_WARN(trans,
1411 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1412 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1416 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1418 ret = iwl_pcie_nic_init(trans);
1420 IWL_ERR(trans, "Unable to init nic\n");
1431 iwl_enable_fw_load_int(trans);
1434 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1435 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1438 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1439 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1441 ret = iwl_pcie_load_given_ucode(trans, fw);
1444 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1453 void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1455 iwl_pcie_reset_ict(trans);
1456 iwl_pcie_tx_start(trans, scd_addr);
1459 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1476 hw_rfkill = iwl_is_rfkill_set(trans);
1478 set_bit(STATUS_RFKILL_HW, &trans->status);
1479 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1481 clear_bit(STATUS_RFKILL_HW, &trans->status);
1482 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1485 iwl_trans_pcie_rf_kill(trans, hw_rfkill, false);
1488 void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1490 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1493 iwl_op_mode_time_point(trans->op_mode,
1499 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1500 _iwl_trans_pcie_stop_device(trans, false);
1501 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1505 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state, bool from_irq)
1508 IWL_TRANS_GET_PCIE_TRANS(trans);
1512 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1514 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state) &&
1515 !WARN_ON(trans->trans_cfg->gen2))
1516 _iwl_trans_pcie_stop_device(trans, from_irq);
1519 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1522 iwl_disable_interrupts(trans);
1531 iwl_pcie_disable_ict(trans);
1533 iwl_pcie_synchronize_irqs(trans);
1535 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
1536 iwl_clear_bit(trans, CSR_GP_CNTRL,
1538 iwl_clear_bit(trans, CSR_GP_CNTRL,
1541 iwl_clear_bit(trans, CSR_GP_CNTRL,
1543 iwl_clear_bit(trans, CSR_GP_CNTRL,
1553 iwl_trans_pcie_tx_reset(trans);
1556 iwl_pcie_set_pwr(trans, true);
1559 static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend)
1561 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1564 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
1565 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1568 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1569 iwl_write32(trans, CSR_IPC_SLEEP_CONTROL,
1582 IWL_ERR(trans, "Timeout %s D3\n",
1590 int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, bool reset)
1596 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1599 ret = iwl_pcie_d3_handshake(trans, true);
1603 iwl_pcie_d3_complete_suspend(trans, test, reset);
1608 int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1612 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1617 iwl_enable_interrupts(trans);
1623 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1624 iwl_set_bit(trans, CSR_GP_CNTRL,
1627 iwl_set_bit(trans, CSR_GP_CNTRL,
1630 ret = iwl_finish_nic_init(trans);
1643 iwl_pcie_reset_ict(trans);
1644 iwl_enable_interrupts(trans);
1646 iwl_pcie_set_pwr(trans, false);
1649 iwl_clear_bit(trans, CSR_GP_CNTRL,
1652 iwl_trans_pcie_tx_reset(trans);
1654 ret = iwl_pcie_rx_init(trans);
1656 IWL_ERR(trans,
1662 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1663 iwl_read_umac_prph(trans, WFPM_GP2));
1665 val = iwl_read32(trans, CSR_RESET);
1673 ret = iwl_pcie_d3_handshake(trans, false);
1680 struct iwl_trans *trans,
1683 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1702 IWL_DEBUG_INFO(trans,
1709 IWL_DEBUG_INFO(trans,
1721 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1725 trans_pcie->trans->num_rx_queues = num_irqs;
1728 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1731 IWL_DEBUG_INFO(trans,
1733 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask);
1735 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
1754 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1758 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1761 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1773 IWL_ERR(trans_pcie->trans,
1804 IWL_ERR(trans_pcie->trans,
1810 iwl_pcie_irq_set_affinity(trans_pcie->trans);
1815 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
1819 switch (trans->trans_cfg->device_family) {
1830 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
1832 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
1835 IWL_ERR(trans,
1839 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1846 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1850 ret = iwl_finish_nic_init(trans);
1854 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1857 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1861 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
1864 return iwl_trans_pcie_sw_reset(trans, true);
1867 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1869 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1874 err = iwl_pcie_prepare_card_hw(trans);
1876 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1880 err = iwl_trans_pcie_clear_persistence_bit(trans);
1884 err = iwl_trans_pcie_sw_reset(trans, true);
1888 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
1889 trans->trans_cfg->integrated) {
1890 err = iwl_pcie_gen2_force_power_gating(trans);
1895 err = iwl_pcie_apm_init(trans);
1902 iwl_enable_rfkill_int(trans);
1910 iwl_pcie_check_hw_rf_kill(trans);
1915 int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1917 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1921 ret = _iwl_trans_pcie_start_hw(trans);
1927 void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1929 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1934 iwl_disable_interrupts(trans);
1936 iwl_pcie_apm_stop(trans, true);
1938 iwl_disable_interrupts(trans);
1940 iwl_pcie_disable_ict(trans);
1944 iwl_pcie_synchronize_irqs(trans);
1948 void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1950 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1953 void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1955 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1958 u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1960 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1963 void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1966 IWL_DEBUG_PCI_RW(trans, "W1 %#010x %#04x\n", ofs, val);
1967 bus_write_1((struct resource *)IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base, ofs, val);
1970 void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1973 IWL_DEBUG_PCI_RW(trans, "W4 %#010x %#010x\n", ofs, val);
1974 bus_write_4((struct resource *)IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base, ofs, val);
1977 u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1981 v = bus_read_4((struct resource *)IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base, ofs);
1982 IWL_DEBUG_PCI_RW(trans, "R4 %#010x %#010x\n", ofs, v);
1987 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1989 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1995 u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1997 u32 mask = iwl_trans_pcie_prph_msk(trans);
1999 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
2001 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
2004 void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
2006 u32 mask = iwl_trans_pcie_prph_msk(trans);
2008 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
2010 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
2013 void iwl_trans_pcie_configure(struct iwl_trans *trans,
2016 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2019 iwl_pcie_free_rbs_pool(trans);
2042 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
2048 trans->command_groups = trans_cfg->command_groups;
2049 trans->command_groups_size = trans_cfg->command_groups_size;
2078 static void iwl_pcie_free_invalid_tx_cmd(struct iwl_trans *trans)
2080 iwl_pcie_free_dma_ptr(trans, &trans->invalid_tx_cmd);
2083 static int iwl_pcie_alloc_invalid_tx_cmd(struct iwl_trans *trans)
2094 ret = iwl_pcie_alloc_dma_ptr(trans, &trans->invalid_tx_cmd,
2098 memcpy(trans->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd));
2102 void iwl_trans_pcie_free(struct iwl_trans *trans)
2104 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2107 iwl_pcie_synchronize_irqs(trans);
2109 if (trans->trans_cfg->gen2)
2110 iwl_txq_gen2_tx_free(trans);
2112 iwl_pcie_tx_free(trans);
2113 iwl_pcie_rx_free(trans);
2129 iwl_pcie_free_ict(trans);
2134 iwl_pcie_free_invalid_tx_cmd(trans);
2136 iwl_pcie_free_fw_monitor(trans);
2139 trans->dev);
2141 trans->dev);
2159 iwl_trans_free(trans);
2205 void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan)
2209 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2212 IWL_ERR(trans, "Device gone - scheduling removal!\n");
2213 iwl_pcie_dump_csr(trans);
2222 IWL_ERR(trans,
2234 * the trans will be freed and reallocated.
2236 set_bit(STATUS_TRANS_DEAD, &trans->status);
2238 removal->pdev = to_pci_dev(trans->dev);
2250 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
2253 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2259 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2267 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
2274 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write);
2275 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
2298 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000);
2300 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2306 iwl_trans_pcie_dump_regs(trans);
2309 iwl_trans_pcie_remove(trans, false);
2311 iwl_write32(trans, CSR_RESET,
2327 bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
2332 ret = __iwl_trans_pcie_grab_nic_access(trans);
2341 void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
2343 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2355 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
2356 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2359 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2371 int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2384 if (iwl_trans_grab_nic_access(trans)) {
2385 iwl_write32(trans, HBUS_TARG_MEM_RADDR,
2389 vals[offs] = iwl_read32(trans,
2398 iwl_trans_release_nic_access(trans);
2409 iwl_trans_release_nic_access(trans);
2421 int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
2427 if (iwl_trans_grab_nic_access(trans)) {
2428 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2430 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2432 iwl_trans_release_nic_access(trans);
2439 int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
2442 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev,
2448 int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2451 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2453 if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2464 int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2466 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2473 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2479 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2498 * trans layer (overflow TX) don't warn.
2515 IWL_ERR(trans,
2517 iwl_txq_log_scd_error(trans, txq);
2521 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2526 int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2528 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2534 cnt < trans->trans_cfg->base_params->num_of_queues;
2544 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2552 void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2555 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2558 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2596 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2625 IWL_ERR(trans, "CSR values:\n");
2626 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2629 IWL_ERR(trans, " %25s: 0X%08x\n",
2631 iwl_read32(trans, csr_tbl[i]));
2638 debugfs_create_file(#name, mode, parent, trans, \
2666 struct iwl_trans *trans;
2678 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2696 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2711 struct iwl_trans *trans = priv->trans;
2712 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2752 priv->trans = inode->i_private;
2760 struct iwl_trans *trans = file->private_data;
2761 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2766 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2775 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2791 u32 r = iwl_get_closed_rb_stts(trans, rxq);
2809 struct iwl_trans *trans = file->private_data;
2810 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2867 struct iwl_trans *trans = file->private_data;
2868 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2886 struct iwl_trans *trans = file->private_data;
2888 iwl_pcie_dump_csr(trans);
2897 struct iwl_trans *trans = file->private_data;
2901 ret = iwl_dump_fh(trans, &buf);
2915 struct iwl_trans *trans = file->private_data;
2916 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2922 !(iwl_read32(trans, CSR_GP_CNTRL) &
2932 struct iwl_trans *trans = file->private_data;
2933 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2942 IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2945 iwl_pcie_handle_rfkill_irq(trans, false);
2953 struct iwl_trans *trans = inode->i_private;
2954 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2956 if (!trans->dbg.dest_tlv ||
2957 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
2958 IWL_ERR(trans, "Debug destination is not set to DRAM\n");
3002 struct iwl_trans *trans = file->private_data;
3003 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3004 u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;
3010 if (trans->dbg.dest_tlv) {
3012 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3013 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3019 if (unlikely(!trans->dbg.rec_on))
3030 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
3031 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
3043 size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
3061 IWL_WARN(trans,
3065 IWL_WARN(trans,
3085 struct iwl_trans *trans = file->private_data;
3086 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3118 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
3120 struct dentry *dir = trans->dbgfs_dir;
3132 void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
3134 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3143 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
3145 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3150 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i);
3155 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
3159 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3167 r = iwl_get_closed_rb_stts(trans, rxq);
3175 dma_sync_single_for_cpu(trans->dev, rxb->page_dma,
3195 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
3207 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3214 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
3221 if (!iwl_trans_grab_nic_access(trans))
3228 if (!trans->trans_cfg->gen2)
3231 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3233 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
3234 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
3236 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
3239 iwl_trans_release_nic_access(trans);
3247 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3255 if (!iwl_trans_grab_nic_access(trans))
3258 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
3260 buffer[i] = iwl_read_umac_prph_no_grab(trans,
3262 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
3264 iwl_trans_release_nic_access(trans);
3270 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3275 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3280 } else if (trans->dbg.dest_tlv) {
3281 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3282 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3283 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3290 write_ptr_val = iwl_read_prph(trans, write_ptr);
3292 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3294 cpu_to_le32(iwl_read_prph(trans, base));
3295 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3297 cpu_to_le32(iwl_read_prph(trans, base_high));
3306 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3310 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
3313 if (trans->dbg.dest_tlv ||
3315 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3316 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
3322 iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
3328 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
3334 if (trans->dbg.dest_tlv->version) {
3335 base = (iwl_read_prph(trans, base) &
3337 trans->dbg.dest_tlv->base_shift;
3339 base += trans->cfg->smem_offset;
3341 base = iwl_read_prph(trans, base) <<
3342 trans->dbg.dest_tlv->base_shift;
3345 iwl_trans_read_mem(trans, base, fw_mon_data->data,
3347 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
3349 iwl_trans_pci_dump_marbh_monitor(trans,
3364 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
3366 if (trans->dbg.fw_mon.size) {
3369 trans->dbg.fw_mon.size;
3370 return trans->dbg.fw_mon.size;
3371 } else if (trans->dbg.dest_tlv) {
3374 if (trans->dbg.dest_tlv->version == 1) {
3375 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3376 cfg_reg = iwl_read_prph(trans, cfg_reg);
3378 trans->dbg.dest_tlv->base_shift;
3380 base += trans->cfg->smem_offset;
3384 trans->dbg.dest_tlv->end_shift;
3387 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3388 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
3390 base = iwl_read_prph(trans, base) <<
3391 trans->dbg.dest_tlv->base_shift;
3392 end = iwl_read_prph(trans, end) <<
3393 trans->dbg.dest_tlv->end_shift;
3396 if (trans->trans_cfg->device_family >=
3398 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3399 end += (1 << trans->dbg.dest_tlv->end_shift);
3411 iwl_trans_pcie_dump_data(struct iwl_trans *trans, u32 dump_mask,
3415 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3422 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
3423 !trans->trans_cfg->mq_rx_supported &&
3440 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
3448 if (trans->trans_cfg->gen2)
3450 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3451 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
3462 num_rbs = iwl_get_closed_rb_stts(trans, rxq);
3470 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
3471 for (i = 0; i < trans->init_dram.paging_cnt; i++)
3474 trans->init_dram.paging[i].size;
3495 if (trans->trans_cfg->gen2)
3500 cmdlen = iwl_trans_pcie_get_cmdlen(trans,
3518 ptr = iwl_txq_dec_wrap(trans, ptr);
3528 len += iwl_trans_pcie_dump_csr(trans, &data);
3530 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
3532 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
3535 if (trans->trans_cfg->gen2 &&
3537 for (i = 0; i < trans->init_dram.paging_cnt; i++) {
3539 u32 page_len = trans->init_dram.paging[i].size;
3546 trans->init_dram.paging[i].block, page_len);
3553 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3560 void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable)
3563 iwl_enable_interrupts(trans);
3565 iwl_disable_interrupts(trans);
3568 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
3571 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3575 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
3584 iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit);
3592 struct iwl_trans *trans;
3609 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev,
3611 if (!trans)
3614 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3616 if (trans->trans_cfg->gen2) {
3625 trans->max_skb_frags = IWL_TRANS_PCIE_MAX_FRAGS(trans_pcie);
3635 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
3638 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
3648 if (trans->trans_cfg->gen2) {
3650 dmam_pool_create("iwlwifi:bc", trans->dev,
3661 (trans->trans_cfg->gen2 ? 64 : 36));
3675 trans_pcie->trans = trans;
3747 iwl_disable_interrupts(trans);
3749 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3750 if (trans->hw_rev == 0xffffffff) {
3763 trans->hw_rev_step = trans->hw_rev & 0xF;
3765 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2;
3767 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3769 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);
3770 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3771 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3776 ret = iwl_pcie_alloc_invalid_tx_cmd(trans);
3785 ret = iwl_pcie_alloc_ict(trans);
3792 IRQF_SHARED, DRV_NAME, trans);
3794 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3804 iwl_dbg_tlv_init(trans);
3806 return trans;
3809 iwl_pcie_free_ict(trans);
3819 iwl_trans_free(trans);
3823 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans,
3826 iwl_write_prph(trans, IMR_UREG_CHICK,
3827 iwl_read_prph(trans, IMR_UREG_CHICK) |
3829 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr);
3830 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB,
3832 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB,
3834 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt);
3835 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL,
3841 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,
3844 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3848 iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt);
3853 IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n");
3854 iwl_trans_pcie_dump_regs(trans);