Lines Matching refs:trans
144 int iwl_pcie_rx_stop(struct iwl_trans *trans)
146 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
148 iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0);
149 return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_GEN3,
151 } else if (trans->trans_cfg->mq_rx_supported) {
152 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0);
153 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS,
156 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
157 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
166 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
178 if (!trans->trans_cfg->base_params->shadow_reg_enable &&
179 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
180 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
183 IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n",
185 iwl_set_bit(trans, CSR_GP_CNTRL,
193 if (!trans->trans_cfg->mq_rx_supported)
194 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
195 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
196 iwl_write32(trans, HBUS_TARG_WRPTR, rxq->write_actual |
199 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),
203 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans)
205 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
208 for (i = 0; i < trans->num_rx_queues; i++) {
214 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
220 static void iwl_pcie_restock_bd(struct iwl_trans *trans,
224 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
238 IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n",
240 IWL_DEBUG_PCI_RW(trans, "Assigned virtual RB ID %u to queue %d index %d\n",
248 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans,
251 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
262 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
275 iwl_pcie_restock_bd(trans, rxq, rxb);
287 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
295 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans,
308 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
336 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
353 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq)
355 if (trans->trans_cfg->mq_rx_supported)
356 iwl_pcie_rxmq_restock(trans, rxq);
358 iwl_pcie_rxsq_restock(trans, rxq);
365 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans,
368 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
398 IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n",
405 IWL_CRIT(trans,
433 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
436 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
450 page = iwl_pcie_rx_alloc_page(trans, &offset, priority);
471 dma_map_page(trans->dev, page, rxb->offset,
474 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
492 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans)
494 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
503 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma,
517 static void iwl_pcie_rx_allocator(struct iwl_trans *trans)
519 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
524 IWL_DEBUG_TPT(trans, "Pending allocation requests = %d\n", pending);
557 page = iwl_pcie_rx_alloc_page(trans, &rxb->offset,
564 rxb->page_dma = dma_map_page(trans->dev, page,
568 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
585 IWL_DEBUG_TPT(trans,
606 IWL_DEBUG_TPT(trans, "%s, exit.\n", __func__);
617 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans,
620 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
659 iwl_pcie_rx_allocator(trans_pcie->trans);
662 static int iwl_pcie_free_bd_size(struct iwl_trans *trans)
664 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
667 return trans->trans_cfg->mq_rx_supported ?
671 static int iwl_pcie_used_bd_size(struct iwl_trans *trans)
673 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
676 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
682 static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans,
685 int free_size = iwl_pcie_free_bd_size(trans);
688 dma_free_coherent(trans->dev,
698 dma_free_coherent(trans->dev,
699 iwl_pcie_used_bd_size(trans) *
706 static size_t iwl_pcie_rb_stts_size(struct iwl_trans *trans)
708 bool use_rx_td = (trans->trans_cfg->device_family >=
717 static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans,
720 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
721 size_t rb_stts_size = iwl_pcie_rb_stts_size(trans);
722 struct device *dev = trans->dev;
727 if (trans->trans_cfg->mq_rx_supported)
728 rxq->queue_size = trans->cfg->num_rbds;
732 free_size = iwl_pcie_free_bd_size(trans);
743 if (trans->trans_cfg->mq_rx_supported) {
745 iwl_pcie_used_bd_size(trans) *
760 for (i = 0; i < trans->num_rx_queues; i++) {
763 iwl_pcie_free_rxq_dma(trans, rxq);
769 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
771 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
772 size_t rb_stts_size = iwl_pcie_rb_stts_size(trans);
779 trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq),
801 dma_alloc_coherent(trans->dev,
802 rb_stts_size * trans->num_rx_queues,
810 for (i = 0; i < trans->num_rx_queues; i++) {
814 ret = iwl_pcie_alloc_rxq_dma(trans, rxq);
822 dma_free_coherent(trans->dev,
823 rb_stts_size * trans->num_rx_queues,
839 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
841 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
860 if (!iwl_trans_grab_nic_access(trans))
864 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
866 iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
867 iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
868 iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
871 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
874 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
878 iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
889 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
897 iwl_trans_release_nic_access(trans);
900 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
903 if (trans->cfg->host_interrupt_operation_mode)
904 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
907 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
909 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
931 if (!iwl_trans_grab_nic_access(trans))
935 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);
937 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);
939 for (i = 0; i < trans->num_rx_queues; i++) {
941 iwl_write_prph64_no_grab(trans,
945 iwl_write_prph64_no_grab(trans,
949 iwl_write_prph64_no_grab(trans,
953 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);
954 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);
955 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);
967 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,
978 iwl_write_prph_no_grab(trans, RFH_GEN_CFG,
983 trans->trans_cfg->integrated ?
987 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);
989 iwl_trans_release_nic_access(trans);
992 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
1005 static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget);
1016 struct iwl_trans *trans;
1020 trans = trans_pcie->trans;
1022 ret = iwl_pcie_rx_handle(trans, rxq->id, budget);
1024 IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n",
1029 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1030 _iwl_enable_interrupts(trans);
1043 struct iwl_trans *trans;
1047 trans = trans_pcie->trans;
1049 ret = iwl_pcie_rx_handle(trans, rxq->id, budget);
1050 IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n", rxq->id, ret,
1062 iwl_pcie_clear_irq(trans, irq_line);
1071 void iwl_pcie_rx_napi_sync(struct iwl_trans *trans)
1073 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1079 for (i = 0; i < trans->num_rx_queues; i++) {
1087 static int _iwl_pcie_rx_init(struct iwl_trans *trans)
1089 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1095 err = iwl_pcie_rx_alloc(trans);
1111 iwl_pcie_free_rbs_pool(trans);
1116 for (i = 0; i < trans->num_rx_queues; i++) {
1129 (trans->trans_cfg->device_family >=
1151 queue_size = trans->trans_cfg->mq_rx_supported ?
1153 allocator_pool_size = trans->num_rx_queues *
1169 iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq);
1174 int iwl_pcie_rx_init(struct iwl_trans *trans)
1176 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1177 int ret = _iwl_pcie_rx_init(trans);
1182 if (trans->trans_cfg->mq_rx_supported)
1183 iwl_pcie_rx_mq_hw_init(trans);
1185 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq);
1187 iwl_pcie_rxq_restock(trans, trans_pcie->rxq);
1190 iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq);
1196 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans)
1199 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
1205 return _iwl_pcie_rx_init(trans);
1208 void iwl_pcie_rx_free(struct iwl_trans *trans)
1210 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1211 size_t rb_stts_size = iwl_pcie_rb_stts_size(trans);
1220 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
1226 iwl_pcie_free_rbs_pool(trans);
1229 dma_free_coherent(trans->dev,
1230 rb_stts_size * trans->num_rx_queues,
1237 for (i = 0; i < trans->num_rx_queues; i++) {
1240 iwl_pcie_free_rxq_dma(trans, rxq);
1269 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans,
1273 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1301 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
1307 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1316 dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
1333 IWL_DEBUG_RX(trans,
1346 IWL_DEBUG_RX(trans,
1349 iwl_get_cmd_string(trans,
1363 maybe_trace_iwlwifi_dev_rx(trans, pkt, len);
1385 iwl_op_mode_rx(trans->op_mode, &rxq->napi,
1388 iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi,
1409 iwl_pcie_hcmd_complete(trans, &rxcb);
1411 IWL_WARN(trans, "Claim null rxb?\n");
1415 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1430 dma_map_page(trans->dev, rxb->page, rxb->offset,
1433 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
1441 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1447 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1450 static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans,
1454 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1461 if (!trans->trans_cfg->mq_rx_supported) {
1467 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
1472 } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1490 IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid);
1498 iwl_force_nmi(trans);
1505 static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget)
1507 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1521 r = iwl_get_closed_rb_stts(trans, rxq);
1529 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r);
1544 IWL_DEBUG_TPT(trans,
1549 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i);
1551 rxb = iwl_pcie_get_rxb(trans, rxq, i, &join);
1572 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i);
1585 iwl_pcie_rx_allocator_get(trans, rxq);
1595 IWL_DEBUG_TPT(trans,
1603 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1604 iwl_pcie_rxq_restock(trans, rxq);
1627 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1629 iwl_pcie_rxq_restock(trans, rxq);
1650 struct iwl_trans *trans = trans_pcie->trans;
1653 trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0);
1655 if (WARN_ON(entry->entry >= trans->num_rx_queues))
1660 IWL_ERR(trans,
1667 lock_map_acquire(&trans->sync_cmd_lockdep_map);
1668 IWL_DEBUG_ISR(trans, "[%d] Got interrupt\n", entry->entry);
1672 iwl_pcie_clear_irq(trans, entry->entry);
1675 lock_map_release(&trans->sync_cmd_lockdep_map);
1683 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
1685 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1689 if (trans->cfg->internal_wimax_coex &&
1690 !trans->cfg->apmg_not_supported &&
1691 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
1693 (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
1695 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1696 iwl_op_mode_wimax_active(trans->op_mode);
1697 wake_up(&trans->wait_command_queue);
1701 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
1709 iwl_trans_fw_error(trans, false);
1711 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1712 wake_up(&trans->wait_command_queue);
1715 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans)
1719 lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock);
1721 trace_iwlwifi_dev_irq(trans->dev);
1724 inta = iwl_read32(trans, CSR_INT);
1743 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans)
1745 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1750 trace_iwlwifi_dev_irq(trans->dev);
1756 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1766 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1773 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1795 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans, bool from_irq)
1797 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1802 prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1803 hw_rfkill = iwl_is_rfkill_set(trans);
1805 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1806 set_bit(STATUS_RFKILL_HW, &trans->status);
1811 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1813 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1819 iwl_trans_pcie_rf_kill(trans, report, from_irq);
1824 &trans->status))
1825 IWL_DEBUG_RF_KILL(trans,
1827 wake_up(&trans->wait_command_queue);
1829 clear_bit(STATUS_RFKILL_HW, &trans->status);
1831 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1837 struct iwl_trans *trans = dev_id;
1838 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1844 lock_map_acquire(&trans->sync_cmd_lockdep_map);
1852 inta = iwl_pcie_int_cause_ict(trans);
1854 inta = iwl_pcie_int_cause_non_ict(trans);
1858 IWL_DEBUG_ISR(trans,
1861 iwl_read32(trans, CSR_INT_MASK),
1862 iwl_read32(trans, CSR_FH_INT_STATUS));
1864 IWL_DEBUG_ISR(trans,
1878 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1883 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1884 _iwl_enable_interrupts(trans);
1886 lock_map_release(&trans->sync_cmd_lockdep_map);
1895 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1911 iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
1915 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
1916 inta, iwl_read32(trans, CSR_INT_MASK));
1923 IWL_ERR(trans, "Hardware error detected. Restarting.\n");
1926 iwl_disable_interrupts(trans);
1929 iwl_pcie_irq_handle_error(trans);
1938 IWL_DEBUG_ISR(trans,
1945 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1947 if (trans->trans_cfg->gen2) {
1952 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
1963 iwl_pcie_handle_rfkill_irq(trans, true);
1969 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1976 IWL_ERR(trans, "Microcode SW error detected. "
1979 iwl_pcie_irq_handle_error(trans);
1985 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1986 iwl_pcie_rxq_check_wrptr(trans);
1987 iwl_pcie_txq_check_wrptrs(trans);
1999 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
2002 iwl_write32(trans, CSR_FH_INT_STATUS,
2007 iwl_write32(trans,
2022 iwl_write8(trans, CSR_INT_PERIODIC_REG,
2033 iwl_write8(trans, CSR_INT_PERIODIC_REG,
2048 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
2049 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
2063 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
2068 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
2075 if (test_bit(STATUS_INT_ENABLED, &trans->status))
2076 _iwl_enable_interrupts(trans);
2079 iwl_enable_fw_load_int(trans);
2082 iwl_enable_rfkill_int(trans);
2085 iwl_enable_fw_load_int_ctx_info(trans);
2090 lock_map_release(&trans->sync_cmd_lockdep_map);
2101 void iwl_pcie_free_ict(struct iwl_trans *trans)
2103 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2106 dma_free_coherent(trans->dev, ICT_SIZE,
2119 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
2121 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2124 dma_alloc_coherent(trans->dev, ICT_SIZE,
2131 iwl_pcie_free_ict(trans);
2141 void iwl_pcie_reset_ict(struct iwl_trans *trans)
2143 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2150 _iwl_disable_interrupts(trans);
2160 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
2162 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
2165 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
2166 _iwl_enable_interrupts(trans);
2171 void iwl_pcie_disable_ict(struct iwl_trans *trans)
2173 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2182 struct iwl_trans *trans = data;
2184 if (!trans)
2192 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
2206 struct iwl_trans *trans = trans_pcie->trans;
2219 lock_map_acquire(&trans->sync_cmd_lockdep_map);
2222 inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);
2223 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
2227 iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh & inta_fh_msk);
2228 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
2231 trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw);
2234 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
2235 lock_map_release(&trans->sync_cmd_lockdep_map);
2241 IWL_DEBUG_ISR(trans,
2244 iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD));
2246 IWL_DEBUG_ISR(trans,
2277 IWL_DEBUG_ISR(trans, "IMR Complete interrupt\n");
2286 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
2302 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
2308 IWL_ERR(trans, "TOP Fatal error detected, inta_hw=0x%x.\n",
2315 IWL_ERR(trans,
2327 iwl_pcie_irq_handle_error(trans);
2334 IWL_DEBUG_ISR(trans,
2337 iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD));
2339 IWL_DEBUG_ISR(trans,
2349 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
2351 if (trans->trans_cfg->gen2) {
2353 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
2367 IWL_DEBUG_ISR(trans,
2374 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
2375 iwl_pcie_rxq_check_wrptr(trans);
2376 iwl_pcie_txq_check_wrptrs(trans);
2384 IWL_ERR(trans, "Microcode CT kill error detected.\n");
2390 iwl_pcie_handle_rfkill_irq(trans, true);
2393 IWL_ERR(trans,
2397 trans->dbg.hw_error = true;
2398 iwl_pcie_irq_handle_error(trans);
2402 IWL_DEBUG_ISR(trans, "Reset flow completed\n");
2408 iwl_pcie_clear_irq(trans, entry->entry);
2410 lock_map_release(&trans->sync_cmd_lockdep_map);