Lines Matching refs:IWL_DEBUG_ISR
1024 IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n",
1050 IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n", rxq->id, ret,
1668 IWL_DEBUG_ISR(trans, "[%d] Got interrupt\n", entry->entry);
1766 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1858 IWL_DEBUG_ISR(trans,
1864 IWL_DEBUG_ISR(trans,
1878 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1915 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
1938 IWL_DEBUG_ISR(trans,
1945 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1985 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1999 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
2049 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
2160 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
2234 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
2241 IWL_DEBUG_ISR(trans,
2246 IWL_DEBUG_ISR(trans,
2277 IWL_DEBUG_ISR(trans, "IMR Complete interrupt\n");
2286 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
2334 IWL_DEBUG_ISR(trans,
2339 IWL_DEBUG_ISR(trans,
2349 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
2367 IWL_DEBUG_ISR(trans,
2374 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
2402 IWL_DEBUG_ISR(trans, "Reset flow completed\n");