Lines Matching refs:trans
20 #include "iwl-trans.h"
191 * @trans: transport pointer (for configuration)
194 static inline u16 iwl_get_closed_rb_stts(struct iwl_trans *trans,
197 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
356 * @trans: pointer to the generic transport area
439 struct iwl_trans *trans;
524 IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans)
526 return (void *)trans->trans_specific;
529 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, int queue)
539 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue));
550 * Convention: trans API functions: iwl_trans_pcie_XXX
557 void iwl_trans_pcie_free(struct iwl_trans *trans);
561 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans);
562 #define _iwl_trans_pcie_grab_nic_access(trans) \
564 likely(__iwl_trans_pcie_grab_nic_access(trans)))
569 int iwl_pcie_rx_init(struct iwl_trans *trans);
570 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans);
575 int iwl_pcie_rx_stop(struct iwl_trans *trans);
576 void iwl_pcie_rx_free(struct iwl_trans *trans);
577 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans);
579 void iwl_pcie_rx_napi_sync(struct iwl_trans *trans);
580 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
587 int iwl_pcie_alloc_ict(struct iwl_trans *trans);
588 void iwl_pcie_free_ict(struct iwl_trans *trans);
589 void iwl_pcie_reset_ict(struct iwl_trans *trans);
590 void iwl_pcie_disable_ict(struct iwl_trans *trans);
622 int iwl_pcie_tx_init(struct iwl_trans *trans);
623 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
624 int iwl_pcie_tx_stop(struct iwl_trans *trans);
625 void iwl_pcie_tx_free(struct iwl_trans *trans);
626 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
629 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
631 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
633 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
635 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
636 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
638 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
639 int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq,
644 struct sg_table *iwl_pcie_prep_tso(struct iwl_trans *trans, struct sk_buff *skb,
648 void iwl_pcie_free_tso_pages(struct iwl_trans *trans, struct sk_buff *skb,
673 static inline void *iwl_txq_get_tfd(struct iwl_trans *trans,
676 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
678 if (trans->trans_cfg->gen2)
694 int iwl_txq_space(struct iwl_trans *trans, const struct iwl_txq *q);
696 static inline void iwl_txq_stop(struct iwl_trans *trans, struct iwl_txq *txq)
698 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
701 iwl_op_mode_queue_full(trans->op_mode, txq->id);
702 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id);
704 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
711 * @trans: the transport (for configuration data)
714 static inline int iwl_txq_inc_wrap(struct iwl_trans *trans, int index)
717 (trans->trans_cfg->base_params->max_tfd_queue_size - 1);
722 * @trans: the transport (for configuration data)
725 static inline int iwl_txq_dec_wrap(struct iwl_trans *trans, int index)
728 (trans->trans_cfg->base_params->max_tfd_queue_size - 1);
731 void iwl_txq_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq);
734 iwl_trans_pcie_wake_queue(struct iwl_trans *trans, struct iwl_txq *txq)
736 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
739 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id);
740 iwl_op_mode_queue_not_full(trans->op_mode, txq->id);
744 int iwl_txq_gen2_set_tb(struct iwl_trans *trans,
748 static inline void iwl_txq_set_tfd_invalid_gen2(struct iwl_trans *trans,
753 iwl_txq_gen2_set_tb(trans, tfd, trans->invalid_tx_cmd.dma,
754 trans->invalid_tx_cmd.size);
757 void iwl_txq_gen2_tfd_unmap(struct iwl_trans *trans,
761 int iwl_txq_dyn_alloc(struct iwl_trans *trans, u32 flags,
765 int iwl_txq_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
768 void iwl_txq_dyn_free(struct iwl_trans *trans, int queue);
769 void iwl_txq_gen2_tx_free(struct iwl_trans *trans);
770 int iwl_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
772 int iwl_txq_gen2_init(struct iwl_trans *trans, int txq_id,
775 static inline u16 iwl_txq_gen1_tfd_tb_get_len(struct iwl_trans *trans,
781 if (trans->trans_cfg->gen2) {
794 void iwl_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
796 void iwl_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr);
797 void iwl_pcie_freeze_txq_timer(struct iwl_trans *trans,
799 int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx);
800 int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm);
805 void iwl_pcie_dump_csr(struct iwl_trans *trans);
810 static inline void _iwl_disable_interrupts(struct iwl_trans *trans)
812 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
814 clear_bit(STATUS_INT_ENABLED, &trans->status);
817 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
821 iwl_write32(trans, CSR_INT, 0xffffffff);
822 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
825 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
827 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
830 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
848 static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans)
850 struct iwl_self_init_dram *dram = &trans->init_dram;
859 dma_free_coherent(trans->dev, dram->fw[i].size,
867 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
869 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
872 _iwl_disable_interrupts(trans);
876 static inline void _iwl_enable_interrupts(struct iwl_trans *trans)
878 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
880 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
881 set_bit(STATUS_INT_ENABLED, &trans->status);
884 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
892 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
894 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
899 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
901 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
904 _iwl_enable_interrupts(trans);
907 static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk)
909 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
911 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);
915 static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk)
917 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
919 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);
923 static inline void iwl_enable_fw_load_int(struct iwl_trans *trans)
925 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
927 IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n");
930 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
932 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
934 iwl_enable_fh_int_msk_msix(trans,
939 static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans)
941 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
943 IWL_DEBUG_ISR(trans, "Enabling ALIVE interrupt only\n");
954 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
956 iwl_enable_hw_int_msk_msix(trans,
962 iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask);
989 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
991 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
993 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
996 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
998 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
1000 iwl_enable_hw_int_msk_msix(trans,
1004 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) {
1010 iwl_set_bit(trans, CSR_GP_CNTRL,
1015 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans, bool from_irq);
1017 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
1019 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1026 return !(iwl_read32(trans, CSR_GP_CNTRL) &
1030 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
1039 v = iwl_read32(trans, reg);
1042 iwl_write32(trans, reg, v);
1045 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
1048 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
1051 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
1054 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
1057 static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans)
1059 return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans));
1062 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state, bool from_irq);
1063 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans);
1066 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans);
1067 void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans);
1069 static inline void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) { }
1074 /* common trans ops for all generations transports */
1075 void iwl_trans_pcie_configure(struct iwl_trans *trans,
1077 int iwl_trans_pcie_start_hw(struct iwl_trans *trans);
1078 void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans);
1079 void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val);
1080 void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val);
1081 u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs);
1082 u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg);
1083 void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, u32 val);
1084 int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1086 int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1088 int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, bool retake_ownership);
1090 iwl_trans_pcie_dump_data(struct iwl_trans *trans, u32 dump_mask,
1093 int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1096 int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, bool reset);
1097 void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable);
1098 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans);
1099 void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1101 int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
1103 bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans);
1104 void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans);
1107 void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr);
1108 int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1110 void iwl_trans_pcie_stop_device(struct iwl_trans *trans);
1113 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans);
1114 void iwl_pcie_apm_config(struct iwl_trans *trans);
1115 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans);
1116 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans);
1117 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans);
1118 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1120 void iwl_pcie_apm_stop_master(struct iwl_trans *trans);
1122 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
1124 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr);
1125 void iwl_pcie_apply_destination(struct iwl_trans *trans);
1128 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power);
1131 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
1133 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans);
1134 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans,
1136 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
1137 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
1138 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1140 int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
1142 int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1144 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans,
1146 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,
1148 int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,