Lines Matching +full:tx +full:- +full:sec
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
4 * Copyright (C) 2018-2024 Intel Corporation
6 #include "iwl-trans.h"
7 #include "iwl-fh.h"
8 #include "iwl-context-info.h"
10 #include "iwl-prph.h"
23 result = dma_alloc_coherent(trans->dev, size, phys, GFP_KERNEL);
35 dma_free_coherent(trans->dev, size, old, oldphys);
52 dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len,
53 &dram->physical);
54 if (!dram->block)
55 return -ENOMEM;
57 dram->size = len;
58 memcpy(dram->block, data, len);
65 struct iwl_self_init_dram *dram = &trans->init_dram;
68 if (!dram->paging) {
69 WARN_ON(dram->paging_cnt);
74 for (i = 0; i < dram->paging_cnt; i++)
75 dma_free_coherent(trans->dev, dram->paging[i].size,
76 dram->paging[i].block,
77 dram->paging[i].physical);
79 kfree(dram->paging);
80 dram->paging_cnt = 0;
81 dram->paging = NULL;
88 struct iwl_self_init_dram *dram = &trans->init_dram;
91 if (WARN(dram->paging,
93 dram->paging_cnt))
102 dram->fw = kcalloc(umac_cnt + lmac_cnt, sizeof(*dram->fw), GFP_KERNEL);
103 if (!dram->fw)
104 return -ENOMEM;
105 dram->paging = kcalloc(paging_cnt, sizeof(*dram->paging), GFP_KERNEL);
106 if (!dram->paging)
107 return -ENOMEM;
111 ret = iwl_pcie_ctxt_info_alloc_dma(trans, fw->sec[i].data,
112 fw->sec[i].len,
113 &dram->fw[dram->fw_cnt]);
116 ctxt_dram->lmac_img[i] =
117 cpu_to_le64(dram->fw[dram->fw_cnt].physical);
118 dram->fw_cnt++;
125 fw->sec[dram->fw_cnt + 1].data,
126 fw->sec[dram->fw_cnt + 1].len,
127 &dram->fw[dram->fw_cnt]);
130 ctxt_dram->umac_img[i] =
131 cpu_to_le64(dram->fw[dram->fw_cnt].physical);
132 dram->fw_cnt++;
137 * Paging memory isn't stored in dram->fw as the umac and lmac - it is
139 * This is since the timing of its release is different -
143 * different - fw_cnt isn't changing so loop counter is added to it.
147 int fw_idx = dram->fw_cnt + i + 2;
149 ret = iwl_pcie_ctxt_info_alloc_dma(trans, fw->sec[fw_idx].data,
150 fw->sec[fw_idx].len,
151 &dram->paging[i]);
155 ctxt_dram->virtual_img[i] =
156 cpu_to_le64(dram->paging[i].physical);
157 dram->paging_cnt++;
177 return -ENOMEM;
179 trans_pcie->ctxt_info_dma_addr = phys;
181 ctxt_info->version.version = 0;
182 ctxt_info->version.mac_id =
183 cpu_to_le16((u16)trans->hw_rev);
185 ctxt_info->version.size = cpu_to_le16(sizeof(*ctxt_info) / 4);
187 switch (trans_pcie->rx_buf_size) {
205 WARN_ON(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds) > 12);
208 u32_encode_bits(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds),
211 ctxt_info->control.control_flags = cpu_to_le32(control_flags);
214 rx_cfg = &ctxt_info->rbd_cfg;
215 rx_cfg->free_rbd_addr = cpu_to_le64(trans_pcie->rxq->bd_dma);
216 rx_cfg->used_rbd_addr = cpu_to_le64(trans_pcie->rxq->used_bd_dma);
217 rx_cfg->status_wr_ptr = cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
219 /* initialize TX command queue */
220 ctxt_info->hcmd_cfg.cmd_queue_addr =
221 cpu_to_le64(trans_pcie->txqs.txq[trans_pcie->txqs.cmd.q_id]->dma_addr);
222 ctxt_info->hcmd_cfg.cmd_queue_size =
226 ret = iwl_pcie_init_fw_sec(trans, fw, &ctxt_info->dram);
228 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
229 ctxt_info, trans_pcie->ctxt_info_dma_addr);
233 trans_pcie->ctxt_info = ctxt_info;
242 iwl_write64(trans, CSR_CTXT_INFO_BA, trans_pcie->ctxt_info_dma_addr);
253 if (!trans_pcie->ctxt_info)
256 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
257 trans_pcie->ctxt_info,
258 trans_pcie->ctxt_info_dma_addr);
259 trans_pcie->ctxt_info_dma_addr = 0;
260 trans_pcie->ctxt_info = NULL;