Lines Matching +full:tx +full:- +full:queues +full:- +full:config
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2021, 2023-2024 Intel Corporation
4 * Copyright (C) 2015-2017 Intel Deutschland GmbH
12 #include "iwl-trans.h"
28 * Keep-Warm (KW) buffer base address.
31 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
33 * from going into a power-savings mode that would cause higher DRAM latency,
34 * and possible data over/under-runs, before all Tx/Rx is complete.
38 * automatically invokes keep-warm accesses when normal accesses might not
42 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
50 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
51 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
53 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
54 * aligned (address bits 0-7 must be 0).
55 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
59 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
74 if (trans->trans_cfg->gen2) {
81 return FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
83 return FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
110 * Tx CMD which will be updated in DRAM.
111 * Note that the TFH offset address for Tx CMD update is always referring to
113 * In case of a DRAM Tx CMD update the TFH will update PN and Key ID
117 * Controls TX DMA operation
126 * set to 1 - interrupt is sent to the driver
142 * Note that this register may be configured with non-dword aligned size.
151 * sent from uCode to host driver). Unlike Tx, there is only one Rx
152 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
153 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
164 * Driver sets up RB size and number of RBDs in the CB via Rx config
168 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
180 * 31-12: Not used by driver
181 * 11- 0: Index of last filled Rx buffer descriptor
190 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
220 * Physical base address of 8-byte Rx Status buffer.
222 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
229 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
236 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
237 * NOTE: For 256-entry circular buffer, use only bits [7:0].
246 * Rx Config/Status Registers (RCSR)
247 * Rx Config Reg for channel 0 (only channel used)
257 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
259 * 29-24: reserved
260 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
262 * 19-18: reserved
263 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
265 * 15-14: reserved
266 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
267 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
269 * 3- 0: reserved
279 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
282 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
283 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
284 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
336 /* Write index table - shadow registers */
378 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off.
390 #define RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */
403 #define RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */
414 #define RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */
419 #define RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/
436 /* TFDB Area - TFDs buffer table */
446 * Device has one configuration register for each of 8 Tx DMA/FIFO channels
447 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
448 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
450 * To use a Tx DMA channel, driver must initialize its
459 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
461 * 29- 4: Reserved, set to "0"
463 * 2- 0: Reserved, set to "0"
468 /* Find Control/Status reg for given Tx DMA/FIFO channel */
505 * Tx Shared Status Registers (TSSR)
507 * After stopping Tx DMA channel (writing 0 to
509 * FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
513 * 31-24: 1 = Channel buffers empty (channel 7:0)
514 * 23-16: 1 = No pending requests (channel 7:0)
522 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
527 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
531 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
543 /* Tx service channels */
548 (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
554 * it is brought from the memory to TX-FIFO
558 #define RX_POOL_SIZE(rbds) ((rbds) - 1 + \
560 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC))
571 * struct iwl_rb_status - reserve buffer status
592 /* cb size is the exponent - 3 */
593 #define TFD_QUEUE_CB_SIZE(x) (ilog2(x) - 3)
627 * enum iwl_tfd_tb_hi_n_len - TB hi_n_len bits
637 * struct iwl_tfd_tb - transmit buffer descriptor within transmit frame descriptor
641 * @lo: low [31:0] portion of the dma address of TX buffer
651 * struct iwl_tfh_tb - transmit buffer descriptor within transmit frame descriptor
655 * @tb_len: length of the tx buffer
664 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
667 * For pre 22000 HW it is 256 x 128 bytes-per-TFD = 32 KBytes
668 * For 22000 HW and on it is 256 x 256 bytes-per-TFD = 65 KBytes
677 * of (4K - 4). The concatenates all of a TFD's buffers into a single
678 * Tx frame, up to 8 KBytes in size.
680 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
684 * struct iwl_tfd - Transmit Frame Descriptor (TFD)
687 * 0-4 number of active tbs
689 * 6-7 padding (not used)
701 * struct iwl_tfh_tfd - Transmit Frame Descriptor (TFD)
703 * 0-4 number of active tbs
704 * 5-15 reserved
717 /* Fixed (non-configurable) rx data from phy */
720 * struct iwlagn_scd_bc_tbl - scheduler byte count table
725 * 0-12 - tx command byte count
726 * 12-16 - station index
728 * 0-12 - tx command byte count
729 * 12-13 - number of 64 byte chunks
730 * 14-16 - reserved
737 * struct iwl_gen3_bc_tbl_entry - scheduler byte count table entry gen3
739 * @tfd_offset: 0-12 - tx command byte count
740 * 12-13 - number of 64 byte chunks
741 * 14-16 - reserved