Lines Matching +full:0 +full:xc40
22 #define FH_MEM_LOWER_BOUND (0x1000)
23 #define FH_MEM_UPPER_BOUND (0x2000)
24 #define FH_MEM_LOWER_BOUND_GEN2 (0xa06000)
25 #define FH_MEM_UPPER_BOUND_GEN2 (0xa08000)
42 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
44 #define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
52 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04
54 * aligned (address bits 0-7 must be 0).
59 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
61 #define FH_MEM_CBBC_0_15_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
62 #define FH_MEM_CBBC_0_15_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10)
63 #define FH_MEM_CBBC_16_19_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBF0)
64 #define FH_MEM_CBBC_16_19_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
65 #define FH_MEM_CBBC_20_31_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xB20)
66 #define FH_MEM_CBBC_20_31_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xB80)
68 #define TFH_TFDQ_CBB_TABLE (0x1C00)
93 * Bits 3:0:
95 * Maximum configuration value allowed is 0xC
104 #define TFH_TRANSFER_MODE (0x1F40)
105 #define TFH_TRANSFER_MAX_PENDING_REQ 0xc
115 #define TFH_TXCMD_UPDATE_CFG (0x1F48)
127 * Bit 0: Indicates the snoop configuration
129 #define TFH_SRV_DMA_CHNL0_CTRL (0x1F60)
130 #define TFH_SRV_DMA_SNOOP BIT(0)
135 #define TFH_SRV_DMA_CHNL0_SRAM_ADDR (0x1F64)
138 #define TFH_SRV_DMA_CHNL0_DRAM_ADDR (0x1F68)
144 #define TFH_SRV_DMA_CHNL0_BC (0x1F70)
168 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
171 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
176 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
181 * 11- 0: Index of last filled Rx buffer descriptor
191 * the circular buffer. This value should initially be 0 (before preparing any
193 * wrap back to 0 at the end of the circular buffer (but don't wrap before
206 * driver may process the RB pointed to by RBD 0. Depending on volume of
215 #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0)
216 #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
222 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
229 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
231 #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004)
236 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
237 * NOTE: For 256-entry circular buffer, use only bits [7:0].
239 #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008)
242 #define FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x00c)
247 * Rx Config Reg for channel 0 (only channel used)
252 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
268 * typical value 0x10 (about 1/2 msec)
269 * 3- 0: reserved
271 #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
272 #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0)
276 #define FH_MEM_RCSR_CHNL0_RBDCB_WPTR (FH_MEM_RCSR_CHNL0 + 0x8)
277 #define FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (FH_MEM_RCSR_CHNL0 + 0x10)
279 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
280 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
281 #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
282 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
283 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
284 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
288 #define RX_RB_TIMEOUT (0x11)
290 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
291 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
292 #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
294 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
295 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
296 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
297 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
299 #define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
300 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
301 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
306 * After stopping Rx DMA channel (writing 0 to
311 * 24: 1 = Channel 0 is idle
316 #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40)
317 #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
320 #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004)
322 (FH_MEM_RSSR_LOWER_BOUND + 0x008)
324 #define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
327 #define FH_MEM_TB_MAX_LENGTH (0x00020000)
331 #define RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */
334 #define RFH_Q0_FRBDCB_WIDX 0xA08080
337 #define RFH_Q0_FRBDCB_WIDX_TRG 0x1C80
340 #define RFH_Q0_FRBDCB_RIDX 0xA080C0
343 #define RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */
346 #define RFH_Q0_URBDCB_WIDX 0xA08180
348 #define RFH_Q0_URBDCB_VAID 0xA081C0
351 #define RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */
354 #define RFH_Q0_ORB_WPTR_LSB 0xA08280
356 #define RFH_RBDBUF_RBD0_LSB 0xA08300
380 #define RFH_GEN_STATUS 0xA09808
381 #define RFH_GEN_STATUS_GEN3 0xA07824
387 #define RFH_RXF_DMA_CFG 0xA09820
388 #define RFH_RXF_DMA_CFG_GEN3 0xA07880
390 #define RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */
392 #define RFH_RXF_DMA_RB_SIZE_1K (0x1 << RFH_RXF_DMA_RB_SIZE_POS)
393 #define RFH_RXF_DMA_RB_SIZE_2K (0x2 << RFH_RXF_DMA_RB_SIZE_POS)
394 #define RFH_RXF_DMA_RB_SIZE_4K (0x4 << RFH_RXF_DMA_RB_SIZE_POS)
395 #define RFH_RXF_DMA_RB_SIZE_8K (0x8 << RFH_RXF_DMA_RB_SIZE_POS)
396 #define RFH_RXF_DMA_RB_SIZE_12K (0x9 << RFH_RXF_DMA_RB_SIZE_POS)
397 #define RFH_RXF_DMA_RB_SIZE_16K (0xA << RFH_RXF_DMA_RB_SIZE_POS)
398 #define RFH_RXF_DMA_RB_SIZE_20K (0xB << RFH_RXF_DMA_RB_SIZE_POS)
399 #define RFH_RXF_DMA_RB_SIZE_24K (0xC << RFH_RXF_DMA_RB_SIZE_POS)
400 #define RFH_RXF_DMA_RB_SIZE_28K (0xD << RFH_RXF_DMA_RB_SIZE_POS)
401 #define RFH_RXF_DMA_RB_SIZE_32K (0xE << RFH_RXF_DMA_RB_SIZE_POS)
403 #define RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */
405 #define RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << RFH_RXF_DMA_RBDCB_SIZE_POS)
406 #define RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << RFH_RXF_DMA_RBDCB_SIZE_POS)
407 #define RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << RFH_RXF_DMA_RBDCB_SIZE_POS)
408 #define RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS)
409 #define RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS)
410 #define RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << RFH_RXF_DMA_RBDCB_SIZE_POS)
411 #define RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << RFH_RXF_DMA_RBDCB_SIZE_POS)
412 #define RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << RFH_RXF_DMA_RBDCB_SIZE_POS)
413 #define RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << RFH_RXF_DMA_RBDCB_SIZE_POS)
414 #define RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */
417 #define RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */
418 #define RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */
419 #define RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/
422 #define RFH_RXF_RXQ_ACTIVE 0xA0980C
424 #define RFH_GEN_CFG 0xA09800
425 #define RFH_GEN_CFG_SERVICE_DMA_SNOOP BIT(0)
429 #define RFH_GEN_CFG_RB_CHUNK_SIZE_64 0
430 /* the driver assumes everywhere that the default RXQ is 0 */
431 #define RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00
437 #define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
438 #define FH_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900)
439 #define FH_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958)
440 #define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
441 #define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
448 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
456 * All other bits should be 0.
461 * 29- 4: Reserved, set to "0"
462 * 3: Enable internal DMA requests (1, normal operation), disable (0)
463 * 2- 0: Reserved, set to "0"
465 #define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
466 #define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
473 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
475 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
477 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
479 #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
480 #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
482 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
483 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
485 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
486 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
487 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
489 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
490 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
491 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
493 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
494 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
495 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
497 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
498 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
499 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
507 * After stopping Tx DMA channel (writing 0 to
513 * 31-24: 1 = Channel buffers empty (channel 7:0)
514 * 23-16: 1 = No pending requests (channel 7:0)
516 #define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0)
517 #define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0)
519 #define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010)
531 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
538 #define FH_TSSR_TX_ERROR_REG (FH_TSSR_LOWER_BOUND + 0x018)
539 #define FH_TSSR_TX_MSG_CONFIG_REG (FH_TSSR_LOWER_BOUND + 0x008)
545 #define FH_SRVC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9C8)
546 #define FH_SRVC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
548 (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
550 #define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98)
551 #define FH_TX_TRB_REG(_chan) (FH_MEM_LOWER_BOUND + 0x958 + (_chan) * 4)
556 #define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
568 #define IWL_DEFAULT_RX_QUEUE 0
573 * @closed_rb_num: [0:11] Indicates the index of the RB which was closed
574 * @closed_fr_num: [0:11] Indicates the index of the RX Frame which was closed
575 * @finished_rb_num: [0:11] Indicates the index of the current RB
577 * @finished_fr_num: [0:11] Indicates the index of the RX Frame
603 #define IMR_TFH_SRV_DMA_CHNL0_CTRL 0x00a0a51c
604 #define IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR 0x00a0a520
605 #define IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB 0x00a0a524
606 #define IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB 0x00a0a528
607 #define IMR_TFH_SRV_DMA_CHNL0_BC 0x00a0a52c
608 #define TFH_SRV_DMA_CHNL0_LEFT_BC 0x00a0a530
611 #define IMR_RFH_GEN_CFG_SERVICE_DMA_RS_MSK 0x0000000c
612 #define IMR_RFH_GEN_CFG_SERVICE_DMA_SNOOP_MSK 0x00000002
615 #define IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK 0x80000000
616 #define IMR_UREG_CHICK 0x00d05c00
617 #define IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS 0x00800000
618 #define IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK 0x00000030
619 #define IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS 0x80000000
623 return (sizeof(addr) > sizeof(u32) ? upper_32_bits(addr) : 0) & 0xF;
632 TB_HI_N_LEN_ADDR_HI_MSK = 0xf,
633 TB_HI_N_LEN_LEN_MSK = 0xfff0,
641 * @lo: low [31:0] portion of the dma address of TX buffer
687 * 0-4 number of active tbs
703 * 0-4 number of active tbs
715 #define IWL_KW_SIZE 0x1000 /* 4k */
725 * 0-12 - tx command byte count
728 * 0-12 - tx command byte count
739 * @tfd_offset: 0-12 - tx command byte count