Lines Matching refs:trans
7 #include "iwl-trans.h"
99 static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans,
113 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n",
116 if (!iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list))
121 static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans,
152 IWL_ERR(trans, "WRT: Invalid DRAM buffer allocation requested size (0)\n");
156 trans->dbg.fw_mon_cfg[alloc_id] = *alloc;
160 IWL_ERR(trans,
166 static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans,
181 IWL_ERR(trans,
187 if (!iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list))
192 static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans,
212 IWL_DEBUG_FW(trans, "WRT: parsing region: %.*s\n",
216 IWL_ERR(trans, "WRT: Invalid region id %u\n", id);
222 IWL_ERR(trans, "WRT: Invalid region type %u\n", type);
227 trans->dbg.imr_data.sram_addr =
229 trans->dbg.imr_data.sram_size =
234 active_reg = &trans->dbg.active_regions[id];
236 IWL_WARN(trans, "WRT: Overriding region id %u\n", id);
245 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type);
250 static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans,
263 IWL_ERR(trans,
269 IWL_DEBUG_FW(trans,
272 trans->dbg.last_tp_resetfw = 0xFF;
274 new_tlv = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list);
287 static int iwl_dbg_tlv_config_set(struct iwl_trans *trans,
296 IWL_DEBUG_FW(trans,
303 IWL_DEBUG_FW(trans,
308 if (!iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].config_list))
313 static int (*dbg_tlv_alloc[])(struct iwl_trans *trans,
323 void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv,
327 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg;
342 !(domain & trans->dbg.domains_bitmap)) {
343 IWL_DEBUG_FW(trans,
345 domain, trans->dbg.domains_bitmap);
350 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type);
355 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type,
360 ret = dbg_tlv_alloc[tlv_idx](trans, tlv);
362 IWL_WARN(trans,
377 void iwl_dbg_tlv_del_timers(struct iwl_trans *trans)
379 struct list_head *timer_list = &trans->dbg.periodic_trig_list;
390 static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans,
400 fw_mon = &trans->dbg.fw_mon_ini[alloc_id];
405 dma_free_coherent(trans->dev, frag->size, frag->block,
418 void iwl_dbg_tlv_free(struct iwl_trans *trans)
423 iwl_dbg_tlv_del_timers(trans);
425 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) {
427 &trans->dbg.active_regions[i];
434 &trans->dbg.debug_info_tlv_list, list) {
439 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
441 &trans->dbg.time_point[i];
469 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++)
470 iwl_dbg_tlv_fragments_free(trans, i);
473 static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data,
486 IWL_ERR(trans, "invalid TLV len: %zd/%u\n",
493 iwl_dbg_tlv_alloc(trans, tlv, true);
499 void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans)
506 trans->trans_cfg->device_family <= IWL_DEVICE_FAMILY_8000)
510 IWL_DEBUG_FW(trans, "%s %s\n", res ? "didn't load" : "loaded", yoyo_bin);
515 trans->dbg.yoyo_bin_loaded = true;
517 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size);
522 void iwl_dbg_tlv_init(struct iwl_trans *trans)
526 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list);
527 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list);
529 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
531 &trans->dbg.time_point[i];
591 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id];
592 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
606 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) {
610 } else if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_BZ &&
639 iwl_dbg_tlv_fragments_free(fwrt->trans,
668 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
672 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
714 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
750 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
757 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
797 &fwrt->trans->dbg.fw_mon_ini[IWL_FW_INI_ALLOCATION_ID_DBGC1].frags[0];
813 if (fwrt->trans->dbg.fw_mon_cfg[i].buf_location ==
847 iwl_trans_send_cmd(fwrt->trans, &cmd);
865 if (!iwl_trans_grab_nic_access(fwrt->trans)) {
874 iwl_trans_write_prph(fwrt->trans, address + offset, value);
876 iwl_trans_release_nic_access(fwrt->trans);
883 iwl_trans_write_mem32(fwrt->trans, address + offset, value);
893 iwl_write32(fwrt->trans, address + offset, value);
901 struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[1].frags[0];
925 ret = iwl_trans_write_mem(fwrt->trans,
940 fwrt->trans->dbg.ucode_preset = debug_token_config;
974 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list;
1017 &fwrt->trans->dbg.periodic_trig_list);
1242 fwrt->trans->dbg.restart_required = false;
1244 if (fwrt->trans->trans_cfg->device_family ==
1246 fwrt->trans->dbg.restart_required = true;
1248 fwrt->trans->dbg.last_tp_resetfw ==
1250 fwrt->trans->dbg.restart_required = false;
1251 fwrt->trans->dbg.last_tp_resetfw = 0xFF;
1254 fwrt->trans->dbg.restart_required = true;
1257 fwrt->trans->dbg.restart_required = false;
1258 fwrt->trans->dbg.last_tp_resetfw =
1273 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest;
1280 fwrt->trans->dbg.domains_bitmap);
1282 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) {
1284 &fwrt->trans->dbg.time_point[i];
1299 &fwrt->trans->dbg.fw_mon_cfg[i];
1326 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) {
1329 &fwrt->trans->dbg.active_regions[i];
1333 fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1349 fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1363 if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
1368 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list;
1369 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list;
1370 conf_list = &fwrt->trans->dbg.time_point[tp_id].config_list;