Lines Matching defs:fwrt
47 * @fwrt: &struct iwl_fw_runtime
53 struct iwl_fw_runtime *fwrt;
540 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt,
557 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE,
563 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n",
579 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt,
591 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id];
592 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
606 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) {
610 } else if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_BZ &&
628 IWL_DEBUG_FW(fwrt,
632 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i],
639 iwl_dbg_tlv_fragments_free(fwrt->trans,
653 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt,
660 if (!fw_has_capa(&fwrt->fw->ucode_capa,
668 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
672 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
686 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n",
714 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
724 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt)
728 if (fw_has_capa(&fwrt->fw->ucode_capa,
733 ret = iwl_dbg_tlv_apply_buffer(fwrt, i);
735 IWL_WARN(fwrt,
741 static int iwl_dbg_tlv_update_dram(struct iwl_fw_runtime *fwrt,
750 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
752 IWL_DEBUG_FW(fwrt, "WRT: alloc_id %u location is not in DRAM_PATH\n",
757 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
775 IWL_DEBUG_FW(fwrt, "WRT: DRAM buffer details alloc_id=%u, num_frags=%u\n",
784 IWL_DEBUG_FW(fwrt, "WRT: DRAM fragment details\n");
785 IWL_DEBUG_FW(fwrt, "frag=%u, addr=0x%016llx, size=0x%x)\n",
792 static void iwl_dbg_tlv_update_drams(struct iwl_fw_runtime *fwrt)
797 &fwrt->trans->dbg.fw_mon_ini[IWL_FW_INI_ALLOCATION_ID_DBGC1].frags[0];
805 if (!fw_has_capa(&fwrt->fw->ucode_capa,
813 if (fwrt->trans->dbg.fw_mon_cfg[i].buf_location ==
817 ret = iwl_dbg_tlv_update_dram(fwrt, i, dram_info);
821 IWL_INFO(fwrt,
832 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt,
847 iwl_trans_send_cmd(fwrt->trans, &cmd);
851 static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt,
865 if (!iwl_trans_grab_nic_access(fwrt->trans)) {
866 IWL_DEBUG_FW(fwrt, "WRT: failed to get nic access\n");
867 IWL_DEBUG_FW(fwrt, "WRT: skipping MAC PERIPHERY config\n");
870 IWL_DEBUG_FW(fwrt, "WRT: MAC PERIPHERY config len: len %u\n", len);
874 iwl_trans_write_prph(fwrt->trans, address + offset, value);
876 iwl_trans_release_nic_access(fwrt->trans);
883 iwl_trans_write_mem32(fwrt->trans, address + offset, value);
884 IWL_DEBUG_FW(fwrt, "WRT: DEV_MEM: count %u, add: %u val: %u\n",
893 iwl_write32(fwrt->trans, address + offset, value);
894 IWL_DEBUG_FW(fwrt, "WRT: CSR: count %u, add: %u val: %u\n",
901 struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[1].frags[0];
914 IWL_DEBUG_FW(fwrt, "WRT: dram_base_addr 0x%016llx, dram_size 0x%x\n",
916 IWL_DEBUG_FW(fwrt, "WRT: config_list->addr_offset: %u\n",
925 ret = iwl_trans_write_mem(fwrt->trans,
928 IWL_ERR(fwrt, "Failed to write dram_info to HW_SMEM\n");
938 IWL_DEBUG_FW(fwrt, "WRT: Setting HWM debug token config: %u\n",
940 fwrt->trans->dbg.ucode_preset = debug_token_config;
958 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data, false);
970 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt)
974 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list;
990 IWL_ERR(fwrt,
996 IWL_WARN(fwrt,
1006 IWL_ERR(fwrt,
1011 timer_node->fwrt = fwrt;
1017 &fwrt->trans->dbg.periodic_trig_list);
1019 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n");
1052 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt,
1068 IWL_DEBUG_FW(fwrt,
1075 IWL_DEBUG_FW(fwrt,
1088 IWL_WARN(fwrt,
1106 IWL_DEBUG_FW(fwrt,
1115 IWL_DEBUG_FW(fwrt,
1121 IWL_DEBUG_FW(fwrt,
1132 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt,
1152 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n",
1159 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match);
1163 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt,
1173 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv);
1177 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt,
1204 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, bool sync,
1207 bool (*data_check)(struct iwl_fw_runtime *fwrt,
1225 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync);
1232 data_check(fwrt, &dump_data, tp_data,
1234 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync);
1242 fwrt->trans->dbg.restart_required = false;
1244 if (fwrt->trans->trans_cfg->device_family ==
1246 fwrt->trans->dbg.restart_required = true;
1248 fwrt->trans->dbg.last_tp_resetfw ==
1250 fwrt->trans->dbg.restart_required = false;
1251 fwrt->trans->dbg.last_tp_resetfw = 0xFF;
1254 fwrt->trans->dbg.restart_required = true;
1257 fwrt->trans->dbg.restart_required = false;
1258 fwrt->trans->dbg.last_tp_resetfw =
1264 IWL_ERR(fwrt, "WRT: wrong resetfw %d\n",
1271 void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt)
1273 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest;
1278 IWL_DEBUG_FW(fwrt,
1280 fwrt->trans->dbg.domains_bitmap);
1282 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) {
1284 &fwrt->trans->dbg.time_point[i];
1286 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp);
1299 &fwrt->trans->dbg.fw_mon_cfg[i];
1313 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i);
1316 IWL_WARN(fwrt,
1326 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) {
1329 &fwrt->trans->dbg.active_regions[i];
1333 fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1344 IWL_DEBUG_FW(fwrt,
1349 fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1356 void _iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt,
1363 if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
1368 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list;
1369 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list;
1370 conf_list = &fwrt->trans->dbg.time_point[tp_id].config_list;
1374 iwl_dbg_tlv_init_cfg(fwrt);
1375 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1376 iwl_dbg_tlv_update_drams(fwrt);
1377 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1380 iwl_dbg_tlv_apply_buffers(fwrt);
1381 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1382 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1383 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1386 iwl_dbg_tlv_set_periodic_trigs(fwrt);
1387 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1392 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1393 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1394 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data,
1398 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1399 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1400 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);