Lines Matching refs:u32

130 	u32	  wbm2sw_cc_enable;
145 	u32 qmi_service_ins_id;
153 	u32 ce_count;
155 	u32 target_ce_count;
157 	u32 svc_to_ce_map_len;
177 	u32 hal_desc_sz;
178 	u32 num_tcl_banks;
179 	u32 max_tx_ring;
246 	u32 hal_tcl1_ring_id;
247 	u32 hal_tcl1_ring_misc;
248 	u32 hal_tcl1_ring_tp_addr_lsb;
249 	u32 hal_tcl1_ring_tp_addr_msb;
250 	u32 hal_tcl1_ring_consumer_int_setup_ix0;
251 	u32 hal_tcl1_ring_consumer_int_setup_ix1;
252 	u32 hal_tcl1_ring_msi1_base_lsb;
253 	u32 hal_tcl1_ring_msi1_base_msb;
254 	u32 hal_tcl1_ring_msi1_data;
255 	u32 hal_tcl_ring_base_lsb;
257 	u32 hal_tcl_status_ring_base_lsb;
259 	u32 hal_wbm_idle_ring_base_lsb;
260 	u32 hal_wbm_idle_ring_misc_addr;
261 	u32 hal_wbm_r0_idle_list_cntl_addr;
262 	u32 hal_wbm_r0_idle_list_size_addr;
263 	u32 hal_wbm_scattered_ring_base_lsb;
264 	u32 hal_wbm_scattered_ring_base_msb;
265 	u32 hal_wbm_scattered_desc_head_info_ix0;
266 	u32 hal_wbm_scattered_desc_head_info_ix1;
267 	u32 hal_wbm_scattered_desc_tail_info_ix0;
268 	u32 hal_wbm_scattered_desc_tail_info_ix1;
269 	u32 hal_wbm_scattered_desc_ptr_hp_addr;
271 	u32 hal_wbm_sw_release_ring_base_lsb;
272 	u32 hal_wbm_sw1_release_ring_base_lsb;
273 	u32 hal_wbm0_release_ring_base_lsb;
274 	u32 hal_wbm1_release_ring_base_lsb;
276 	u32 pcie_qserdes_sysclk_en_sel;
277 	u32 pcie_pcs_osc_dtct_config_base;
279 	u32 hal_ppe_rel_ring_base;
281 	u32 hal_reo2_ring_base;
282 	u32 hal_reo1_misc_ctrl_addr;
283 	u32 hal_reo1_sw_cookie_cfg0;
284 	u32 hal_reo1_sw_cookie_cfg1;
285 	u32 hal_reo1_qdesc_lut_base0;
286 	u32 hal_reo1_qdesc_lut_base1;
287 	u32 hal_reo1_ring_base_lsb;
288 	u32 hal_reo1_ring_base_msb;
289 	u32 hal_reo1_ring_id;
290 	u32 hal_reo1_ring_misc;
291 	u32 hal_reo1_ring_hp_addr_lsb;
292 	u32 hal_reo1_ring_hp_addr_msb;
293 	u32 hal_reo1_ring_producer_int_setup;
294 	u32 hal_reo1_ring_msi1_base_lsb;
295 	u32 hal_reo1_ring_msi1_base_msb;
296 	u32 hal_reo1_ring_msi1_data;
297 	u32 hal_reo1_aging_thres_ix0;
298 	u32 hal_reo1_aging_thres_ix1;
299 	u32 hal_reo1_aging_thres_ix2;
300 	u32 hal_reo1_aging_thres_ix3;
302 	u32 hal_reo2_sw0_ring_base;
304 	u32 hal_sw2reo_ring_base;
305 	u32 hal_sw2reo1_ring_base;
307 	u32 hal_reo_cmd_ring_base;
309 	u32 hal_reo_status_ring_base;