Lines Matching +full:0 +full:x00000054
32 return 0; in ath12k_hw_mac_id_to_srng_id_qcn9274()
51 return 0; in ath12k_hw_mac_id_to_pdev_id_wcn7850()
67 if (ring_num == 0 || ring_num == 2 || ring_num == 4) in ath12k_dp_srng_is_comp_ring_wcn7850()
91 #define ATH12K_TX_RING_MASK_0 0x1
92 #define ATH12K_TX_RING_MASK_1 0x2
93 #define ATH12K_TX_RING_MASK_2 0x4
94 #define ATH12K_TX_RING_MASK_3 0x8
95 #define ATH12K_TX_RING_MASK_4 0x10
97 #define ATH12K_RX_RING_MASK_0 0x1
98 #define ATH12K_RX_RING_MASK_1 0x2
99 #define ATH12K_RX_RING_MASK_2 0x4
100 #define ATH12K_RX_RING_MASK_3 0x8
102 #define ATH12K_RX_ERR_RING_MASK_0 0x1
104 #define ATH12K_RX_WBM_REL_RING_MASK_0 0x1
106 #define ATH12K_REO_STATUS_RING_MASK_0 0x1
108 #define ATH12K_HOST2RXDMA_RING_MASK_0 0x1
110 #define ATH12K_RX_MON_RING_MASK_0 0x1
111 #define ATH12K_RX_MON_RING_MASK_1 0x2
112 #define ATH12K_RX_MON_RING_MASK_2 0x4
114 #define ATH12K_TX_MON_RING_MASK_0 0x1
115 #define ATH12K_TX_MON_RING_MASK_1 0x2
121 .pipenum = __cpu_to_le32(0),
126 .reserved = __cpu_to_le32(0),
136 .reserved = __cpu_to_le32(0),
146 .reserved = __cpu_to_le32(0),
156 .reserved = __cpu_to_le32(0),
166 .reserved = __cpu_to_le32(0),
176 .reserved = __cpu_to_le32(0),
186 .reserved = __cpu_to_le32(0),
196 .reserved = __cpu_to_le32(0),
206 .reserved = __cpu_to_le32(0),
218 .reserved = __cpu_to_le32(0),
228 .reserved = __cpu_to_le32(0),
238 .reserved = __cpu_to_le32(0),
248 .pipenum = __cpu_to_le32(0),
253 .reserved = __cpu_to_le32(0),
263 .reserved = __cpu_to_le32(0),
273 .reserved = __cpu_to_le32(0),
283 .reserved = __cpu_to_le32(0),
293 .reserved = __cpu_to_le32(0),
303 .reserved = __cpu_to_le32(0),
313 .reserved = __cpu_to_le32(0),
320 .nentries = __cpu_to_le32(0),
321 .nbytes_max = __cpu_to_le32(0),
323 .reserved = __cpu_to_le32(0),
333 .reserved = __cpu_to_le32(0),
396 __cpu_to_le32(0),
406 __cpu_to_le32(0),
447 __cpu_to_le32(0),
448 __cpu_to_le32(0),
449 __cpu_to_le32(0),
507 __cpu_to_le32(0),
528 __cpu_to_le32(0),
529 __cpu_to_le32(0),
530 __cpu_to_le32(0),
542 0, 0, 0,
548 0, 0, 0, 0,
555 0, 0, 0,
559 0, 0, 0,
563 0, 0, 0,
567 0, 0, 0,
585 0, 0, 0,
608 .hal_tcl1_ring_id = 0x00000908,
609 .hal_tcl1_ring_misc = 0x00000910,
610 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c,
611 .hal_tcl1_ring_tp_addr_msb = 0x00000920,
612 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930,
613 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934,
614 .hal_tcl1_ring_msi1_base_lsb = 0x00000948,
615 .hal_tcl1_ring_msi1_base_msb = 0x0000094c,
616 .hal_tcl1_ring_msi1_data = 0x00000950,
617 .hal_tcl_ring_base_lsb = 0x00000b58,
620 .hal_tcl_status_ring_base_lsb = 0x00000d38,
622 .hal_wbm_idle_ring_base_lsb = 0x00000d0c,
623 .hal_wbm_idle_ring_misc_addr = 0x00000d1c,
624 .hal_wbm_r0_idle_list_cntl_addr = 0x00000210,
625 .hal_wbm_r0_idle_list_size_addr = 0x00000214,
626 .hal_wbm_scattered_ring_base_lsb = 0x00000220,
627 .hal_wbm_scattered_ring_base_msb = 0x00000224,
628 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000230,
629 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000234,
630 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000240,
631 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000244,
632 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000024c,
634 .hal_wbm_sw_release_ring_base_lsb = 0x0000034c,
635 .hal_wbm_sw1_release_ring_base_lsb = 0x000003c4,
636 .hal_wbm0_release_ring_base_lsb = 0x00000dd8,
637 .hal_wbm1_release_ring_base_lsb = 0x00000e50,
640 .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8,
641 .pcie_pcs_osc_dtct_config_base = 0x01e0d45c,
644 .hal_ppe_rel_ring_base = 0x0000043c,
647 .hal_reo2_ring_base = 0x0000055c,
648 .hal_reo1_misc_ctrl_addr = 0x00000b7c,
649 .hal_reo1_sw_cookie_cfg0 = 0x00000050,
650 .hal_reo1_sw_cookie_cfg1 = 0x00000054,
651 .hal_reo1_qdesc_lut_base0 = 0x00000058,
652 .hal_reo1_qdesc_lut_base1 = 0x0000005c,
653 .hal_reo1_ring_base_lsb = 0x000004e4,
654 .hal_reo1_ring_base_msb = 0x000004e8,
655 .hal_reo1_ring_id = 0x000004ec,
656 .hal_reo1_ring_misc = 0x000004f4,
657 .hal_reo1_ring_hp_addr_lsb = 0x000004f8,
658 .hal_reo1_ring_hp_addr_msb = 0x000004fc,
659 .hal_reo1_ring_producer_int_setup = 0x00000508,
660 .hal_reo1_ring_msi1_base_lsb = 0x0000052C,
661 .hal_reo1_ring_msi1_base_msb = 0x00000530,
662 .hal_reo1_ring_msi1_data = 0x00000534,
663 .hal_reo1_aging_thres_ix0 = 0x00000b08,
664 .hal_reo1_aging_thres_ix1 = 0x00000b0c,
665 .hal_reo1_aging_thres_ix2 = 0x00000b10,
666 .hal_reo1_aging_thres_ix3 = 0x00000b14,
669 .hal_reo2_sw0_ring_base = 0x000008a4,
672 .hal_sw2reo_ring_base = 0x00000304,
673 .hal_sw2reo1_ring_base = 0x0000037c,
676 .hal_reo_cmd_ring_base = 0x0000028c,
679 .hal_reo_status_ring_base = 0x00000a84,
684 .hal_tcl1_ring_id = 0x00000908,
685 .hal_tcl1_ring_misc = 0x00000910,
686 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c,
687 .hal_tcl1_ring_tp_addr_msb = 0x00000920,
688 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930,
689 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934,
690 .hal_tcl1_ring_msi1_base_lsb = 0x00000948,
691 .hal_tcl1_ring_msi1_base_msb = 0x0000094c,
692 .hal_tcl1_ring_msi1_data = 0x00000950,
693 .hal_tcl_ring_base_lsb = 0x00000b58,
696 .hal_tcl_status_ring_base_lsb = 0x00000d38,
699 .hal_wbm_idle_ring_base_lsb = 0x00000d3c,
700 .hal_wbm_idle_ring_misc_addr = 0x00000d4c,
701 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240,
702 .hal_wbm_r0_idle_list_size_addr = 0x00000244,
703 .hal_wbm_scattered_ring_base_lsb = 0x00000250,
704 .hal_wbm_scattered_ring_base_msb = 0x00000254,
705 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260,
706 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264,
707 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270,
708 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274,
709 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000027c,
712 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c,
713 .hal_wbm_sw1_release_ring_base_lsb = 0x000003f4,
716 .hal_wbm0_release_ring_base_lsb = 0x00000e08,
717 .hal_wbm1_release_ring_base_lsb = 0x00000e80,
720 .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8,
721 .pcie_pcs_osc_dtct_config_base = 0x01e0d45c,
724 .hal_ppe_rel_ring_base = 0x0000046c,
727 .hal_reo2_ring_base = 0x00000578,
728 .hal_reo1_misc_ctrl_addr = 0x00000b9c,
729 .hal_reo1_sw_cookie_cfg0 = 0x0000006c,
730 .hal_reo1_sw_cookie_cfg1 = 0x00000070,
731 .hal_reo1_qdesc_lut_base0 = 0x00000074,
732 .hal_reo1_qdesc_lut_base1 = 0x00000078,
733 .hal_reo1_ring_base_lsb = 0x00000500,
734 .hal_reo1_ring_base_msb = 0x00000504,
735 .hal_reo1_ring_id = 0x00000508,
736 .hal_reo1_ring_misc = 0x00000510,
737 .hal_reo1_ring_hp_addr_lsb = 0x00000514,
738 .hal_reo1_ring_hp_addr_msb = 0x00000518,
739 .hal_reo1_ring_producer_int_setup = 0x00000524,
740 .hal_reo1_ring_msi1_base_lsb = 0x00000548,
741 .hal_reo1_ring_msi1_base_msb = 0x0000054C,
742 .hal_reo1_ring_msi1_data = 0x00000550,
743 .hal_reo1_aging_thres_ix0 = 0x00000B28,
744 .hal_reo1_aging_thres_ix1 = 0x00000B2C,
745 .hal_reo1_aging_thres_ix2 = 0x00000B30,
746 .hal_reo1_aging_thres_ix3 = 0x00000B34,
749 .hal_reo2_sw0_ring_base = 0x000008c0,
752 .hal_sw2reo_ring_base = 0x00000320,
753 .hal_sw2reo1_ring_base = 0x00000398,
756 .hal_reo_cmd_ring_base = 0x000002A8,
759 .hal_reo_status_ring_base = 0x00000aa0,
764 .hal_tcl1_ring_id = 0x00000908,
765 .hal_tcl1_ring_misc = 0x00000910,
766 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c,
767 .hal_tcl1_ring_tp_addr_msb = 0x00000920,
768 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930,
769 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934,
770 .hal_tcl1_ring_msi1_base_lsb = 0x00000948,
771 .hal_tcl1_ring_msi1_base_msb = 0x0000094c,
772 .hal_tcl1_ring_msi1_data = 0x00000950,
773 .hal_tcl_ring_base_lsb = 0x00000b58,
776 .hal_tcl_status_ring_base_lsb = 0x00000d38,
778 .hal_wbm_idle_ring_base_lsb = 0x00000d3c,
779 .hal_wbm_idle_ring_misc_addr = 0x00000d4c,
780 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240,
781 .hal_wbm_r0_idle_list_size_addr = 0x00000244,
782 .hal_wbm_scattered_ring_base_lsb = 0x00000250,
783 .hal_wbm_scattered_ring_base_msb = 0x00000254,
784 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260,
785 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264,
786 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270,
787 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274,
788 .hal_wbm_scattered_desc_ptr_hp_addr = 0x00000027c,
790 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c,
791 .hal_wbm_sw1_release_ring_base_lsb = 0x00000284,
792 .hal_wbm0_release_ring_base_lsb = 0x00000e08,
793 .hal_wbm1_release_ring_base_lsb = 0x00000e80,
796 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,
797 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c,
800 .hal_ppe_rel_ring_base = 0x0000043c,
803 .hal_reo2_ring_base = 0x0000055c,
804 .hal_reo1_misc_ctrl_addr = 0x00000b7c,
805 .hal_reo1_sw_cookie_cfg0 = 0x00000050,
806 .hal_reo1_sw_cookie_cfg1 = 0x00000054,
807 .hal_reo1_qdesc_lut_base0 = 0x00000058,
808 .hal_reo1_qdesc_lut_base1 = 0x0000005c,
809 .hal_reo1_ring_base_lsb = 0x000004e4,
810 .hal_reo1_ring_base_msb = 0x000004e8,
811 .hal_reo1_ring_id = 0x000004ec,
812 .hal_reo1_ring_misc = 0x000004f4,
813 .hal_reo1_ring_hp_addr_lsb = 0x000004f8,
814 .hal_reo1_ring_hp_addr_msb = 0x000004fc,
815 .hal_reo1_ring_producer_int_setup = 0x00000508,
816 .hal_reo1_ring_msi1_base_lsb = 0x0000052C,
817 .hal_reo1_ring_msi1_base_msb = 0x00000530,
818 .hal_reo1_ring_msi1_data = 0x00000534,
819 .hal_reo1_aging_thres_ix0 = 0x00000b08,
820 .hal_reo1_aging_thres_ix1 = 0x00000b0c,
821 .hal_reo1_aging_thres_ix2 = 0x00000b10,
822 .hal_reo1_aging_thres_ix3 = 0x00000b14,
825 .hal_reo2_sw0_ring_base = 0x000008a4,
828 .hal_sw2reo_ring_base = 0x00000304,
829 .hal_sw2reo1_ring_base = 0x0000037c,
832 .hal_reo_cmd_ring_base = 0x0000028c,
835 .hal_reo_status_ring_base = 0x00000a84,
857 .name = "qcn9274 hw1.0",
860 .dir = "QCN9274/hw1.0",
884 .num_rxdma_dst_ring = 0,
912 .name = "wcn7850 hw2.0",
916 .dir = "WCN7850/hw2.0",
969 .name = "qcn9274 hw2.0",
972 .dir = "QCN9274/hw2.0",
996 .num_rxdma_dst_ring = 0,
1030 for (i = 0; i < ARRAY_SIZE(ath12k_hw_params); i++) { in ath12k_hw_init()
1038 ath12k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev); in ath12k_hw_init()
1046 return 0; in ath12k_hw_init()