Lines Matching +full:10 +full:- +full:bit
1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
245 #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(9)
246 #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(10)
247 #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(11)
299 #define HAL_RX_HT_SIG_INFO_INFO0_BW BIT(7)
302 #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING BIT(6)
303 #define HAL_RX_HT_SIG_INFO_INFO1_GI BIT(7)
326 #define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC BIT(3)
328 #define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS GENMASK(21, 10)
331 #define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING BIT(2)
333 #define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED BIT(8)
356 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM BIT(7)
362 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND BIT(0)
363 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE BIT(1)
364 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG BIT(2)
367 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING BIT(7)
368 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA BIT(8)
369 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC BIT(9)
370 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF BIT(10)
372 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM BIT(13)
373 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND BIT(15)
380 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG BIT(1)
382 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB BIT(4)
383 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR GENMASK(10, 5)
387 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB BIT(22)
389 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION BIT(25)
392 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_CODING BIT(7)
393 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB GENMASK(10, 8)
394 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA BIT(11)
395 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC BIT(12)
396 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXBF BIT(10)
398 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM BIT(15)
411 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID GENMASK(10, 0)
413 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING BIT(20)
420 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID GENMASK(10, 0)
422 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF BIT(19)
424 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM BIT(19)
425 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING BIT(20)
490 __le32 reserved1[10];
494 #define HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE BIT(16)
498 #define HAL_RX_RESP_REQ_INFO1_STBC BIT(27)
499 #define HAL_RX_RESP_REQ_INFO1_LDPC BIT(28)
500 #define HAL_RX_RESP_REQ_INFO1_IS_AMPDU BIT(29)
524 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID BIT(30)
525 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER BIT(31)
528 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC BIT(7)
529 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_DCM BIT(8)
582 /* HE radiotap HE-MU flags1 */
594 /* HE radiotap HE-MU flags2 */
623 #define HAL_RX_MPDU_ERR_FCS BIT(0)
624 #define HAL_RX_MPDU_ERR_DECRYPT BIT(1)
625 #define HAL_RX_MPDU_ERR_TKIP_MIC BIT(2)
626 #define HAL_RX_MPDU_ERR_AMSDU_ERR BIT(3)
627 #define HAL_RX_MPDU_ERR_OVERFLOW BIT(4)
628 #define HAL_RX_MPDU_ERR_MSDU_LEN BIT(5)
629 #define HAL_RX_MPDU_ERR_MPDU_LEN BIT(6)
630 #define HAL_RX_MPDU_ERR_UNENCRYPTED_FRAME BIT(7)